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High-Performance Method and Architecture for Attention Computation in DNN Inference. DNN 推断中注意力计算的高性能方法和架构
Pub Date : 2024-08-01 DOI: 10.1109/TBCAS.2024.3436837
Qi Cheng, Xiaofang Hu, He Xiao, Yue Zhou, Shukai Duan

In recent years, The combination of Attention mechanism and deep learning has a wide range of applications in the field of medical imaging. However, due to its complex computational processes, existing hardware architectures have high resource consumption or low accuracy, and deploying them efficiently to DNN accelerators is a challenge. This paper proposes an online-programmable Attention hardware architecture based on compute-in-memory (CIM) marco, which reduces the complexity of Attention in hardware and improves integration density, energy efficiency, and calculation accuracy. First, the Attention computation process is decomposed into multiple cascaded combinatorial matrix operations to reduce the complexity of its implementation on the hardware side; second, in order to reduce the influence of the non-ideal characteristics of the hardware, an online-programmable CIM architecture is designed to improve calculation accuracy by dynamically adjusting the weights; and lastly, it is verified that the proposed Attention hardware architecture can be applied for the inference of deep neural networks through Spice simulation. Based on the 100nm CMOS process, compared with the traditional Attention hardware architectures, the integrated density and energy efficiency are increased by at least 91.38 times, and latency and computing efficiency are improved by about 12.5 times.

近年来,注意力机制与深度学习的结合在医学影像领域有着广泛的应用。然而,由于其计算过程复杂,现有的硬件架构存在资源消耗大或精度低的问题,如何将其高效地部署到 DNN 加速器上是一个难题。本文提出了一种基于内存计算(CIM)marco 的在线可编程 Attention 硬件架构,降低了 Attention 在硬件上的复杂度,提高了集成密度、能效和计算精度。首先,将Attention计算过程分解为多个级联组合矩阵运算,以降低其在硬件端的实现复杂度;其次,为了降低硬件非理想特性的影响,设计了一种在线可编程CIM架构,通过动态调整权重来提高计算精度;最后,通过Spice仿真验证了所提出的Attention硬件架构可应用于深度神经网络推理。基于 100nm CMOS 工艺,与传统的 Attention 硬件架构相比,集成密度和能效至少提高了 91.38 倍,延迟和计算效率提高了约 12.5 倍。
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引用次数: 0
AI Accelerator With Ultralightweight Time-Period CNN-Based Model for Arrhythmia Classification 基于超轻时间周期 CNN 模型的人工智能加速器,用于心律失常分类。
Pub Date : 2024-07-30 DOI: 10.1109/TBCAS.2024.3435718
Shuenn-Yuh Lee;Ming-Yueh Ku;Wei-Cheng Tseng;Ju-Yi Chen
This work proposes a classification system for arrhythmias, aiming to enhance the efficiency of the diagnostic process for cardiologists. The proposed algorithm includes a naive preprocessing procedure for electrocardiography (ECG) data applicable to various ECG databases. Additionally, this work proposes an ultralightweight model for arrhythmia classification based on a convolutional neural network and incorporating R-peak interval features to represent long-term rhythm information, thereby improving the model's classification performance. The proposed model is trained and tested by using the MIT-BIH and NCKU-CBIC databases in accordance with the classification standards of the Association for the Advancement of Medical Instrumentation (AAMI), achieving high accuracies of 98.32% and 97.1%. This work applies the arrhythmia classification algorithm to a web-based system, thus providing a graphical interface. The cloud-based execution of automated artificial intelligence (AI) classification allows cardiologists and patients to view ECG wave conditions instantly, thereby remarkably enhancing the quality of medical examination. This work also designs a customized integrated circuit for the hardware implementation of an AI accelerator. The accelerator utilizes a parallelized processing element array architecture to perform convolution and fully connected layer operations. It introduces proposed hybrid stationary techniques, combining input and weight stationary modes to increase data reuse drastically and reduce hardware execution cycles and power consumption, ultimately achieving high-performance computing. This accelerator is implemented in the form of a chip by using the TSMC 180 nm CMOS process. It exhibits a power consumption of 122 µW, a classification latency of 6.8 ms, and an energy efficiency of 0.83 µJ/classification.
这项研究提出了一种心律失常分类系统,旨在提高心脏病专家诊断过程的效率。提出的算法包括一个适用于各种心电图数据库的心电图(ECG)数据天真预处理程序。此外,这项研究还提出了一种基于卷积神经网络的超轻量级心律失常分类模型,并结合 R 峰间期特征来表示长期节律信息,从而提高了模型的分类性能。根据美国医学仪器促进协会(AAMI)的分类标准,使用 MIT-BIH 和 NCKU-CBIC 数据库对提出的模型进行了训练和测试,取得了 98.32% 和 97.1% 的高准确率。这项工作将心律失常分类算法应用于基于网络的系统,从而提供了一个图形界面。基于云计算的人工智能(AI)自动分类执行可让心脏病专家和患者即时查看心电图波形情况,从而显著提高医疗检查质量。这项工作还为人工智能加速器的硬件实施设计了定制集成电路。该加速器利用并行化处理元件阵列架构来执行卷积和全连接层操作。它引入了拟议的混合静态技术,将输入和权重静态模式相结合,大幅提高了数据重用率,减少了硬件执行周期和功耗,最终实现了高性能计算。该加速器采用台积电 180 纳米 CMOS 工艺,以芯片形式实现。它的功耗为 122 μW,分类延迟为 6.8 ms,能效为 0.83 μJ/分类。
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引用次数: 0
Active Neural Interface Circuits and Systems for Selective Control of Peripheral Nerves: A Review 用于选择性控制外周神经的主动神经接口电路和系统:综述。
Pub Date : 2024-07-17 DOI: 10.1109/TBCAS.2024.3430038
Maryam Habibollahi;Dai Jiang;Henry Thomas Lancashire;Andreas Demosthenous
Interfaces with peripheral nerves have been widely developed to enable bioelectronic control of neural activity. Peripheral nerve neuromodulation shows great potential in addressing motor dysfunctions, neurological disorders, and psychiatric conditions. The integration of high-density neural electrodes with stimulation and recording circuits poses a challenge in the design of neural interfaces. Recent advances in active electrode strategies have achieved improved reliability and performance by implementing in-situ control, stimulation, and recording of neural fibers. This paper presents an overview of state-of-the-art neural interface systems that comprise a range of neural electrodes, neurostimulators, and bio-amplifier circuits, with a special focus on interfaces for the peripheral nerves. A discussion on the efficacy of active electrode systems and recommendations for future directions conclude this paper.
为实现对神经活动的生物电子控制,与周围神经的接口已得到广泛开发。外周神经调控在解决运动功能障碍、神经系统疾病和精神疾病方面显示出巨大的潜力。高密度神经电极与刺激和记录电路的整合给神经接口的设计带来了挑战。有源电极策略的最新进展通过实现神经纤维的原位控制、刺激和记录,提高了可靠性和性能。本文概述了最先进的神经接口系统,包括一系列神经电极、神经刺激器和生物放大器电路,并特别关注外周神经接口。本文最后讨论了有源电极系统的功效,并对未来发展方向提出了建议。
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引用次数: 0
A Power-Efficient Envelope-Detector-Less Amplitude-Shift-Keying Forward Telemetry for Wirelessly Powered Biomedical Devices. 用于无线供电生物医学设备的高能效无包络探测器移幅键控前向遥测技术。
Pub Date : 2024-07-12 DOI: 10.1109/TBCAS.2024.3427396
Hyun-Su Lee, Hyung-Min Lee

This paper proposes an envelope-detector-less (EDL) amplitude-shift-keying (ASK) forward telemetry (FT) demodulator for wireless power/data transfer (WPDT) systems. The EDL ASK FT demodulator can substitute bulky and power-hungry components, which are an envelope detector and an analog comparator in the conventional ASK FT demodulator, with a digital controller, reducing both power dissipation and chip area. The proposed demodulator shares the gate control signals of pass transistors, which are used in an ac-dc regulator for wireless power reception, to maintain a constant load voltage while efficiently demodulating the forward telemetry data. Also, a proposed digital cleaner in the EDL demodulator refines this control signal into a wide pulse without suffering from resonant frequency noise, while a synchronizer can align its frequency with the data rate and resonant frequency. The 0.25-μm CMOS prototype chip of the proposed power-path-less EDL ASK FT demodulator, equipped with the ac-dc regulator, demonstrates a significant 38.2% reduction in power dissipation compared to the conventional ASK FT demodulator. Moreover, the EDL ASK FT demodulator occupies only 0.023-mm2 silicon area and achieves a low bit error rate (BER) less than 10-4 while maintaining a regulated voltage of 4.5 V on the load.

本文提出了一种用于无线功率/数据传输(WPDT)系统的无包络探测器(EDL)振幅偏移键控(ASK)前向遥测(FT)解调器。EDL ASK FT 解调器可以用数字控制器替代传统 ASK FT 解调器中的包络检测器和模拟比较器等体积庞大、功耗高的元件,从而减少功耗和芯片面积。拟议的解调器共享用于无线功率接收交流-直流稳压器的通路晶体管的栅极控制信号,以便在有效解调前向遥测数据的同时保持恒定的负载电压。此外,EDL 解调器中的数字清零器可将该控制信号细化为宽脉冲,而不会受到谐振频率噪声的影响,同时同步器可使其频率与数据速率和谐振频率保持一致。与传统的 ASK FT 解调器相比,配备交流-直流稳压器的无功率路径 EDL ASK FT 解调器 0.25μm CMOS 原型芯片的功耗大幅降低了 38.2%。此外,EDL ASK FT 解调器仅占 0.023 平方毫米的硅面积,误码率 (BER) 低于 10-4,同时负载上的稳压电压保持在 4.5 V。
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引用次数: 0
A Wearable Dual-Mode Probe for Image-Guided Closed-Loop Ultrasound Neuromodulation. 用于图像引导闭环超声神经调制的可穿戴双模探头
Pub Date : 2024-07-11 DOI: 10.1109/TBCAS.2024.3425858
Junjun Huan, Vida Pashaei, Steve J A Majerus, Swarup Bhunia, Soumyajit Mandal

Low-intensity focused ultrasound (FUS) is an emerging non-invasive and spatially/temporally precise method for modulating the firing rates and patterns of peripheral nerves. This paper describes an image-guided platform for chronic and patient-specific FUS neuromodulation. The system uses custom wearable probes containing separate ultrasound imaging and modulation transducer arrays realized using piezoelectric transducers assembled on a flexible printed circuit board (PCB). Dual-mode probes operating around 4 MHz (imaging) and 1.3 MHz (modulation) were fabricated and tested on tissue phantoms. The resulting B-mode images were analyzed using a template-matching algorithm to estimate the location of the target nerve and then direct the modulation beam toward the target. The ultrasound transmit voltage used to excite the modulation array was optimized in real-time by automatically regulating functional feedback signals (the average rates of emulated muscle twitches detected by an on-board motion sensor) through a proportional and integral (PI) controller, thus providing robustness to inter-subject variability and probe positioning errors. The proposed closed-loop neuromodulation paradigm was experimentally demonstrated in vitro using an active tissue phantom that integrates models of the posterior tibial nerve and nearby blood vessels together with embedded sensors and actuators.

低强度聚焦超声(FUS)是一种新兴的非侵入性、空间/时间精确调节周围神经发射率和模式的方法。本文介绍了一种用于慢性和特定患者 FUS 神经调控的图像引导平台。该系统使用定制的可穿戴探头,其中包含独立的超声成像和调制换能器阵列,这些阵列使用组装在柔性印刷电路板(PCB)上的压电换能器实现。双模探头的工作频率分别为 4 MHz(成像)和 1.3 MHz(调制),已制作完成并在组织模型上进行了测试。利用模板匹配算法对生成的 B 型图像进行分析,以估计靶神经的位置,然后将调制束导向靶点。用于激励调制阵列的超声波发射电压通过一个比例和积分(PI)控制器自动调节功能反馈信号(由板载运动传感器检测到的模拟肌肉抽搐的平均速率)进行实时优化,从而提供对受试者间变异性和探头定位误差的鲁棒性。所提出的闭环神经调控范例在体外实验中得到了验证,该范例使用了一个主动组织模型,该模型将胫后神经和附近血管的模型与嵌入式传感器和致动器集成在一起。
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引用次数: 0
Low-Power Fully Integrated 256-Channel Nanowire Electrode-on-Chip Neural Interface for Intracellular Electrophysiology 用于细胞内电生理学的低功耗全集成 256 通道纳米线片上电极神经接口。
Pub Date : 2024-07-10 DOI: 10.1109/TBCAS.2024.3407794
Jun Wang;Ren Liu;Youngbin Tchoe;Alessio Paolo Buccino;Akshay Paul;Deborah Pre;Agnieszka D'Antonio-Chronowska;Frazer A. Kelly;Anne G. Bang;Chul Kim;Shadi Dayeh;Gert Cauwenberghs
Intracellular electrophysiology, a vital and versatile technique in cellular neuroscience, is typically conducted using the patch-clamp method. Despite its effectiveness, this method poses challenges due to its complexity and low throughput. The pursuit of multi-channel parallel neural intracellular recording has been a long-standing goal, yet achieving reliable and consistent scaling has been elusive because of several technological barriers. In this work, we introduce a micropower integrated circuit, optimized for scalable, high-throughput in vitro intrinsically intracellular electrophysiology. This system is capable of simultaneous recording and stimulation, implementing all essential functions such as signal amplification, acquisition, and control, with a direct interface to electrodes integrated on the chip. The electrophysiology system-on-chip (eSoC), fabricated in 180nm CMOS, measures 2.236 mm $times$ 2.236 mm. It contains four 8 $times$ 8 arrays of nanowire electrodes, each with a 50 $mu$m pitch, placed over the top-metal layer on the chip surface, totaling 256 channels. Each channel has a power consumption of 0.47 $mu$W, suitable for current stimulation and voltage recording, and covers 80 dB adjustable range at a sampling rate of 25 kHz. Experimental recordings with the eSoC from cultured neurons in vitro validate its functionality in accurately resolving chemically induced multi-unit intracellular electrical activity.
细胞内电生理学是细胞神经科学中一项重要的多功能技术,通常采用膜片钳法进行研究。尽管这种方法非常有效,但由于其复杂性和低通量,也带来了挑战。追求多通道并行神经细胞内记录是一个长期目标,但由于一些技术障碍,实现可靠和一致的扩展一直难以实现。在这项工作中,我们介绍了一种微功率集成电路,它针对可扩展、高通量的体外细胞内电生理学进行了优化。该系统能够同时进行记录和刺激,实现信号放大、采集和控制等所有基本功能,并具有与集成在芯片上的电极的直接接口。电生理学片上系统(eSoC)采用 180 纳米 CMOS 制造,尺寸为 2.236 毫米 × 2.236 毫米。它包含四个 8 × 8 的纳米线电极阵列,每个阵列的间距为 50 μm,放置在芯片表面的顶层金属层上,共有 256 个通道。每个通道的功耗为 0.47 μW,适用于电流刺激和电压记录,采样率为 25 kHz,可调范围为 80 dB。使用 eSoC 对体外培养的神经元进行的实验记录验证了它在精确分辨化学诱导的多单元细胞内电活动方面的功能。
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引用次数: 0
A Standard-Cell-Based Neuro-Inspired Integrate-and-Fire Analog-to-Time Converter for Biological and Low-Frequency Signals — Comparison With Analog Version 用于生物和低频信号的基于标准细胞的神经启发式集成与发射模-时转换器--与模拟版本的比较。
Pub Date : 2024-07-04 DOI: 10.1109/TBCAS.2024.3422282
Miguel Lima Teixeira;João P. Oliveira;José C. Príncipe;João Goes
Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 $boldsymbol{mu}$W and 53 $boldsymbol{mu}$W, and an energy per pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy per pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.
连续时间异步数据转换器,即模数转换器和模时转换器,可用于某些类型的应用,如处理信息稀疏的生物信号。这些转换器中的一个特殊例子就是受神经系统启发而产生的积分-发射转换器(IFC)。如果有可能开发出一种基于标准单元(SCB)的 IFC 电路,使其在先进技术节点中性能良好,那么它将受益于 SCB 电路设计的简便性,并可在广泛使用的现场可编程门阵列(FPGA)中实现。因此,本文提出了两个在 130 纳米 CMOS 标准工艺中设计和原型开发的 IFC 电路。第一个是新型 SCB 开环动态 IFC。后者是采用传统模块的闭环模拟 IFC。本文对这两种 IFC 电路进行了比较。SCB 和模拟 IFC 的功耗分别为 59 μW 和 53 μW,每个脉冲的能量分别为 18 pJ 和 1060 pJ。据报告,SCB IFC 是 IFC 电路中单位脉冲能耗最低的电路之一。据我们所知,全差分模拟 IFC 是同类电路中的首创。此外,它们不需要外部时钟。SCB 和模拟 IFC 的峰峰值幅度分别为 1.6 mV 至 28 mV 和 0.6 mV 至 2.4 mV,频率范围分别为 2 Hz 至 42 kHz 和 10 Hz 至 4 kHz。归一化有效值转换和重建误差较低,低于 5.2%。SCB 和模拟 IFC 的最大脉冲密度(平均发射率)分别为 3300 kHz 和 50 kHz。
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引用次数: 0
A 62.2dB SNDR Event-Driven Level-Crossing ADC with SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical Signal Acquisition. 用于时间稀疏生物医学信号采集的 62.2dB SNDR 事件驱动电平交叉 ADC,带有 SAR 辅助延迟补偿环路。
Pub Date : 2024-07-04 DOI: 10.1109/TBCAS.2024.3423366
Mengyu Li, Yi Huo, Shuang Song, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan

This paper proposed an event-driven clockless level-crossing ADC (LC-ADC) suitable for biomedical applications. Thanks to the LC loop, the sampling rate of the converter automatically adapts to the input activities. Activity-dependent power consumption and data compression can thus be realized, saving system power, especially during time-sparse signal acquisition. Meanwhile, a SAR-assisted loop is exploited to resolve the loop-delay-induced distortion in conventional LC-ADC. Therefore, the resolution and power efficiency of the LC-ADC are improved effectively while maintaining the event-driven feature. Implemented in a 55nm process, the proposed LC-ADC achieves a scalable power consumption and a peak SNDR of 62.2dB for a 20kHz input. It also achieves a Walden FoM of 29.7fJ/conv.-step and a Schreier FoM of 158.6dB, which is best in class, without using off-chip calibration. Sub μW power is realized when the input frequency is below 1.5kHz. The proposed LC-ADC is also verified by simulated electrocardiogram (ECG), neural spike, and electromyogram (EMG) signals. It provides a ~7X data compression for ECG input, providing an attractive solution for time-sparse signal acquisition in biomedical applications.

本文提出了一种适用于生物医学应用的事件驱动无时钟电平转换器(LC-ADC)。通过 LC 环路,转换器的采样率可自动适应输入活动。因此,可以实现与活动相关的功耗和数据压缩,从而节省系统功耗,尤其是在时间稀疏信号采集期间。同时,利用 SAR 辅助环路解决了传统 LC-ADC 中环路延迟引起的失真问题。因此,在保持事件驱动特性的同时,LC-ADC 的分辨率和能效得到了有效提高。采用 55 纳米工艺实现的 LC-ADC 功耗可调,20kHz 输入的峰值 SNDR 为 62.2dB。它还实现了 29.7fJ/conv.-step 的 Walden FoM 和 158.6dB 的 Schreier FoM,这在同类产品中是最好的,而且无需使用片外校准。当输入频率低于 1.5kHz 时,可实现低于 μW 的功率。拟议的 LC-ADC 还通过模拟心电图(ECG)、神经尖峰和肌电图(EMG)信号进行了验证。它为心电图输入提供了约 7 倍的数据压缩,为生物医学应用中的时间稀疏信号采集提供了有吸引力的解决方案。
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引用次数: 0
Low-Power Analog Integrated Architecture of the Voting Classification Algorithm for Diabetes Disease Prediction 用于糖尿病疾病预测的投票分类算法的低功耗模拟集成架构。
Pub Date : 2024-07-02 DOI: 10.1109/TBCAS.2024.3421313
Vassilis Alimisis;Charis Aletraris;Nikolaos P. Eleftheriou;Emmanouil Anastasios Serlis;Alex James;Paul P. Sotiriadis
A low-power ($boldsymbol{sim}$ 600nW), fully analog integrated architecture for a voting classification algorithm is introduced. It can effectively handle multiple-input features, maintaining exceptional levels of accuracy and with very low power consumption. The proposed architecture is based on a versatile Voting algorithm that selectively incorporates one of three key classification models: Bayes or Centroid, or, the Learning Vector Quantization model; all of which are implemented using Gaussian-likelihood and Euclidean distance function circuits, as well as a current comparison circuit. To evaluate the proposed architecture, a comprehensive comparison with popular analog classifiers is performed, using real-life diabetes dataset. All model architectures were trained using Python and compared with the software-based classifiers. The circuit implementations were performed using the TSMC $90$ nm CMOS process technology and the Cadence IC Suite was utilized for the design, schematic and post-layout simulations. The proposed classifiers achieved sensitivity of ${boldsymbol{geq}}96.7%$ and specificity of ${boldsymbol{geq}}89.7%$.
本文介绍了一种用于投票分类算法的低功耗(∼ 600nW)全模拟集成架构。它能有效处理多输入特征,保持极高的准确度,而且功耗极低。所提出的架构基于一种多功能投票算法,该算法有选择地结合了三种关键分类模型之一:所有这些都是通过高斯似然和欧氏距离函数电路以及电流比较电路实现的。为了评估所提出的架构,我们使用真实的糖尿病数据集与流行的模拟分类器进行了全面比较。所有模型架构都使用 Python 进行了训练,并与基于软件的分类器进行了比较。电路实现采用台积电 90 纳米 CMOS 工艺技术,并使用 Cadence IC Suite 进行设计、原理图和布局后仿真。建议的分类器灵敏度≥ 96.7%,特异度≥ 89.7%。
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引用次数: 0
A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-$mu$W Robust Wearable Sensing 用于亚微瓦稳健型可穿戴传感技术的 10 通道、120 nW/通道可重构电容数字转换器。
Pub Date : 2024-07-01 DOI: 10.1109/TBCAS.2024.3420871
Omar Faruqe;Daehyun Lee;Natalie B. Ownby;Benton H. Calhoun
This paper presents a 10-channel, 120 nW/channel, reconfigurable capacitance-to-digital converter (CDC) enabling sub-$mu$W wearable sensing applications. The proposed multi-channel architecture supports 10 channels with a shared reconfigurable 6-bit differential analog-to-digital converter (ADC). The reconfigurable nature of the CDC enables adaptive sensing range and sensing speed based on the target application. Furthermore, the architecture performs both on/off-chip parasitic correction and baseline calibration to measure the change in capacitance ($mathbf{Delta C}$), excluding baseline and parasitic capacitances. The experimental results show the measurement range of $mathbf{Delta C}$ are 5.34 pF for 1x sensitivity and 1.8 pF for 3x sensitivity respectively. The capacitive divider-based architecture excludes power-hungry operational trans-impedance amplifiers for capacitance to voltage conversion, and the architecture supports programmable channel access to activate or deactivate each channel independently. The random interrupt protection logic avoids any broken sample or data error in a sampling window. Additionally, the channel monitoring logic helps keep track of specific channel information. The measured silicon result shows a total power consumption of 1.2 $mathbf{mu}$W for 1.6 kHz sampling frequency when driven by a 32 kHz clock, which is 8.6x less than prior works. The CDC is also tested with DMMP (dimethyl-methylphosphonate) gas sensor in gas chromatography (GC). Implemented in 65 nm CMOS process, the 10-channel CDC occupies 0.251 $mathbf{mm^{2}}$ of active area (0.0251 $mathbf{mm^{2}}$/Ch).
本文介绍了一种 10 通道、120 nW/通道的可重构电容数字转换器(CDC),可实现亚微瓦级的可穿戴传感应用。所提出的多通道架构支持 10 个通道,共享一个可重新配置的 6 位差分模数转换器 (ADC)。CDC 的可重构特性可根据目标应用实现自适应传感范围和传感速度。此外,该架构还执行片上/片外寄生校正和基线校准,以测量电容变化(ΔC),不包括基线电容和寄生电容。实验结果表明,1 倍灵敏度和 3 倍灵敏度的 ΔC 测量范围分别为 5.34 pF 和 1.8 pF。基于电容分压器的架构排除了将电容转换为电压的高功耗运算跨阻放大器,该架构支持可编程通道访问,可独立激活或停用每个通道。随机中断保护逻辑可避免采样窗口中出现任何采样中断或数据错误。此外,通道监控逻辑有助于跟踪特定通道信息。硅测量结果表明,在 32 kHz 时钟驱动下,1.6 kHz 采样频率的总功耗为 1.2 μW,比以前的产品降低了 8.6 倍。CDC 还在气相色谱仪 (GC) 中与 DMMP(二甲基甲基膦酸盐)气体传感器进行了测试。10 通道 CDC 采用 65 纳米 CMOS 工艺实现,占地面积为 0.251 平方毫米(0.0251 平方毫米/时)。
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引用次数: 0
期刊
IEEE transactions on biomedical circuits and systems
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