Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128350
Yingzhe Wang, Xuefeng Zheng, Jiaduo Zhu, Shengrui Xu, Xiao-hua Ma, Jincheng Zhang, Y. Hao, Linlin Xu, J. Dai, Peixian Li
This work provides an intensive investigation of defect evolution in the degradation process induced by electrical stress of AlGaN-based deep ultraviolet light emitting diodes. The reduced optical power and the increased leakage current are directly related to a new generated electron trap B with an energy level in the range of 0.25-0.38 eV, which is extracted from deep level transient spectroscopy (DLTS) measurement. The significantly increased "yellow" band peak in PL spectra and the linear relation between DLTS signal and pulse width indicate that, defect B corresponds to Ga vacancy along dislocation. The increase of Ga vacancy is accompanied with a decrease of hole trap A with energy level of 0.29-0.34 eV. Combining with first-principle calculation and experimental results, it is demonstrated that the generation of Ga vacancy is originated from the variation in Mg-related defect along dislocation.
{"title":"Evolution of Defect in AlGaN-based Deep Ultraviolet Light Emitting Diodes During Electrical Stress","authors":"Yingzhe Wang, Xuefeng Zheng, Jiaduo Zhu, Shengrui Xu, Xiao-hua Ma, Jincheng Zhang, Y. Hao, Linlin Xu, J. Dai, Peixian Li","doi":"10.1109/IRPS45951.2020.9128350","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128350","url":null,"abstract":"This work provides an intensive investigation of defect evolution in the degradation process induced by electrical stress of AlGaN-based deep ultraviolet light emitting diodes. The reduced optical power and the increased leakage current are directly related to a new generated electron trap B with an energy level in the range of 0.25-0.38 eV, which is extracted from deep level transient spectroscopy (DLTS) measurement. The significantly increased \"yellow\" band peak in PL spectra and the linear relation between DLTS signal and pulse width indicate that, defect B corresponds to Ga vacancy along dislocation. The increase of Ga vacancy is accompanied with a decrease of hole trap A with energy level of 0.29-0.34 eV. Combining with first-principle calculation and experimental results, it is demonstrated that the generation of Ga vacancy is originated from the variation in Mg-related defect along dislocation.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115023540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129591
Y. Qu, Jiwu Lu, Junkang Li, Zhuo Chen, Jie Zhang, Chunlong Li, Shiuh-Wuu Lee, Yi Zhao
Self-heating effect (SHE) in aggressively scaled SOI FinFETs is experimentally and quantitatively investigated by utilizing a sub-nanosecond (ns) characterization technique. A 3D mapping of the channel temperature rise is obtained under different heating (the transistor is turned ON with a current flowing through the channel) and cooling (the transistor is turned OFF) time ranging from 500 ps to 10 μs. It is observed that SHE could be alleviated or almost totally suppressed when the heating time is small enough and the cooling time is reasonably long. Furthermore, for the first time, the real-time channel temperature is electrically monitored with a sub-nanosecond resolution during the whole stress phase. Thus, the hot carrier degradation (HCD) lifetime can be precisely projected no matter SHE exists or not during the stress phases of HCD stress. In addition, the impact of SHE during HCI stress is also simulated in the real digital circuit applications.
{"title":"In-Situ Monitoring of Self-Heating Effect in Aggressively Scaled FinFETs and Its Quantitative Impact on Hot Carrier Degradation Under Dynamic Circuit Operation","authors":"Y. Qu, Jiwu Lu, Junkang Li, Zhuo Chen, Jie Zhang, Chunlong Li, Shiuh-Wuu Lee, Yi Zhao","doi":"10.1109/IRPS45951.2020.9129591","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129591","url":null,"abstract":"Self-heating effect (SHE) in aggressively scaled SOI FinFETs is experimentally and quantitatively investigated by utilizing a sub-nanosecond (ns) characterization technique. A 3D mapping of the channel temperature rise is obtained under different heating (the transistor is turned ON with a current flowing through the channel) and cooling (the transistor is turned OFF) time ranging from 500 ps to 10 μs. It is observed that SHE could be alleviated or almost totally suppressed when the heating time is small enough and the cooling time is reasonably long. Furthermore, for the first time, the real-time channel temperature is electrically monitored with a sub-nanosecond resolution during the whole stress phase. Thus, the hot carrier degradation (HCD) lifetime can be precisely projected no matter SHE exists or not during the stress phases of HCD stress. In addition, the impact of SHE during HCI stress is also simulated in the real digital circuit applications.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131111675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129299
D. Ji, B. Ercan, Garrett Benson, A. Newaz, S. Chowdhury
This abstract presents a study on the avalanche capability of GaN p-i-n diode leading to the achievement of 60A/W, 278V GaN avalanche photodiode. The GaN p-i-n diode fabricated on a free-standing GaN substrate was avalanche capable due to optimal edge termination. Both electrical and optical characterizations were conducted to validate the occurrence of avalanche in these devices. The device showed a positive temperature coefficient of breakdown voltage, which follows the nature of avalanche breakdown. The positive coefficient was measured to be 3.85 ×10-4 K-1 (0.1V/K) under a measurement temperature ranges from 300 K to 525 K. Moreover, the fabricated device showed excellent performance as an avalanche photo detector with record device metrics: (1) record high photoresponsivity of 60 A/W; (2) high optical gain of 105; and (3) low cark current. Robust avalanche is a key requirement in various device applications and necessary for their reliable operation.
{"title":"Robust avalanche in GaN leading to record performance in avalanche photodiode","authors":"D. Ji, B. Ercan, Garrett Benson, A. Newaz, S. Chowdhury","doi":"10.1109/IRPS45951.2020.9129299","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129299","url":null,"abstract":"This abstract presents a study on the avalanche capability of GaN p-i-n diode leading to the achievement of 60A/W, 278V GaN avalanche photodiode. The GaN p-i-n diode fabricated on a free-standing GaN substrate was avalanche capable due to optimal edge termination. Both electrical and optical characterizations were conducted to validate the occurrence of avalanche in these devices. The device showed a positive temperature coefficient of breakdown voltage, which follows the nature of avalanche breakdown. The positive coefficient was measured to be 3.85 ×10-4 K-1 (0.1V/K) under a measurement temperature ranges from 300 K to 525 K. Moreover, the fabricated device showed excellent performance as an avalanche photo detector with record device metrics: (1) record high photoresponsivity of 60 A/W; (2) high optical gain of 105; and (3) low cark current. Robust avalanche is a key requirement in various device applications and necessary for their reliable operation.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134061944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129306
Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Hyungcheol Shin, Haesoo Kim, Gil-Bok Choi, M. Seo, K. Noh
For the first time, we analyzed the effect of program/erase (P/E) cycles on short term retention in 3-D NAND flash memory. Trap-assisted tunneling (TAT) component with relatively large time-constant (τ) was found after P/E cycle stress. We have confirmed that the charge failure mechanisms consist of four components. Short term retention data measured at various temperatures and at several program verify levels (PV) for two patterns were analyzed and separated using our stretched exponential model. Finally, the activation energy (Ea) of each charge failure mechanism was extracted by the Arrhenius law and the magnitudes of Ea were compared as a function of P/E cycle counts.
{"title":"Modeling of Charge Failure Mechanisms during the Short Term Retention Depending on Program/Erase Cycle Counts in 3-D NAND Flash Memories","authors":"Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Hyungcheol Shin, Haesoo Kim, Gil-Bok Choi, M. Seo, K. Noh","doi":"10.1109/IRPS45951.2020.9129306","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129306","url":null,"abstract":"For the first time, we analyzed the effect of program/erase (P/E) cycles on short term retention in 3-D NAND flash memory. Trap-assisted tunneling (TAT) component with relatively large time-constant (τ) was found after P/E cycle stress. We have confirmed that the charge failure mechanisms consist of four components. Short term retention data measured at various temperatures and at several program verify levels (PV) for two patterns were analyzed and separated using our stretched exponential model. Finally, the activation energy (Ea) of each charge failure mechanism was extracted by the Arrhenius law and the magnitudes of Ea were compared as a function of P/E cycle counts.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129736924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129638
K. Ramkumar, V. Prabhakar, V. Agrawal, L. Hinh, S. Saha, S. Samanta, R. Kapre
Reliability of 40nm SONOS (Si-Oxide-Nitride-Oxide-Si) based non-volatile memory (NVM) cell has been evaluated for analog memory to perform neuromorphic computing. Process flow and smart-write algorithms were developed to tune key reliability parameters like retention and noise performance for this application. Their optimization to meet the product reliability requirements are also discussed. The performance of SONOS was evaluated on mini test arrays as well as actual memory arrays and the retention data obtained are discussed
{"title":"Reliability Aspects of SONOS Based Analog Memory for Neuromorphic Computing","authors":"K. Ramkumar, V. Prabhakar, V. Agrawal, L. Hinh, S. Saha, S. Samanta, R. Kapre","doi":"10.1109/IRPS45951.2020.9129638","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129638","url":null,"abstract":"Reliability of 40nm SONOS (Si-Oxide-Nitride-Oxide-Si) based non-volatile memory (NVM) cell has been evaluated for analog memory to perform neuromorphic computing. Process flow and smart-write algorithms were developed to tune key reliability parameters like retention and noise performance for this application. Their optimization to meet the product reliability requirements are also discussed. The performance of SONOS was evaluated on mini test arrays as well as actual memory arrays and the retention data obtained are discussed","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132335190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128320
J. P. Ashton, P. Lenahan, D. Lichtenwalner, A. Lelis
4H-SiC metal-oxide-semiconductor field-effect transistors have a substantially lower effective channel mobility than silicon-based counterparts. Nitric oxide annealing has been primarily utilized to provide an order of magnitude improvement in the effective channel mobility. Barium interface layers provide an additional doubling of the mobility over nitric oxide anneals. However, barium-based 4H-SiC transistors show more susceptibility to oxide leakage. We have investigated the atomic scale mechanisms of oxide leakage in barium-based devices with electrically detected magnetic resonance. We observe the presence of E’ centers within the oxides of modestly stressed devices. Our measurements directly demonstrate that these E’ centers are important and very likely the dominating cause of these leakage currents. In conventional silicon-based devices, E’ centers are known to be important defects in reliability issues such as bias temperature instabilities and stress-induced leakage currents.
{"title":"Leakage Currents and E’ Centers in 4H-SiC MOSFETs with Barium Passivation","authors":"J. P. Ashton, P. Lenahan, D. Lichtenwalner, A. Lelis","doi":"10.1109/IRPS45951.2020.9128320","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128320","url":null,"abstract":"4H-SiC metal-oxide-semiconductor field-effect transistors have a substantially lower effective channel mobility than silicon-based counterparts. Nitric oxide annealing has been primarily utilized to provide an order of magnitude improvement in the effective channel mobility. Barium interface layers provide an additional doubling of the mobility over nitric oxide anneals. However, barium-based 4H-SiC transistors show more susceptibility to oxide leakage. We have investigated the atomic scale mechanisms of oxide leakage in barium-based devices with electrically detected magnetic resonance. We observe the presence of E’ centers within the oxides of modestly stressed devices. Our measurements directly demonstrate that these E’ centers are important and very likely the dominating cause of these leakage currents. In conventional silicon-based devices, E’ centers are known to be important defects in reliability issues such as bias temperature instabilities and stress-induced leakage currents.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"17 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116444548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128911
L. Luo, K. Shubhakar, S. Mei, N. Raghavan, Fan Zhang, D. Shum, K. Pey
The electrical reliability study of 40 nm embedded non-volatile memory (NVM) technology was widely studied with respect to data retention and cycling. However, intrinsic reliability of NVM gate oxide was rarely reported. Here, we present key results on soft breakdown (SBD) and hard breakdown (HBD) events in split-gate NVM (SG-NVM) together with most likely breakdown (BD) location in erase gate (EG) oxide. A new method of nanoprobe electrical stressing was applied on EG oxide and physical failures were successfully observed using transmission electron microscopy (TEM). Combined kinetic Monte Carlo (KMC) and finite element method (FEM) simulation results show that the BD occurs in EG oxide associated with high-electric field during erase operation. The HBD path can be clearly identified and shows melting of whole W plug and copper, connected to erase Poly-Si gate on top of EG oxide. Thus, our results provide critical information to identify the reliability weak link of the SG-NVM device and, electrical and physical behavior of the EG oxide during the SBD and HBD events.
{"title":"Reliability and Breakdown Study of Erase Gate Oxide in Split-Gate Non-Volatile Memory Device","authors":"L. Luo, K. Shubhakar, S. Mei, N. Raghavan, Fan Zhang, D. Shum, K. Pey","doi":"10.1109/IRPS45951.2020.9128911","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128911","url":null,"abstract":"The electrical reliability study of 40 nm embedded non-volatile memory (NVM) technology was widely studied with respect to data retention and cycling. However, intrinsic reliability of NVM gate oxide was rarely reported. Here, we present key results on soft breakdown (SBD) and hard breakdown (HBD) events in split-gate NVM (SG-NVM) together with most likely breakdown (BD) location in erase gate (EG) oxide. A new method of nanoprobe electrical stressing was applied on EG oxide and physical failures were successfully observed using transmission electron microscopy (TEM). Combined kinetic Monte Carlo (KMC) and finite element method (FEM) simulation results show that the BD occurs in EG oxide associated with high-electric field during erase operation. The HBD path can be clearly identified and shows melting of whole W plug and copper, connected to erase Poly-Si gate on top of EG oxide. Thus, our results provide critical information to identify the reliability weak link of the SG-NVM device and, electrical and physical behavior of the EG oxide during the SBD and HBD events.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116623072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129212
Hyeong-Sub Song, S. Eadi, Hyun-Dong Song, Hyun-Woong Choi, Ga-Won Lee, H. Lee
The reduction of random telegraph noise (RTN) at the circuit level using common noise canceling methods, such as correlated double sampling (CDS), has proven difficult. Therefore, reduction of RTN at the device level is increasingly being investigated. In this paper, RTN characteristics are analyzed source follower transistor. Impacts of RTN levels are investigated before and after intentional hot carrier agings (HCA). Unlike channel hot carrier (CHC) stress, which showed small changes in RTN characteristics or decreased RTN levels, drain avalanche hot carrier (DAHC) stress resulted in increasing power spectral density levels below 10 Hz. This implies low-frequency RTN is closely related to interface charge density (Nit). The Nit generated by DAHC would results in the increase of influence of RTN on active traps in channel near drain junction. On the other hands, in case of CHC, it seems that the RTN characteristic is weakened by changing the dominant current path distributed around the active trap by charged trap.
{"title":"Investigation of Random Telegraph Noise Characteristics with Intentional Hot Carrier Aging","authors":"Hyeong-Sub Song, S. Eadi, Hyun-Dong Song, Hyun-Woong Choi, Ga-Won Lee, H. Lee","doi":"10.1109/IRPS45951.2020.9129212","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129212","url":null,"abstract":"The reduction of random telegraph noise (RTN) at the circuit level using common noise canceling methods, such as correlated double sampling (CDS), has proven difficult. Therefore, reduction of RTN at the device level is increasingly being investigated. In this paper, RTN characteristics are analyzed source follower transistor. Impacts of RTN levels are investigated before and after intentional hot carrier agings (HCA). Unlike channel hot carrier (CHC) stress, which showed small changes in RTN characteristics or decreased RTN levels, drain avalanche hot carrier (DAHC) stress resulted in increasing power spectral density levels below 10 Hz. This implies low-frequency RTN is closely related to interface charge density (Nit). The Nit generated by DAHC would results in the increase of influence of RTN on active traps in channel near drain junction. On the other hands, in case of CHC, it seems that the RTN characteristic is weakened by changing the dominant current path distributed around the active trap by charged trap.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116725925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129232
S. Maaß, H. Reisinger, T. Aichinger, G. Rescher
We study the bias temperature instability (BTI) behavior of 4H-SiC trench MOSFETs after application of very high gate-voltage pulses at high temperatures. These pulses correspond to an electric field sufficiently high to trigger impact ionization and the associated effects in gate oxides. BTI effects measured in the form of threshold voltage or VTh drifts are more severe after these pulses as compared to BTI after voltage pulses that are sufficiently below the impact ionization regime. The effects shown in this paper impose an upper limit on electric fields applied to the gate during, e.g., device screening during front-end processing, but also in the application.
{"title":"Influence of high-voltage gate-oxide pulses on the BTI behavior of SiC MOSFETs","authors":"S. Maaß, H. Reisinger, T. Aichinger, G. Rescher","doi":"10.1109/IRPS45951.2020.9129232","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129232","url":null,"abstract":"We study the bias temperature instability (BTI) behavior of 4H-SiC trench MOSFETs after application of very high gate-voltage pulses at high temperatures. These pulses correspond to an electric field sufficiently high to trigger impact ionization and the associated effects in gate oxides. BTI effects measured in the form of threshold voltage or VTh drifts are more severe after these pulses as compared to BTI after voltage pulses that are sufficiently below the impact ionization regime. The effects shown in this paper impose an upper limit on electric fields applied to the gate during, e.g., device screening during front-end processing, but also in the application.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131884216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128308
T. Kemmer, M. Dammann, M. Baeumler, V. Polyakov, P. Brückner, H. Konstanzer, R. Quay, O. Ambacher
A systematic investigation of the effect of temperature and electric field on the degradation of 100 nm AlGaN/GaN HEMTs stressed under on- and off-state conditions has been carried out. The shape of the degradation behavior is analyzed and compared between stress conditions. The shape parameter of an Avrami-model was found to be reduced at higher temperatures. Failure analysis was performed by delayering with subsequent SEM and AFM investigation of the semiconductor surface. All devices showed surface damage in the vicinity of the drain-sided gate-edge. Devices stressed at high voltage and high temperature exhibited more and deeper pits than devices stressed at low drain-bias and low temperature, even though all devices have been stressed to the same electrical degradation of 10 % decrease in IDSS.
{"title":"Failure Analysis of 100 nm AlGaN/GaN HEMTs Stressed under On- and Off-State Stress","authors":"T. Kemmer, M. Dammann, M. Baeumler, V. Polyakov, P. Brückner, H. Konstanzer, R. Quay, O. Ambacher","doi":"10.1109/IRPS45951.2020.9128308","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128308","url":null,"abstract":"A systematic investigation of the effect of temperature and electric field on the degradation of 100 nm AlGaN/GaN HEMTs stressed under on- and off-state conditions has been carried out. The shape of the degradation behavior is analyzed and compared between stress conditions. The shape parameter of an Avrami-model was found to be reduced at higher temperatures. Failure analysis was performed by delayering with subsequent SEM and AFM investigation of the semiconductor surface. All devices showed surface damage in the vicinity of the drain-sided gate-edge. Devices stressed at high voltage and high temperature exhibited more and deeper pits than devices stressed at low drain-bias and low temperature, even though all devices have been stressed to the same electrical degradation of 10 % decrease in IDSS.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134282213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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