Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128341
R. Akimoto, R. Kuroda, A. Teramoto, Takezo Mawaki, S. Ichino, T. Suwa, S. Sugawa
In this work, temporal noise characteristics of 11520 MOSFETs were measured for each of rectangular and trapezoidal shaped gates, and characteristics of random telegraph noise (RTN), such as amplitude and time constants under various drain-to-source voltage (VDS) conditions were extracted and analyzed. It was found that RTN is dominated by traps at the minimum gate width in the channel formed under each of the operating bias conditions, and traps at the source side are most influential under a large VDS. The trap location along the source-drain direction is estimated by the VDS dependencies of RTN characteristics.
{"title":"Effect of Drain-to-Source Voltage on Random Telegraph Noise Based on Statistical Analysis of MOSFETs with Various Gate Shapes","authors":"R. Akimoto, R. Kuroda, A. Teramoto, Takezo Mawaki, S. Ichino, T. Suwa, S. Sugawa","doi":"10.1109/IRPS45951.2020.9128341","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128341","url":null,"abstract":"In this work, temporal noise characteristics of 11520 MOSFETs were measured for each of rectangular and trapezoidal shaped gates, and characteristics of random telegraph noise (RTN), such as amplitude and time constants under various drain-to-source voltage (VDS) conditions were extracted and analyzed. It was found that RTN is dominated by traps at the minimum gate width in the channel formed under each of the operating bias conditions, and traps at the source side are most influential under a large VDS. The trap location along the source-drain direction is estimated by the VDS dependencies of RTN characteristics.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126059172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129116
F. Masin, M. Meneghini, E. Canato, A. Barbato, C. D. Santi, A. Stockman, A. Banerjee, P. Moens, E. Zanoni, G. Meneghesso
This paper reports a detailed analysis of the performance and stability of E-mode GaN HEMTs under soft and hard switching conditions. We developed a novel on-wafer setup that controls the overlapping between the gate and drain pulses and, simultaneously, senses the current at the source. This allowed us to plot the instantaneous power, the switching I-V locus and evaluate the switching losses on wafer level. The dynamic on-resistance RDS,ON is evaluated during hard and soft switching at room temperature and high temperature. The results demonstrate that (i) the properties of the buffer impact on dynamic-Ron, in soft- and hard-switching; devices with non-optimized buffer have stronger dynamic-Ron under hard switching; (ii) Ron-increase under hard switching is not strongly influenced by switching (power) losses; (iii) results indicate that a higher dynamic-Ron in hard switching is correlated to a wider switching locus. The proposed testing approach can be used as a screening tool to evaluate – in one single measurement – the switching losses, the dynamic-Ron and the impact of hard-switching on wafer level.
{"title":"Charge Trapping and Stability of E-Mode p-gate GaN HEMTs Under Soft- and Hard- Switching Conditions","authors":"F. Masin, M. Meneghini, E. Canato, A. Barbato, C. D. Santi, A. Stockman, A. Banerjee, P. Moens, E. Zanoni, G. Meneghesso","doi":"10.1109/IRPS45951.2020.9129116","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129116","url":null,"abstract":"This paper reports a detailed analysis of the performance and stability of E-mode GaN HEMTs under soft and hard switching conditions. We developed a novel on-wafer setup that controls the overlapping between the gate and drain pulses and, simultaneously, senses the current at the source. This allowed us to plot the instantaneous power, the switching I-V locus and evaluate the switching losses on wafer level. The dynamic on-resistance RDS,ON is evaluated during hard and soft switching at room temperature and high temperature. The results demonstrate that (i) the properties of the buffer impact on dynamic-Ron, in soft- and hard-switching; devices with non-optimized buffer have stronger dynamic-Ron under hard switching; (ii) Ron-increase under hard switching is not strongly influenced by switching (power) losses; (iii) results indicate that a higher dynamic-Ron in hard switching is correlated to a wider switching locus. The proposed testing approach can be used as a screening tool to evaluate – in one single measurement – the switching losses, the dynamic-Ron and the impact of hard-switching on wafer level.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123630035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128345
R. Grover, T. Acosta, C. AnDyke, E. Armagan, C. Auth, S. Chugh, K. Downes, M. Hattendorf, N. Jack, S. Joshi, R. Kasim, G. Leatherman, S. Lee, C.-Y. Lin, A. Madhavan, H. Mao, A. Lowrie, G. Martin, G. McPherson, P. Nayak, A. Neale, D. Nminibapiel, Benjamin Orr, J. Palmer, C. Pelto, S. Poon, I. Post, T. Pramanik, Anisur Rahman, S. Ramey, N. Seifert, K. Sethi, A. Schmitz, H. Wu, A. Yeoh
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.
{"title":"A Reliability Overview of Intel’s 10+ Logic Technology","authors":"R. Grover, T. Acosta, C. AnDyke, E. Armagan, C. Auth, S. Chugh, K. Downes, M. Hattendorf, N. Jack, S. Joshi, R. Kasim, G. Leatherman, S. Lee, C.-Y. Lin, A. Madhavan, H. Mao, A. Lowrie, G. Martin, G. McPherson, P. Nayak, A. Neale, D. Nminibapiel, Benjamin Orr, J. Palmer, C. Pelto, S. Poon, I. Post, T. Pramanik, Anisur Rahman, S. Ramey, N. Seifert, K. Sethi, A. Schmitz, H. Wu, A. Yeoh","doi":"10.1109/IRPS45951.2020.9128345","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128345","url":null,"abstract":"We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129107172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128335
D. Veksler, G. Bersuker, Adam W. Bushmaker, M. Mason, P. Shrestha, K. Cheung, J. Campbell, T. Rueckes, L. Cleveland, H. Luan, D. Gilmer
Carbon nanotubes (CNT) resistance-change memory devices were assessed for neuromorphic applications under high frequency use conditions by employing the ultra-short (100 ps -10 ns) voltage pulse technique. Under properly selected operation conditions, CNTs demonstrate switching characteristics promising for various NN implementations.
{"title":"Memory update characteristics of carbon nanotube memristors (NRAM®) under circuitry-relevant operation conditions","authors":"D. Veksler, G. Bersuker, Adam W. Bushmaker, M. Mason, P. Shrestha, K. Cheung, J. Campbell, T. Rueckes, L. Cleveland, H. Luan, D. Gilmer","doi":"10.1109/IRPS45951.2020.9128335","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128335","url":null,"abstract":"Carbon nanotubes (CNT) resistance-change memory devices were assessed for neuromorphic applications under high frequency use conditions by employing the ultra-short (100 ps -10 ns) voltage pulse technique. Under properly selected operation conditions, CNTs demonstrate switching characteristics promising for various NN implementations.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129548786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128344
J. Jeong, Jae-Young Sung, Hee-Hun Yang, H. Lee, Ga-Won Lee
In this study, the instability caused by charge migration in 3D SONOS flash memory was analyzed using a mesh-shaped pattern. The lateral and vertical charge migration is separated using the test pattern, and the flat band voltage shift caused by the lateral charge migration is analyzed by program (or erase) and retention repetitive test. In addition, the mechanism of charge migration was modeled by extracting the activation energy of charge migration.
{"title":"Reliability Analysis by Charge Migration of 3D SONOS Flash Memory","authors":"J. Jeong, Jae-Young Sung, Hee-Hun Yang, H. Lee, Ga-Won Lee","doi":"10.1109/IRPS45951.2020.9128344","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128344","url":null,"abstract":"In this study, the instability caused by charge migration in 3D SONOS flash memory was analyzed using a mesh-shaped pattern. The lateral and vertical charge migration is separated using the test pattern, and the flat band voltage shift caused by the lateral charge migration is analyzed by program (or erase) and retention repetitive test. In addition, the mechanism of charge migration was modeled by extracting the activation energy of charge migration.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126483214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129560
M. Miller, E. I. Cole, G. M. Kraus, P. Robertson
The defect detection capabilities of Power Spectrum Analysis (PSA) [1] have been successfully combined with local laser heating to isolate defective circuitry in a high-speed Si Phase Locked Loop (PLL). The defective operation resulted in missed counts when operating at multi-GHz speeds and elevated temperatures. By monitoring PSA signals at a specific frequency through zero-spanning and scanning the suspect device with a heating laser (1340 nm wavelength), the area(s) causing failure were localized. PSA circumvents the need for a rapid pass/fail detector like that used for Soft Defect Localization (SDL) [2] or Laser-Assisted Defect Analysis (LADA) [3] and converts the at-speed failure to a DC signature. The experimental setup for image acquisition and examples demonstrating utility are described.
{"title":"At-Speed Defect Localization by Combining Laser Scanning Microscopy and Power Spectrum Analysis","authors":"M. Miller, E. I. Cole, G. M. Kraus, P. Robertson","doi":"10.1109/IRPS45951.2020.9129560","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129560","url":null,"abstract":"The defect detection capabilities of Power Spectrum Analysis (PSA) [1] have been successfully combined with local laser heating to isolate defective circuitry in a high-speed Si Phase Locked Loop (PLL). The defective operation resulted in missed counts when operating at multi-GHz speeds and elevated temperatures. By monitoring PSA signals at a specific frequency through zero-spanning and scanning the suspect device with a heating laser (1340 nm wavelength), the area(s) causing failure were localized. PSA circumvents the need for a rapid pass/fail detector like that used for Soft Defect Localization (SDL) [2] or Laser-Assisted Defect Analysis (LADA) [3] and converts the at-speed failure to a DC signature. The experimental setup for image acquisition and examples demonstrating utility are described.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121546609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128333
Weishen Chu, Laura Spinella, D. Shirley, P. Ho
Effects of wiring density and Cu pillar structure, two key features for advanced Cu low-k chips, on chip package interaction (CPI) were investigated. A multi-level finite element analysis (FEA) model was developed to evaluate the effects on CPI based on the energy release rate driving delamination. The effect of wiring density in low-k dielectric layers and the interaction effect between intermetallic compound and wiring design were quantified to assess CPI reliability.
{"title":"Effects of Wiring Density and Pillar Structure on Chip Package Interaction for Advanced Cu Low-k Chips","authors":"Weishen Chu, Laura Spinella, D. Shirley, P. Ho","doi":"10.1109/IRPS45951.2020.9128333","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128333","url":null,"abstract":"Effects of wiring density and Cu pillar structure, two key features for advanced Cu low-k chips, on chip package interaction (CPI) were investigated. A multi-level finite element analysis (FEA) model was developed to evaluate the effects on CPI based on the energy release rate driving delamination. The effect of wiring density in low-k dielectric layers and the interaction effect between intermetallic compound and wiring design were quantified to assess CPI reliability.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131098095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129584
A. Chasin, J. Franco, E. Bury, R. Ritzenthaler, E. Litta, A. Spessot, N. Horiguchi, D. Linten, B. Kaczer
In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices. Firstly, the controversial impact of fin width is studied in terms of exact {VOV ,VD} stress conditions and taking in account the impact of external parasitic series resistance and Self-Heating Effects (SHE). Secondly, the impact of Hydrogen/Deuterium High-Pressure Anneal (HPA) on both time-0 and reliability is evaluated.
{"title":"Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation","authors":"A. Chasin, J. Franco, E. Bury, R. Ritzenthaler, E. Litta, A. Spessot, N. Horiguchi, D. Linten, B. Kaczer","doi":"10.1109/IRPS45951.2020.9129584","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129584","url":null,"abstract":"In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices. Firstly, the controversial impact of fin width is studied in terms of exact {VOV ,VD} stress conditions and taking in account the impact of external parasitic series resistance and Self-Heating Effects (SHE). Secondly, the impact of Hydrogen/Deuterium High-Pressure Anneal (HPA) on both time-0 and reliability is evaluated.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129322
R. Kabouche, K. Harrouche, E. Okada, F. Medjdoub
We report on an on-wafer short-term 40 GHz RF reliability stress test comparison up to 140°C base plate temperature between a 3 nm and 4 nm barrier thickness AlN/GaN HEMT technology showing high power performances in the millimeter wave range. It is found that the barrier thickness in this highly strain heterostructure has a major impact on the device reliability. The superior robustness when using thinner barrier (closer to the critical thickness) is attributed to the reduced strain.
{"title":"Short-term reliability of high performance Q-band AlN/GaN HEMTs","authors":"R. Kabouche, K. Harrouche, E. Okada, F. Medjdoub","doi":"10.1109/IRPS45951.2020.9129322","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129322","url":null,"abstract":"We report on an on-wafer short-term 40 GHz RF reliability stress test comparison up to 140°C base plate temperature between a 3 nm and 4 nm barrier thickness AlN/GaN HEMT technology showing high power performances in the millimeter wave range. It is found that the barrier thickness in this highly strain heterostructure has a major impact on the device reliability. The superior robustness when using thinner barrier (closer to the critical thickness) is attributed to the reduced strain.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126673961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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