Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405809
D. Lekshmanan, A. Bansal, K. Roy
In FinFET SRAM, width quantization and variation in silicon thickness are major challenges impacting stability and manufacturability. We propose a methodology to improve the stability of an SRAM cell by co-optimizing the different transistor fin combinations (relative sizing of different transistors) and silicon fin thickness (of FinFET) at iso-area. At iso-area, read SNM can be increased approx. 2X by varying fin-combination while decreasing write margin by 17%. Further, at iso-area and stability, we propose that silicon fin thickness constraint can be relaxed in FinFETs to improve the manufacturability and reduce process variability. Increasing the silicon fin thickness by approx. 50%, degrades read SNM by 10% while negligibly affecting write margin and increasing access time by 36%. Increased silicon thickness reduces body thickness variation in FinFETs, resulting in reduced device mismatch among transistors in an SRAM cell.
{"title":"FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area","authors":"D. Lekshmanan, A. Bansal, K. Roy","doi":"10.1109/CICC.2007.4405809","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405809","url":null,"abstract":"In FinFET SRAM, width quantization and variation in silicon thickness are major challenges impacting stability and manufacturability. We propose a methodology to improve the stability of an SRAM cell by co-optimizing the different transistor fin combinations (relative sizing of different transistors) and silicon fin thickness (of FinFET) at iso-area. At iso-area, read SNM can be increased approx. 2X by varying fin-combination while decreasing write margin by 17%. Further, at iso-area and stability, we propose that silicon fin thickness constraint can be relaxed in FinFETs to improve the manufacturability and reduce process variability. Increasing the silicon fin thickness by approx. 50%, degrades read SNM by 10% while negligibly affecting write margin and increasing access time by 36%. Increased silicon thickness reduces body thickness variation in FinFETs, resulting in reduced device mismatch among transistors in an SRAM cell.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122164540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405678
Weimin Wu, Xin Li, G. Gildenblat, G. Workman, S. Veeraraghavan, C. McAndrew, R. V. Langevelde, G. Smit, A. Scholten, D. Klaassen, J. Watts
This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability, a parasitic bipolar model, and self-heating. A nonlinear body resistance is included for modeling body-contacted SOI devices. The PSP-SOI model has been extensively tested on several PD/SOI technologies.
{"title":"PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs","authors":"Weimin Wu, Xin Li, G. Gildenblat, G. Workman, S. Veeraraghavan, C. McAndrew, R. V. Langevelde, G. Smit, A. Scholten, D. Klaassen, J. Watts","doi":"10.1109/CICC.2007.4405678","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405678","url":null,"abstract":"This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability, a parasitic bipolar model, and self-heating. A nonlinear body resistance is included for modeling body-contacted SOI devices. The PSP-SOI model has been extensively tested on several PD/SOI technologies.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126078554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405703
K. Jenkins, K. Shepard, Zheng Xu
A circuit for on-chip measurement of period jitter and skew of clock distribution is described. The circuit uses a single latch and a voltage-controlled delay element. The circuit is evaluated in a stand-alone pad frame, where a jitter resolution of about 1 ps is demonstrated, and is incorporated in a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurement.
{"title":"On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks","authors":"K. Jenkins, K. Shepard, Zheng Xu","doi":"10.1109/CICC.2007.4405703","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405703","url":null,"abstract":"A circuit for on-chip measurement of period jitter and skew of clock distribution is described. The circuit uses a single latch and a voltage-controlled delay element. The circuit is evaluated in a stand-alone pad frame, where a jitter resolution of about 1 ps is demonstrated, and is incorporated in a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurement.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405691
M. Locher, M. Tomesen, J. Kuenen, A. Daanen, H. Visser, B. Essink, P. Vervoort, M. Nijrolder, Rob Kopmeiners, W. Redman-White, Richard A. H. Balmford, Rachid El Waffaoui
This paper describes a dual signal path (MIMO) low power, high performance direct conversion WiBro/WiMAX 802.16e radio transceiver optimized for mobile applications and coexistence with on-board cellular and WLAN/Bluetooth systems. It is fabricated in a SiGe BiCMOS process and achieves a receiver NF of less than 2.5 dB over an operation frequency of 2.3-2.7 GHz. The transmit gain can be digitally tuned over a 75 dB range. The transceiver consumes 65/103 mA at a 2.8 V supply in OFDMA Rx/Tx modes respectively.
{"title":"A Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e)","authors":"M. Locher, M. Tomesen, J. Kuenen, A. Daanen, H. Visser, B. Essink, P. Vervoort, M. Nijrolder, Rob Kopmeiners, W. Redman-White, Richard A. H. Balmford, Rachid El Waffaoui","doi":"10.1109/CICC.2007.4405691","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405691","url":null,"abstract":"This paper describes a dual signal path (MIMO) low power, high performance direct conversion WiBro/WiMAX 802.16e radio transceiver optimized for mobile applications and coexistence with on-board cellular and WLAN/Bluetooth systems. It is fabricated in a SiGe BiCMOS process and achieves a receiver NF of less than 2.5 dB over an operation frequency of 2.3-2.7 GHz. The transmit gain can be digitally tuned over a 75 dB range. The transceiver consumes 65/103 mA at a 2.8 V supply in OFDMA Rx/Tx modes respectively.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121860859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405774
F. Aflatouni, O. Momeni, H. Hashemi
A heterodyne electro-optical phase locked loop (EO-PLL) architecture is proposed that can lock the frequency and phase of semiconductor lasers. An aided acquisition circuit inspired by the combination of RF image rejection receivers and digital PLL architectures is incorporated in the EOPLL to extend the frequency acquisition range to GHz, even in the presence of large optical delays in the EOPLL. An integrated circuit prototype is implemented in a 0.13 μm CMOS technology and includes a wide bandwidth transimpedance amplifier and the PLL circuitry. Measurement results for the stand-alone chip and the locking of vertical cavity surface emitting lasers (VCSEL) using the implemented chip are reported.
{"title":"A heterodyne phase locked loop with GHz acquisition range for coherent locking of semiconductor lasers in 0.13 μm CMOS","authors":"F. Aflatouni, O. Momeni, H. Hashemi","doi":"10.1109/CICC.2007.4405774","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405774","url":null,"abstract":"A heterodyne electro-optical phase locked loop (EO-PLL) architecture is proposed that can lock the frequency and phase of semiconductor lasers. An aided acquisition circuit inspired by the combination of RF image rejection receivers and digital PLL architectures is incorporated in the EOPLL to extend the frequency acquisition range to GHz, even in the presence of large optical delays in the EOPLL. An integrated circuit prototype is implemented in a 0.13 μm CMOS technology and includes a wide bandwidth transimpedance amplifier and the PLL circuitry. Measurement results for the stand-alone chip and the locking of vertical cavity surface emitting lasers (VCSEL) using the implemented chip are reported.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125671454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405734
Ali Kiaei, B. Matinpour, Ahmad Bahai, T. Lee
A 10 Gb/s equalizer using both feedforward and decision-feedback equalization is designed for high speed serial-links. The chip is implemented in a standard 0.25 mum SiGe BiCMOS technology with 50 GHz peak ft, and packaged in a commercial LLP package. Using a 4-stage feedforward and 2-tap post-cursor cancellation, this equalizer achieves a total peak-to-peak jitter of 27 ps and 33 ps for 10" and 20" of copper traces on FR4, respectively. The transmitter uses NRZ signaling with no pre-emphasis.
针对高速串行链路，设计了一种采用前馈和决策反馈均衡的10gb /s均衡器。该芯片采用标准的0.25 μ m SiGe BiCMOS技术，峰值频率为50 GHz，并封装在商用LLP封装中。使用4级前馈和2分导后光标消除，该均衡器在FR4上的10”和20”铜走线分别实现了27 ps和33 ps的峰对峰抖动。发射机使用无预强调的NRZ信号。
{"title":"A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links","authors":"Ali Kiaei, B. Matinpour, Ahmad Bahai, T. Lee","doi":"10.1109/CICC.2007.4405734","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405734","url":null,"abstract":"A 10 Gb/s equalizer using both feedforward and decision-feedback equalization is designed for high speed serial-links. The chip is implemented in a standard 0.25 mum SiGe BiCMOS technology with 50 GHz peak ft, and packaged in a commercial LLP package. Using a 4-stage feedforward and 2-tap post-cursor cancellation, this equalizer achieves a total peak-to-peak jitter of 27 ps and 33 ps for 10\" and 20\" of copper traces on FR4, respectively. The transmitter uses NRZ signaling with no pre-emphasis.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124082518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405748
A. Haftbaradaran, K. Martin
Sample-time error among different channels of a time-interleaved analog-to-digital converter (ADC) is a factor in significant degradation of the ADC performance, especially in high frequencies. A two-channel, time-interleaved ADC structure with a background sample-time error compensation technique has been implemented. The sample-time error detection technique uses random data and has been implemented in the digital domain at a low level of complexity. The error correction is performed by adjusting the delay of the clock path of one channel, using a 6-bit digitally-controlled delay element (DCDE). At a sampling rate of 400 MSamples/s, the experimental results show that the spurious-free dynamic range (SFDR) of the ADC system is improved to 58.8 dB at 190 MHz. The ADC system achieves a signal-to-noise-and-distortion ratio (SNDR) of 59.6 dB at 5 MHz and 55.2 dB at 190 MHz after compensation. This error compensation method is especially suitable for time-interleaved ADCs used in digital data communication systems.
{"title":"A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems","authors":"A. Haftbaradaran, K. Martin","doi":"10.1109/CICC.2007.4405748","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405748","url":null,"abstract":"Sample-time error among different channels of a time-interleaved analog-to-digital converter (ADC) is a factor in significant degradation of the ADC performance, especially in high frequencies. A two-channel, time-interleaved ADC structure with a background sample-time error compensation technique has been implemented. The sample-time error detection technique uses random data and has been implemented in the digital domain at a low level of complexity. The error correction is performed by adjusting the delay of the clock path of one channel, using a 6-bit digitally-controlled delay element (DCDE). At a sampling rate of 400 MSamples/s, the experimental results show that the spurious-free dynamic range (SFDR) of the ADC system is improved to 58.8 dB at 190 MHz. The ADC system achieves a signal-to-noise-and-distortion ratio (SNDR) of 59.6 dB at 5 MHz and 55.2 dB at 190 MHz after compensation. This error compensation method is especially suitable for time-interleaved ADCs used in digital data communication systems.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127443339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405709
Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seunghoon Lee, D. Chung, Kyoung-Ho Moon, Hojin Park, Jae-Whui Kim
This work describes a re-configurable 0.5 V to 1.2 V, 10 MS/s to 100 MS/s, 10 b two-step pipeline ADC. The prototype ADC in a 0.13 um CMOS process demonstrates the measured DNL and INL within 0.35 LSB and 0.49 LSB, respectively. The ADC with an active die area of 0.98 mm2 shows the maximum SNDR and SFDR of 56.0 dB and 69.6 dB, respectively, and a power consumption of 19.2 mW at a nominal condition of 0.8 V and 60 MS/s.
{"title":"A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC","authors":"Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seunghoon Lee, D. Chung, Kyoung-Ho Moon, Hojin Park, Jae-Whui Kim","doi":"10.1109/CICC.2007.4405709","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405709","url":null,"abstract":"This work describes a re-configurable 0.5 V to 1.2 V, 10 MS/s to 100 MS/s, 10 b two-step pipeline ADC. The prototype ADC in a 0.13 um CMOS process demonstrates the measured DNL and INL within 0.35 LSB and 0.49 LSB, respectively. The ADC with an active die area of 0.98 mm2 shows the maximum SNDR and SFDR of 56.0 dB and 69.6 dB, respectively, and a power consumption of 19.2 mW at a nominal condition of 0.8 V and 60 MS/s.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129091706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405824
T. Laxminidhi, V. Prasadu, S. Pavan
We present a widely programmable fifth order Chebyshev opamp-RC ladder filter whose 3 dB bandwidth is digitally tunable over a 7X range, from 44-300 MHz. The opamp uses feed-forward compensation to achieve high DC gain and wide bandwidth with reduced bias currents. The principle of "constant capacitance scaling" is used to maintain the shape of the filter response when the bandwidth is changed by a large factor. The filter consumes 36 mW from a 1.8 V supply and has a dynamic range of 56.6 dB.
{"title":"A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS","authors":"T. Laxminidhi, V. Prasadu, S. Pavan","doi":"10.1109/CICC.2007.4405824","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405824","url":null,"abstract":"We present a widely programmable fifth order Chebyshev opamp-RC ladder filter whose 3 dB bandwidth is digitally tunable over a 7X range, from 44-300 MHz. The opamp uses feed-forward compensation to achieve high DC gain and wide bandwidth with reduced bias currents. The principle of \"constant capacitance scaling\" is used to maintain the shape of the filter response when the bandwidth is changed by a large factor. The filter consumes 36 mW from a 1.8 V supply and has a dynamic range of 56.6 dB.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130032742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405851
P. Kinget, B. Soltanian, Songtao Xu, Shih-An Yu
This paper reviews basic trade-offs in oscillator performance specifications. The better understanding of phase noise mechanisms as well as the availability of reliable phase noise simulation tools has led to significant improvements in the power-noise trade-off in recent years. It has further enabled the invention of oscillator topologies which exhibit lower device noise to phase noise conversion, and in this paper pulsed biasing and its implementation through tail-current shaping is described as an example. Area reduction of LC oscillators is further investigated as the large size of oscillators' on-chip LC tank circuits is becoming a significant problem in deeply scaled SOC designs which often require multiple on-chip oscillators.
{"title":"Advanced Design Techniques for Integrated Voltage Controlled LC Oscillators","authors":"P. Kinget, B. Soltanian, Songtao Xu, Shih-An Yu","doi":"10.1109/CICC.2007.4405851","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405851","url":null,"abstract":"This paper reviews basic trade-offs in oscillator performance specifications. The better understanding of phase noise mechanisms as well as the availability of reliable phase noise simulation tools has led to significant improvements in the power-noise trade-off in recent years. It has further enabled the invention of oscillator topologies which exhibit lower device noise to phase noise conversion, and in this paper pulsed biasing and its implementation through tail-current shaping is described as an example. Area reduction of LC oscillators is further investigated as the large size of oscillators' on-chip LC tank circuits is becoming a significant problem in deeply scaled SOC designs which often require multiple on-chip oscillators.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126205277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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