Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820899
Young-Min Hong, Young-Hyun Jun, L. Kim
We propose a fast row cycle DRAM core architecture, which employs the pipelined row address decoding scheme for an hierarchical word line structure. The pipelined row address decoding scheme decreases the amount of the skew during the decoding operation. We obtain the row cycle time by reducing the latency from the beginning of the input address signal to the latching of the sub word line signal. We confirm an 9.14 ns row address cycle time at 2.5 V, even when a row address in the identical cell array is successively accessed by HSPICE simulation based on a LG 0.18 /spl mu/m technology. Adding the latch circuits for pipelining, the area penalty is only 2% of the total size compared with conventional pipelined row address decoding schemes and power dissipation is about 7.5% larger.
{"title":"A pipelined row address decoding scheme for hierarchical word line structure DRAM","authors":"Young-Min Hong, Young-Hyun Jun, L. Kim","doi":"10.1109/ICVC.1999.820899","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820899","url":null,"abstract":"We propose a fast row cycle DRAM core architecture, which employs the pipelined row address decoding scheme for an hierarchical word line structure. The pipelined row address decoding scheme decreases the amount of the skew during the decoding operation. We obtain the row cycle time by reducing the latency from the beginning of the input address signal to the latching of the sub word line signal. We confirm an 9.14 ns row address cycle time at 2.5 V, even when a row address in the identical cell array is successively accessed by HSPICE simulation based on a LG 0.18 /spl mu/m technology. Adding the latch circuits for pipelining, the area penalty is only 2% of the total size compared with conventional pipelined row address decoding schemes and power dissipation is about 7.5% larger.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"69 1","pages":"259-262"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84134697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820803
A. Abidi
Starting from a topic initially confined to academic research the field of RF-CMOS integrated circuits has now progressed to the point that it is on the threshold of important commercial deployment. Progress is on several fronts. New MOS-appropriate circuit techniques have been discovered for many of the RF, IF, and baseband blocks required in state-of-the-art wireless transceivers. Transceiver architectures have evolved to take advantage of the strengths of CMOS, and to circumvent its weaknesses. Recent CMOS implementations of RF and IF blocks combine analog circuits with switched and digital functions in unprecedented ways. The object of this paper is to summarize the important concepts underlying good practice in the design of RF-CMOS circuits, and to summarize the experience to date in integrating transceivers.
{"title":"Wireless transceivers in CMOS IC technology. The new wave","authors":"A. Abidi","doi":"10.1109/ICVC.1999.820803","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820803","url":null,"abstract":"Starting from a topic initially confined to academic research the field of RF-CMOS integrated circuits has now progressed to the point that it is on the threshold of important commercial deployment. Progress is on several fronts. New MOS-appropriate circuit techniques have been discovered for many of the RF, IF, and baseband blocks required in state-of-the-art wireless transceivers. Transceiver architectures have evolved to take advantage of the strengths of CMOS, and to circumvent its weaknesses. Recent CMOS implementations of RF and IF blocks combine analog circuits with switched and digital functions in unprecedented ways. The object of this paper is to summarize the important concepts underlying good practice in the design of RF-CMOS circuits, and to summarize the experience to date in integrating transceivers.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"30 1","pages":"3-10"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84159817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820926
You-Jin Cha, Jin-Kug Lee, Jin Park, Seunghoon Lee
This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the proposed AGC is controlled directly by digital bits without conventional extra digital-to-analog converters. The amplifying function of the AGC is divided into three stages for high-speed operation. A capacitor-segment combination technique considerably improves the effective bandwidth of the AGC. The prototype implemented in a 0.5 /spl mu/m n-well CMOS process shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz. A two-stage AGC is proposed to reduce power and chip area further.
{"title":"Digitally-controlled automatic gain control circuits for CMOS CCD electronic cameras","authors":"You-Jin Cha, Jin-Kug Lee, Jin Park, Seunghoon Lee","doi":"10.1109/ICVC.1999.820926","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820926","url":null,"abstract":"This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the proposed AGC is controlled directly by digital bits without conventional extra digital-to-analog converters. The amplifying function of the AGC is divided into three stages for high-speed operation. A capacitor-segment combination technique considerably improves the effective bandwidth of the AGC. The prototype implemented in a 0.5 /spl mu/m n-well CMOS process shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz. A two-stage AGC is proposed to reduce power and chip area further.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"68 1","pages":"342-345"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84101594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821000
Jae-Hee Won, Kiyoung Choi
We show that an efficient implementation of a self-timed statistical carry lookahead adder can be built from a Manchester carry chain. By exploiting multiple-output DCVSL, the presented implementation not only relieves the delay matching problem of previous design in completion detection but also reduces the number of transistors. The worst case delay is comparable to the previous design, and 25.8% of average power consumption is reduced.
{"title":"Self-timed statistical carry lookahead adder using multiple-output DCVSL","authors":"Jae-Hee Won, Kiyoung Choi","doi":"10.1109/ICVC.1999.821000","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821000","url":null,"abstract":"We show that an efficient implementation of a self-timed statistical carry lookahead adder can be built from a Manchester carry chain. By exploiting multiple-output DCVSL, the presented implementation not only relieves the delay matching problem of previous design in completion detection but also reduces the number of transistors. The worst case delay is comparable to the previous design, and 25.8% of average power consumption is reduced.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"560-563"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82982519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820959
Sang-Gug Lee, Hyuk-Yong Gwak, R. Lowther
The integrated circuit interconnects are experimented with patterned ground shields (PGS) at microwave frequencies. Measurement results demonstrate that the PGS can considerably reduce the power loss at high frequencies as the PGS shields the lossy silicon substrate. Furthermore. The PGS reduces the wave length of the interconnect line as a transmission line. The reduction of the wave length has significant implications in microwave IC design as the technique can be used to shorten the transmission line length for a given electrical length.
{"title":"Characteristics of interconnect lines with patterned ground shields and its implication for microwave ICs","authors":"Sang-Gug Lee, Hyuk-Yong Gwak, R. Lowther","doi":"10.1109/ICVC.1999.820959","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820959","url":null,"abstract":"The integrated circuit interconnects are experimented with patterned ground shields (PGS) at microwave frequencies. Measurement results demonstrate that the PGS can considerably reduce the power loss at high frequencies as the PGS shields the lossy silicon substrate. Furthermore. The PGS reduces the wave length of the interconnect line as a transmission line. The reduction of the wave length has significant implications in microwave IC design as the technique can be used to shorten the transmission line length for a given electrical length.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"444-447"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75870363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820952
Kyong-Ha Lee, Junseok Lee, Hyun-Cheol Kim, J. Hwang
Anomalous short channel characteristics in NO-nitrided gate oxide device were investigated in this paper. In NMOS, the NO-nitrided gate oxide device has less reverse short-channel effect with lower threshold voltage than pure gate oxide device. On the other hand, the opposite case is seen for PMOS. These characteristics are attributed to the boron dose loss in surface region by NO-nitrided oxidation in SIMS analysis. By these results, we can apply nitrogen effect by NO-nitrided oxide to the simulation using interface trap model in TSUPREM-4. We can optimize the NO anneal condition of 0.18 /spl mu/m technology by simulation.
{"title":"TCAD simulation of the nitrogen effect by NO-nitrided oxide","authors":"Kyong-Ha Lee, Junseok Lee, Hyun-Cheol Kim, J. Hwang","doi":"10.1109/ICVC.1999.820952","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820952","url":null,"abstract":"Anomalous short channel characteristics in NO-nitrided gate oxide device were investigated in this paper. In NMOS, the NO-nitrided gate oxide device has less reverse short-channel effect with lower threshold voltage than pure gate oxide device. On the other hand, the opposite case is seen for PMOS. These characteristics are attributed to the boron dose loss in surface region by NO-nitrided oxidation in SIMS analysis. By these results, we can apply nitrogen effect by NO-nitrided oxide to the simulation using interface trap model in TSUPREM-4. We can optimize the NO anneal condition of 0.18 /spl mu/m technology by simulation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"44 1","pages":"423-426"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81432130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820972
Jongwan Jung, Youngjong Lee, J. Hwang, Kyungho Lee
We examined the effect of inter-level dielectric (ILD) and densification anneal on device characteristics, such as polysilicon (poly-Si) activation, silicide resistance, and gate oxide integrity (GOI). For the sample with PTEOS/USG/PTEOS as ILD, any significant degradation of poly-Si activation and silicide resistance was not observed. But gate oxide was severely damaged due to PID. On the other hand, the sample with HLD/BPSG/PTEOS as ILD was free from PID. However, the poly-Si activation and silicide resistance significantly varied depending on the BPSG densification anneal. Our results shows that we should make a compromise between the dopant activation and silicide resistance.
{"title":"The effect of ILD material and BPSG densification anneal on the device characteristics","authors":"Jongwan Jung, Youngjong Lee, J. Hwang, Kyungho Lee","doi":"10.1109/ICVC.1999.820972","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820972","url":null,"abstract":"We examined the effect of inter-level dielectric (ILD) and densification anneal on device characteristics, such as polysilicon (poly-Si) activation, silicide resistance, and gate oxide integrity (GOI). For the sample with PTEOS/USG/PTEOS as ILD, any significant degradation of poly-Si activation and silicide resistance was not observed. But gate oxide was severely damaged due to PID. On the other hand, the sample with HLD/BPSG/PTEOS as ILD was free from PID. However, the poly-Si activation and silicide resistance significantly varied depending on the BPSG densification anneal. Our results shows that we should make a compromise between the dopant activation and silicide resistance.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"41 1","pages":"473-475"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82432066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820934
Jong-Moon Kim, Ho-Jun Song, Young-Back Kim
This paper describes the design and implementation of an L1-band C/A-code GPS RF front-end chip. The chip incorporates a low-noise RF preamplifier, a frequency synthesizer with a conventional voltage-controlled oscillator, a variable gain amplifier, and an analog-to-digital converter. The only external requirements are a temperature compensated crystal oscillator, a two-pole LC filter, a varactor-tuned LC tank circuit for tuning the frequency of the VCO, and standard passive components for the PLL loop filter, the impedance matching and the power supply decoupling. The chip has been implemented in a 0.8-/spl mu/m BiCMOS process. The chip size and operating current are 9 mm/sup 2/ and 42 mA at 3.3 V, respectively.
{"title":"Design and implementation of L1-band C/A-code GPS RF front-end chip","authors":"Jong-Moon Kim, Ho-Jun Song, Young-Back Kim","doi":"10.1109/ICVC.1999.820934","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820934","url":null,"abstract":"This paper describes the design and implementation of an L1-band C/A-code GPS RF front-end chip. The chip incorporates a low-noise RF preamplifier, a frequency synthesizer with a conventional voltage-controlled oscillator, a variable gain amplifier, and an analog-to-digital converter. The only external requirements are a temperature compensated crystal oscillator, a two-pole LC filter, a varactor-tuned LC tank circuit for tuning the frequency of the VCO, and standard passive components for the PLL loop filter, the impedance matching and the power supply decoupling. The chip has been implemented in a 0.8-/spl mu/m BiCMOS process. The chip size and operating current are 9 mm/sup 2/ and 42 mA at 3.3 V, respectively.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"67 1","pages":"372-375"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80882455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820997
S. Yoo, Kiyoung Choi
The authors propose a bus encoding scheme which partitions the configuration data sequence of an FPGA into sub-sequences and applies partial bus-invert coding to each sub-sequence to reduce the number of data bus transitions in reconfiguring the FPGA. Experimental results show that the proposed method gives 12.79%/spl sim/17.06% more reduction of bus transitions on average compared with the conventional bus-invert coding, partial bus-invert coding, and the Beach coding.
{"title":"Interleaving partial bus-invert coding for low power reconfiguration of FPGAs","authors":"S. Yoo, Kiyoung Choi","doi":"10.1109/ICVC.1999.820997","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820997","url":null,"abstract":"The authors propose a bus encoding scheme which partitions the configuration data sequence of an FPGA into sub-sequences and applies partial bus-invert coding to each sub-sequence to reduce the number of data bus transitions in reconfiguring the FPGA. Experimental results show that the proposed method gives 12.79%/spl sim/17.06% more reduction of bus transitions on average compared with the conventional bus-invert coding, partial bus-invert coding, and the Beach coding.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"28 1","pages":"549-552"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89315685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820989
K. Min, Y. Sohn, S.Y. Lee, H.S. Yang, S. Lee
We have estimated the problems of high energy application to memory device fabrication from the point of wafer crystalline structure. Following a series of experiments, we have found the different implantation damage induced by the variations of off-cut and azimuth angle of wafer and show that the difference can be reduced if the tilted wafer is adopted. The use of off-angle wafer also minimizes the shadowing effect depending on the tilt angle of implantation because there is no need to use the tilting method in ion implantation process.
{"title":"Current problems of high energy application in memory device fabrication","authors":"K. Min, Y. Sohn, S.Y. Lee, H.S. Yang, S. Lee","doi":"10.1109/ICVC.1999.820989","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820989","url":null,"abstract":"We have estimated the problems of high energy application to memory device fabrication from the point of wafer crystalline structure. Following a series of experiments, we have found the different implantation damage induced by the variations of off-cut and azimuth angle of wafer and show that the difference can be reduced if the tilted wafer is adopted. The use of off-angle wafer also minimizes the shadowing effect depending on the tilt angle of implantation because there is no need to use the tilting method in ion implantation process.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"6 1","pages":"514-517"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87785146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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