Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820971
Pyung-Moon Zhang, Oh-Khong Kwon
We propose a simple and cost-effective process of die buffer region which enhances the safe operation area (SOA) of the lateral double diffused MOSFETs (LDMOSFETs). Field oxide used for LOCOS isolation in conventional low voltage CMOS process is grown selectively around n+ drain of LDMOSFETs, which acts as buffer region around n+ drain with the help of dopant redistribution at silicon surface. The 150 V rating n-channel LDMOSFETs optimized using the proposed method have the best-reported specific on-resistance of 3.91 m/spl Omega/ cm/sup 2/ and higher second breakdown voltage by 20 V than that of conventional LDMOSFETs.
{"title":"A simple method for formation of the buffer layer in n-channel LDMOS","authors":"Pyung-Moon Zhang, Oh-Khong Kwon","doi":"10.1109/ICVC.1999.820971","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820971","url":null,"abstract":"We propose a simple and cost-effective process of die buffer region which enhances the safe operation area (SOA) of the lateral double diffused MOSFETs (LDMOSFETs). Field oxide used for LOCOS isolation in conventional low voltage CMOS process is grown selectively around n+ drain of LDMOSFETs, which acts as buffer region around n+ drain with the help of dopant redistribution at silicon surface. The 150 V rating n-channel LDMOSFETs optimized using the proposed method have the best-reported specific on-resistance of 3.91 m/spl Omega/ cm/sup 2/ and higher second breakdown voltage by 20 V than that of conventional LDMOSFETs.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"30 1","pages":"469-472"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88224785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820958
Jae-Seong Jeong, O. Beom-hoan, Se-Guen Park
A novel technique, named as "Enhanced-ICP", for a better etch process, has been proposed. Here, we report an improved result of the E-ICP. A photo-resist etch uniformity of below 1% within 10 cm in diameter has been accomplished with improved plasma density and the low electron temperature of 1 eV.
{"title":"Improved etching technique of E-ICP (Enhanced Inductively Coupled Plasma)","authors":"Jae-Seong Jeong, O. Beom-hoan, Se-Guen Park","doi":"10.1109/ICVC.1999.820958","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820958","url":null,"abstract":"A novel technique, named as \"Enhanced-ICP\", for a better etch process, has been proposed. Here, we report an improved result of the E-ICP. A photo-resist etch uniformity of below 1% within 10 cm in diameter has been accomplished with improved plasma density and the low electron temperature of 1 eV.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"273 1","pages":"441-443"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86729038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820864
Kyune-Jin Shim, Ki-yeop Park, Won Gyu Lee, Dai-Hoon Lee
Model based full chip Optical Proximity Correction (OPC) was applied to logic devices with a minimum gate length of 0.24 /spl mu/m. Two empirical models were used in order to correct for both the 1D optical proximity effect and the 2D optical proximity effect simultaneously. OPC features such as line bias and hammer head were effective in reducing critical dimension variation and line shortening. Increased process margin and reduction in interconnection resistance were obtained.
{"title":"Application of full chip OPC to quarter micron logic device","authors":"Kyune-Jin Shim, Ki-yeop Park, Won Gyu Lee, Dai-Hoon Lee","doi":"10.1109/ICVC.1999.820864","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820864","url":null,"abstract":"Model based full chip Optical Proximity Correction (OPC) was applied to logic devices with a minimum gate length of 0.24 /spl mu/m. Two empirical models were used in order to correct for both the 1D optical proximity effect and the 2D optical proximity effect simultaneously. OPC features such as line bias and hammer head were effective in reducing critical dimension variation and line shortening. Increased process margin and reduction in interconnection resistance were obtained.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"517 1","pages":"171-173"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91527849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820891
Yunseok Chun, Kwang Pyo Lee, Sang Su Lee, Sang Chul Kim, Byung-Seop Hong, Hong Yang
Boron behavior in p/sup +/ W-polycide gate used for high performance surface-channel pMOSFET was investigated. The poly structure and poly-WSi/sub x/ interface play an important role in the characteristics of the MOSFET. It was found that large-grain poly showed severe boron penetration compared to an 800 /spl Aring/ amorphous Si layer. In addition, boron out-diffusion into the WSi/sub x/ layer causes severe gate depletion which gives rise to low saturation current. Application of chemical oxide between poly and tungsten silicide turns out to be good barrier to block fluorine diffusion into the gate oxide as well as boron out-diffusion into the WSi/sub x/ layer. A surface channel pMOSFET using N/sub 2/O-annealed oxide and chemical oxide shows excellent characteristics of high saturation current, low leakage and gate depletion.
{"title":"Application of low-temperature N/sub 2/O-annealed oxide and chemical oxide for both boron penetration and gate depletion reductions for thin p/sup +/ tungsten polycide gate","authors":"Yunseok Chun, Kwang Pyo Lee, Sang Su Lee, Sang Chul Kim, Byung-Seop Hong, Hong Yang","doi":"10.1109/ICVC.1999.820891","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820891","url":null,"abstract":"Boron behavior in p/sup +/ W-polycide gate used for high performance surface-channel pMOSFET was investigated. The poly structure and poly-WSi/sub x/ interface play an important role in the characteristics of the MOSFET. It was found that large-grain poly showed severe boron penetration compared to an 800 /spl Aring/ amorphous Si layer. In addition, boron out-diffusion into the WSi/sub x/ layer causes severe gate depletion which gives rise to low saturation current. Application of chemical oxide between poly and tungsten silicide turns out to be good barrier to block fluorine diffusion into the gate oxide as well as boron out-diffusion into the WSi/sub x/ layer. A surface channel pMOSFET using N/sub 2/O-annealed oxide and chemical oxide shows excellent characteristics of high saturation current, low leakage and gate depletion.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"23 1","pages":"237-240"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84625225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820900
M. Je, Joonho Gil, Jaeyoung Kwak, H. Yoo, Hyungcheol Shin
We propose a new capacitor array scheme that we call a temperature adaptive capacitor array (TACA) and use it to achieve complete digital trimming of the TCXO at 20 MHz with 0.3 ppm trimming accuracy. The TACA scheme guarantees monotonicity and saves silicon area at the same time. About 10 % reduction in array layout area and about 14 % reduction in the pre-decoding logic area are reported.
{"title":"A digital temperature compensated crystal oscillator using a temperature adaptive capacitor array","authors":"M. Je, Joonho Gil, Jaeyoung Kwak, H. Yoo, Hyungcheol Shin","doi":"10.1109/ICVC.1999.820900","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820900","url":null,"abstract":"We propose a new capacitor array scheme that we call a temperature adaptive capacitor array (TACA) and use it to achieve complete digital trimming of the TCXO at 20 MHz with 0.3 ppm trimming accuracy. The TACA scheme guarantees monotonicity and saves silicon area at the same time. About 10 % reduction in array layout area and about 14 % reduction in the pre-decoding logic area are reported.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"60 1","pages":"263-265"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90629496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820928
Seung-Chul Lee, Joon-seok Lee, Sung-Ho Lee, Seunghoon Lee
This paper describes a phase-locked loop (PLL) clock generator with low sensitivity to power supply noise. A voltage controlled oscillator employing a source follower reduces power supply noise sensitivity with the proposed power-efficient low-ripple DC-DC converter. Simulated clock jitter is less than /spl plusmn/20 ps, with a 200 mV peak-to-peak sinusoidal noise signal of 1 MHz to 400 MHz applied to a power supply. The proposed PLL simulated in a 0.65 /spl mu/m double-poly double-metal CMOS process consumes 27 mW at 200 MHz from a 3 V supply. The prototype is under fabrication.
{"title":"A 3 V 200 MHz PLL with a low-noise VCO based on a power-efficient low-ripple DC-DC converter","authors":"Seung-Chul Lee, Joon-seok Lee, Sung-Ho Lee, Seunghoon Lee","doi":"10.1109/ICVC.1999.820928","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820928","url":null,"abstract":"This paper describes a phase-locked loop (PLL) clock generator with low sensitivity to power supply noise. A voltage controlled oscillator employing a source follower reduces power supply noise sensitivity with the proposed power-efficient low-ripple DC-DC converter. Simulated clock jitter is less than /spl plusmn/20 ps, with a 200 mV peak-to-peak sinusoidal noise signal of 1 MHz to 400 MHz applied to a power supply. The proposed PLL simulated in a 0.65 /spl mu/m double-poly double-metal CMOS process consumes 27 mW at 200 MHz from a 3 V supply. The prototype is under fabrication.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"346-348"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90124098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820988
H. Moon, T.G. Chung, H. Lee, E. Ahn, T. Cho, S.Y. Oh
The application of a flip chip ball grid array (BGA) package with organic substrate in electronic devices has significantly grown during the past few years. However, potential package reliability problems can still occur, for example die cracks, underfill cracks, and solder joint cracks. An experimental stress analysis which is to measure the stress distribution at the flip chip BGA package using strain gauge and finite element analysis were performed to predict the susceptibility of die cracking during thermal cyclic loading. The experimental stress analysis which is the in-situ stress measurement technique was applied for different variables such as chip thickness, organic substrate and underfill materials. The stress distribution was measured on four kinds of flip chip BGA packages. These results were also compared with the reliability data of package level in order to verify its effectiveness. From the above results, we can find that the strain behavior of the flip chip BGA package with temperature is nonlinear. It also reveals that the strain measured at the lowest temperature is not the maximum. Finally, we can conclude that the experimental stress analysis is a very useful method to predict the susceptibility of die tracking during the thermal cyclic loading in flip chip BGA packages.
{"title":"Experimental stress analysis for flip chip BGA packages using strain gauge","authors":"H. Moon, T.G. Chung, H. Lee, E. Ahn, T. Cho, S.Y. Oh","doi":"10.1109/ICVC.1999.820988","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820988","url":null,"abstract":"The application of a flip chip ball grid array (BGA) package with organic substrate in electronic devices has significantly grown during the past few years. However, potential package reliability problems can still occur, for example die cracks, underfill cracks, and solder joint cracks. An experimental stress analysis which is to measure the stress distribution at the flip chip BGA package using strain gauge and finite element analysis were performed to predict the susceptibility of die cracking during thermal cyclic loading. The experimental stress analysis which is the in-situ stress measurement technique was applied for different variables such as chip thickness, organic substrate and underfill materials. The stress distribution was measured on four kinds of flip chip BGA packages. These results were also compared with the reliability data of package level in order to verify its effectiveness. From the above results, we can find that the strain behavior of the flip chip BGA package with temperature is nonlinear. It also reveals that the strain measured at the lowest temperature is not the maximum. Finally, we can conclude that the experimental stress analysis is a very useful method to predict the susceptibility of die tracking during the thermal cyclic loading in flip chip BGA packages.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"8 1","pages":"510-513"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90359837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820969
Jong-Hyup Lee, Byoung-Ho Kwon, Se-Young Lee, Hee-Jeen Kim, Young-Gyoon Ryu, Seongsoo Kweon, Jeong-Gun Lee
The purpose of this study is to report polishing characteristics of W CMP with combination sets of slurry and pad in 0.25 um logic technology. W etch back process is compared with W CMP process in view of electrical performance in the 0.25 /spl mu/m logic device. The proper selection of consumables is important to the successful application of W CMP. The W CMP process should be carefully controlled to be implemented in the back-end process of sub-quarter micron logic device.
{"title":"W CMP evaluation for 0.25 /spl mu/m logic device","authors":"Jong-Hyup Lee, Byoung-Ho Kwon, Se-Young Lee, Hee-Jeen Kim, Young-Gyoon Ryu, Seongsoo Kweon, Jeong-Gun Lee","doi":"10.1109/ICVC.1999.820969","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820969","url":null,"abstract":"The purpose of this study is to report polishing characteristics of W CMP with combination sets of slurry and pad in 0.25 um logic technology. W etch back process is compared with W CMP process in view of electrical performance in the 0.25 /spl mu/m logic device. The proper selection of consumables is important to the successful application of W CMP. The W CMP process should be carefully controlled to be implemented in the back-end process of sub-quarter micron logic device.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"61 1","pages":"466-468"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77926738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820938
Jin-Cheon Kim, Sanghoon Lee, Hong-June Park
In this paper, a sense amplifier-based flip-flop (SAFF) with a fast output transition capability is proposed to reduce the pipeline overhead of high-performance microprocessors. The new SAFF overcomes the speed limitation of the conventional SAFF which is caused by the output latch implementation. The speed enhancement is achieved by reducing the number of gate stages to be passed from three to two. The SPICE simulation shows that the clock-to-output delay time of the new SAFF is enhanced by 63% compared to that of the conventional SAFF and the new SAFF has the fastest speed in comparison with the recently published flip-flops.
{"title":"A sense amplifier-based CMOS flip-flop with an enhanced output transition time for high-performance microprocessors","authors":"Jin-Cheon Kim, Sanghoon Lee, Hong-June Park","doi":"10.1109/ICVC.1999.820938","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820938","url":null,"abstract":"In this paper, a sense amplifier-based flip-flop (SAFF) with a fast output transition capability is proposed to reduce the pipeline overhead of high-performance microprocessors. The new SAFF overcomes the speed limitation of the conventional SAFF which is caused by the output latch implementation. The speed enhancement is achieved by reducing the number of gate stages to be passed from three to two. The SPICE simulation shows that the clock-to-output delay time of the new SAFF is enhanced by 63% compared to that of the conventional SAFF and the new SAFF has the fastest speed in comparison with the recently published flip-flops.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"83 1","pages":"384-387"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72860213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820876
T. Kikkawa
This paper describes advanced interconnect technologies with respect to ULSI scaling. Copper interconnects and low-k interlayer dielectrics, in conjunction with chemical mechanical polishing (CMP) planarization, are key technologies for future scaled ULSIs to reduce the RC delay of global interconnects. Salicide is an essential technology for sub-quarter micron CMOS gate and source/drain electrodes to reduce the parasitic resistances of transistors for high-speed logic ULSIs. Consequently, both resistivity and capacitance are key factors for materials used in the interconnect technologies for ULSI scaling.
{"title":"Advanced interconnect technologies for ULSI scaling","authors":"T. Kikkawa","doi":"10.1109/ICVC.1999.820876","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820876","url":null,"abstract":"This paper describes advanced interconnect technologies with respect to ULSI scaling. Copper interconnects and low-k interlayer dielectrics, in conjunction with chemical mechanical polishing (CMP) planarization, are key technologies for future scaled ULSIs to reduce the RC delay of global interconnects. Salicide is an essential technology for sub-quarter micron CMOS gate and source/drain electrodes to reduce the parasitic resistances of transistors for high-speed logic ULSIs. Consequently, both resistivity and capacitance are key factors for materials used in the interconnect technologies for ULSI scaling.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"7 1","pages":"202-207"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85424000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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