Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820953
Myoung-Kyu Park, H. Lee, M. Jang, Jun-Hyeok Choi, D. Kang, J. Hwang
The gate delay of ring oscillators in high V/sub T/ CMOSFET technology is characterized with respect to various channel widths (0.72 /spl mu/m-10 /spl mu/m). An expression for gate delay including the channel-width independent capacitance components is derived and compared with experimental results. Substantial increase of gate delay in the narrow channel width region is found due to channel width independent capacitance components which are inherent to transistors. Although the channel width independent capacitance is negligible in wide channel width, gate delay of narrow channel width (/spl les/1 /spl mu/m) ring oscillator increased more than 20% compared with 5 /spl mu/m channel width ring oscillator.
{"title":"Accurate evaluation of gate delay for low-power and high-density 0.18 /spl mu/m CMOSFET technology","authors":"Myoung-Kyu Park, H. Lee, M. Jang, Jun-Hyeok Choi, D. Kang, J. Hwang","doi":"10.1109/ICVC.1999.820953","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820953","url":null,"abstract":"The gate delay of ring oscillators in high V/sub T/ CMOSFET technology is characterized with respect to various channel widths (0.72 /spl mu/m-10 /spl mu/m). An expression for gate delay including the channel-width independent capacitance components is derived and compared with experimental results. Substantial increase of gate delay in the narrow channel width region is found due to channel width independent capacitance components which are inherent to transistors. Although the channel width independent capacitance is negligible in wide channel width, gate delay of narrow channel width (/spl les/1 /spl mu/m) ring oscillator increased more than 20% compared with 5 /spl mu/m channel width ring oscillator.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"56 1","pages":"427-429"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85603200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820818
Sun-Ghil Lee, J. Choi, Sangyong Kim, M. Nam, J. Lee, K. Seo, H. Yoon
Hot carriers deteriorate the interface between Si and gate oxide, which causes the change of current level. We suggest a method for simulating hot carrier-induced device degradation. Based on the present model, we are able to calculate degraded I-V characteristics with time using 2-D process simulation TSUPREM-4 and 2-D device simulator MEDICI. We compare simulated results with experimental ones.
{"title":"Simulation method and application for the hot carrier-induced device degradation of NMOSFET","authors":"Sun-Ghil Lee, J. Choi, Sangyong Kim, M. Nam, J. Lee, K. Seo, H. Yoon","doi":"10.1109/ICVC.1999.820818","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820818","url":null,"abstract":"Hot carriers deteriorate the interface between Si and gate oxide, which causes the change of current level. We suggest a method for simulating hot carrier-induced device degradation. Based on the present model, we are able to calculate degraded I-V characteristics with time using 2-D process simulation TSUPREM-4 and 2-D device simulator MEDICI. We compare simulated results with experimental ones.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"49-52"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89796983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820854
Woo-Sung Chu, K. Yoon, Han Sik Yoon, W. Koh, D. S. Kim, Jae Hyun Park, J. Ha
The characteristics of oxide trench etch in a dual damascene process were studied in a transformer coupled plasma etcher using C/sub 4/F/sub 8//CH/sub 2/F/sub 2//CO mixed plasmas. It was found that the selectivity of oxide with respect to nitride is inversely proportional to the DC bias voltage measured in the C/sub 4/F/sub 8/ plasma system. However adding CO gas to C/sub 4/F/sub 8/ plasma caused an increase in the selectivity with increasing DC bias voltage, which possibly resulted from the reduction of ion densities by the reaction of CO with fluorine ions in the plasma. Under the optimized trench etch conditions with low DC bias voltage, a dual damascene structure of 0.18 /spl mu/m design rule was successfully constructed.
{"title":"Selective oxide trench etch for dual damascene process in a transformer coupled plasma system","authors":"Woo-Sung Chu, K. Yoon, Han Sik Yoon, W. Koh, D. S. Kim, Jae Hyun Park, J. Ha","doi":"10.1109/ICVC.1999.820854","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820854","url":null,"abstract":"The characteristics of oxide trench etch in a dual damascene process were studied in a transformer coupled plasma etcher using C/sub 4/F/sub 8//CH/sub 2/F/sub 2//CO mixed plasmas. It was found that the selectivity of oxide with respect to nitride is inversely proportional to the DC bias voltage measured in the C/sub 4/F/sub 8/ plasma system. However adding CO gas to C/sub 4/F/sub 8/ plasma caused an increase in the selectivity with increasing DC bias voltage, which possibly resulted from the reduction of ion densities by the reaction of CO with fluorine ions in the plasma. Under the optimized trench etch conditions with low DC bias voltage, a dual damascene structure of 0.18 /spl mu/m design rule was successfully constructed.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"3 1","pages":"147-150"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82407098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820904
Yong-Ha Park, Ramchan Woo, Sun-Ho Han, Jung-Su Kim, Se-Joong Lee, Jeonghoon Kook, Jae-Woon Lim, H. Yoo
We implement a rendering engine which has 7.1 GB/s bandwidth and 11.1 Mpolygon/s drawing speed. It has 3D rendering functions such as double buffering, smooth shading, alpha blending and depth comparison. It can convert 3D primitives into complete pixel data in every 90 ns. A serial access memory permits simultaneous memory access both for rendering operation and for screen refresh operation. The proposed virtual page mapping performs rendering operation without a page miss irrespective of the location of a polygon in the screen. Also, the partial word line activation and the sequential block activation can reduce the power consumption of 64 concurrent memory arrays to only 1.2 W.
{"title":"7.1 GB/sec bandwidth 3D rendering engine using the EML technology","authors":"Yong-Ha Park, Ramchan Woo, Sun-Ho Han, Jung-Su Kim, Se-Joong Lee, Jeonghoon Kook, Jae-Woon Lim, H. Yoo","doi":"10.1109/ICVC.1999.820904","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820904","url":null,"abstract":"We implement a rendering engine which has 7.1 GB/s bandwidth and 11.1 Mpolygon/s drawing speed. It has 3D rendering functions such as double buffering, smooth shading, alpha blending and depth comparison. It can convert 3D primitives into complete pixel data in every 90 ns. A serial access memory permits simultaneous memory access both for rendering operation and for screen refresh operation. The proposed virtual page mapping performs rendering operation without a page miss irrespective of the location of a polygon in the screen. Also, the partial word line activation and the sequential block activation can reduce the power consumption of 64 concurrent memory arrays to only 1.2 W.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"166 1","pages":"277-280"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75059489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821008
Yon-Kyun Im, Chi-Weon Yoon, H. Yoo, T. Jung
We propose POPeye that can measure and analyze the performance of the DRAM in real PC environment. POPeye is composed of a virtual PC and hardware structural simulator. Virtual PC of POPeye emulates the total PC system on Unix environment. While running real applications such as Windows95 and MS-office, POPeye's hardware structural simulator can offer the detailed information of transactions between CPU and memory system.
{"title":"POPeye: a system analysis tool for DRAM performance measurement","authors":"Yon-Kyun Im, Chi-Weon Yoon, H. Yoo, T. Jung","doi":"10.1109/ICVC.1999.821008","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821008","url":null,"abstract":"We propose POPeye that can measure and analyze the performance of the DRAM in real PC environment. POPeye is composed of a virtual PC and hardware structural simulator. Virtual PC of POPeye emulates the total PC system on Unix environment. While running real applications such as Windows95 and MS-office, POPeye's hardware structural simulator can offer the detailed information of transactions between CPU and memory system.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"8 1","pages":"590-592"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75175523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820844
Jeone-Hwan Son, Kunsik Park, J. Nam, Shin-Young Chung, Hyeong-Mo Yang, S. Park, Youngjong Lee, Kyungho Lee
Blanket tilt implanted shallow trench isolation (BTI-STI) process is proposed and investigated for enhanced retention time characteristics of high density DRAM. It is confirmed that BTI-STI process can improve the tail retention time due to low surface channel doping and no degradation is observed for buried-channel p-MOSFET even at narrow width. The proposed process is useful for realizing future high density DRAM without increase in process complexity.
{"title":"Blanket tilt implanted shallow trench isolation (BTI-STI) process for enhanced DRAM retention time characteristics","authors":"Jeone-Hwan Son, Kunsik Park, J. Nam, Shin-Young Chung, Hyeong-Mo Yang, S. Park, Youngjong Lee, Kyungho Lee","doi":"10.1109/ICVC.1999.820844","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820844","url":null,"abstract":"Blanket tilt implanted shallow trench isolation (BTI-STI) process is proposed and investigated for enhanced retention time characteristics of high density DRAM. It is confirmed that BTI-STI process can improve the tail retention time due to low surface channel doping and no degradation is observed for buried-channel p-MOSFET even at narrow width. The proposed process is useful for realizing future high density DRAM without increase in process complexity.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"74 1","pages":"122-124"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80005279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820892
Byunghak Lee, Sangcheol Kim, Dong-chan Kim, Taewoo Kim, Jungyeol Park, Youngho Choe, Y. Woo, E. Ryou, Jongoh Kim, J. Om
The dependence of oxide charge-to-breakdown (Q/sub BD/) and device degradation on the combined post annealing of RTA and FA in the tungsten polycide gate technology have been experimentally investigated. The experimental results suggest that Q/sub BD/ and degradation are improved by lower temperature and shorter time of RTA. Whereas the FA/RTA annealing sequence is more advantageous for improving Q/sub BD/, the RTA/FA annealing sequence is good for improving device degradation.
{"title":"The effects of post annealing on oxide-charge-to-breakdown and interface state in tungsten polycide gate","authors":"Byunghak Lee, Sangcheol Kim, Dong-chan Kim, Taewoo Kim, Jungyeol Park, Youngho Choe, Y. Woo, E. Ryou, Jongoh Kim, J. Om","doi":"10.1109/ICVC.1999.820892","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820892","url":null,"abstract":"The dependence of oxide charge-to-breakdown (Q/sub BD/) and device degradation on the combined post annealing of RTA and FA in the tungsten polycide gate technology have been experimentally investigated. The experimental results suggest that Q/sub BD/ and degradation are improved by lower temperature and shorter time of RTA. Whereas the FA/RTA annealing sequence is more advantageous for improving Q/sub BD/, the RTA/FA annealing sequence is good for improving device degradation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"79 1","pages":"241-244"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80297120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821007
Y.H. Kim, J. Nam, Y. Sohn, S. Heo, S. Lee, H.J. Park, Y. han, J. Doh, Y.J. Choi, J. Choi, J. Choi, C. Park
A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and V/sub TN/ respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 V/sub TN/ respectively. Also the pumping current was increased in the new circuit.
{"title":"Two-phase boosted voltage generator [CMOS DRAMs]","authors":"Y.H. Kim, J. Nam, Y. Sohn, S. Heo, S. Lee, H.J. Park, Y. han, J. Doh, Y.J. Choi, J. Choi, J. Choi, C. Park","doi":"10.1109/ICVC.1999.821007","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821007","url":null,"abstract":"A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and V/sub TN/ respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 V/sub TN/ respectively. Also the pumping current was increased in the new circuit.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"62 1","pages":"586-589"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76842909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820833
Jun-Hyung Um, Tae-wan Kim
Wallace-tree style implementations have been proven to be effective schemes for fast computations of arithmetic. This paper generalizes the concept of Wallace's scheme to include 'uneven' arrival times of input operands of the arithmetic circuit. More specifically, for an arithmetic expression in the circuit, we proposed a synthesis algorithm for solving the problem of transforming the expression into a form of the Wallace-tree structure that leads to a minimal timing of the circuit. This practically enables an extensive utilization of Wallace's scheme over the arithmetic circuit, thereby reducing the timing of circuit more effectively. Experimental results are provided to show the effectiveness of the proposed algorithm, over the conventional two-step (RTL and logic) optimization.
{"title":"Wallace-tree based timing-driven synthesis of arithmetic circuits","authors":"Jun-Hyung Um, Tae-wan Kim","doi":"10.1109/ICVC.1999.820833","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820833","url":null,"abstract":"Wallace-tree style implementations have been proven to be effective schemes for fast computations of arithmetic. This paper generalizes the concept of Wallace's scheme to include 'uneven' arrival times of input operands of the arithmetic circuit. More specifically, for an arithmetic expression in the circuit, we proposed a synthesis algorithm for solving the problem of transforming the expression into a form of the Wallace-tree structure that leads to a minimal timing of the circuit. This practically enables an extensive utilization of Wallace's scheme over the arithmetic circuit, thereby reducing the timing of circuit more effectively. Experimental results are provided to show the effectiveness of the proposed algorithm, over the conventional two-step (RTL and logic) optimization.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"101 1","pages":"89-94"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74284458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820878
Jong-Rim Lee, Soo-Mi Lee, Jong-Chae Kim, Wook H. Lee, Won-suk Yang, Sang-Don Lee
This paper presents the properties for CoSi/sub 2/ junction used to realize embedded DRAM and logic (EDL). In high thermal processes for EDL, TiN capping shows considerably better junction leakage and device characteristics than Ti capping.
{"title":"CoSi/sub 2/ junction leakage with Ti or TiN capping, and device characteristics in embedded DRAM with stack capacitor","authors":"Jong-Rim Lee, Soo-Mi Lee, Jong-Chae Kim, Wook H. Lee, Won-suk Yang, Sang-Don Lee","doi":"10.1109/ICVC.1999.820878","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820878","url":null,"abstract":"This paper presents the properties for CoSi/sub 2/ junction used to realize embedded DRAM and logic (EDL). In high thermal processes for EDL, TiN capping shows considerably better junction leakage and device characteristics than Ti capping.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"138 1","pages":"208-210"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81746738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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