Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820968
C. Jeon, Y. Chung, Sang-Young Kim, Jeong-Gun Lee
The generation of defect around trench corners has been investigated using delayering and Wright etching method in 0.25 /spl mu/m logic technology. Process variables impacting the generation of dislocations, including densification of HDP oxide and source/drain (S/D) anneal are studied. It was found that the dislocation density increased abruptly after S/D implantation and post-anneal. Almost all dislocations were detected at trench bottom corners, which correspond to the stress concentrated region. The fact that all etch-pits are discovered at nMOS area without exception implies that the generation of trench dislocations is correlated to the N+S/D implantation. The change of S/D anneal from rapid thermal anneal (RTA) to tube anneal followed by RTA can completely eliminate trench dislocations.
{"title":"Generation of trench dislocation in 0.25 /spl mu/m logic technology and its elimination","authors":"C. Jeon, Y. Chung, Sang-Young Kim, Jeong-Gun Lee","doi":"10.1109/ICVC.1999.820968","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820968","url":null,"abstract":"The generation of defect around trench corners has been investigated using delayering and Wright etching method in 0.25 /spl mu/m logic technology. Process variables impacting the generation of dislocations, including densification of HDP oxide and source/drain (S/D) anneal are studied. It was found that the dislocation density increased abruptly after S/D implantation and post-anneal. Almost all dislocations were detected at trench bottom corners, which correspond to the stress concentrated region. The fact that all etch-pits are discovered at nMOS area without exception implies that the generation of trench dislocations is correlated to the N+S/D implantation. The change of S/D anneal from rapid thermal anneal (RTA) to tube anneal followed by RTA can completely eliminate trench dislocations.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"62 1","pages":"463-465"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86373398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820902
K. Murakami
The paper outlines the current status of PPRAM-related projects at Kyushu University and other institutes: (1) PPRAM-Link; (2) PPRAM-Link interface IP cores; (3) reference PPRAM architectures; (4) PPRAM-MOE. The paper also discusses two on-chip memory-path architectures for PPRAM-type SOCs in detail: variable line-size cache and way-predicting set-associative cache.
{"title":"Current status of PPRAM","authors":"K. Murakami","doi":"10.1109/ICVC.1999.820902","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820902","url":null,"abstract":"The paper outlines the current status of PPRAM-related projects at Kyushu University and other institutes: (1) PPRAM-Link; (2) PPRAM-Link interface IP cores; (3) reference PPRAM architectures; (4) PPRAM-MOE. The paper also discusses two on-chip memory-path architectures for PPRAM-type SOCs in detail: variable line-size cache and way-predicting set-associative cache.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"52 4 1","pages":"266-276"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77378615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820909
Ik-soo Eo, Ho-Soo Lee, Kyungsu Kim
In CDMA (code division multiple access) system the first action for exchanging information is code acquisition which is finding spreading code position. Thus the high-speed code acquisition is very important technology for successful communication. We propose parallel code acquisition system, the code acquisition time is reduced by the parallel structure. But the parallel code acquisition structure needs so many gates that are increasing the chip area and power consumption, thus we propose the parallel code acquisition hardware with small gate design. The efficient design is achieved with function sharing and structure. The designed 16 parallel code acquisition is about 32000 gates compared with 8000 gates of one parallel code acquisition.
{"title":"High speed code acquisition for wideband CDMA system","authors":"Ik-soo Eo, Ho-Soo Lee, Kyungsu Kim","doi":"10.1109/ICVC.1999.820909","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820909","url":null,"abstract":"In CDMA (code division multiple access) system the first action for exchanging information is code acquisition which is finding spreading code position. Thus the high-speed code acquisition is very important technology for successful communication. We propose parallel code acquisition system, the code acquisition time is reduced by the parallel structure. But the parallel code acquisition structure needs so many gates that are increasing the chip area and power consumption, thus we propose the parallel code acquisition hardware with small gate design. The efficient design is achieved with function sharing and structure. The designed 16 parallel code acquisition is about 32000 gates compared with 8000 gates of one parallel code acquisition.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"39 1","pages":"293-296"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77398439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820867
Seong-Ho Park, G. Lim, Yong-Hee Lee
In this paper a 0.5 /spl mu/m BiCMOS device model library developed for RFIC applications has been introduced. The modeling methodology, the RF device characteristics available in this library, their equivalent circuit models with high-frequency parasitics, and modeling results have been described.
{"title":"Development of 0.5 /spl mu/m BiCMOS device model library for RFIC applications","authors":"Seong-Ho Park, G. Lim, Yong-Hee Lee","doi":"10.1109/ICVC.1999.820867","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820867","url":null,"abstract":"In this paper a 0.5 /spl mu/m BiCMOS device model library developed for RFIC applications has been introduced. The modeling methodology, the RF device characteristics available in this library, their equivalent circuit models with high-frequency parasitics, and modeling results have been described.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"28 1","pages":"178-181"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86029730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820860
Sangyeon Han, Taejnn Park, Bonkee Kim, Hyungcheol Shin, Kwyro Lee
We report on 40 nm patterning using an E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of the E-beam system, we reduced the PR thickness to 100 nm, and the field size to 200 /spl mu/m. In this way, PEB (Post Expose Bake) time and temperature, which are very important factors for nanopatterning, were reduced for minimum line width. In addition, digitizing was optimized for better results. Quantum wires, quantum dots, and quantum dots on a narrow channel, which can be used for nano-scale memory devices (such as single electron memory devices), were fabricated using these lithography techniques.
{"title":"40 nm electron beam patterning and its application to silicon nano-structure fabrication","authors":"Sangyeon Han, Taejnn Park, Bonkee Kim, Hyungcheol Shin, Kwyro Lee","doi":"10.1109/ICVC.1999.820860","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820860","url":null,"abstract":"We report on 40 nm patterning using an E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of the E-beam system, we reduced the PR thickness to 100 nm, and the field size to 200 /spl mu/m. In this way, PEB (Post Expose Bake) time and temperature, which are very important factors for nanopatterning, were reduced for minimum line width. In addition, digitizing was optimized for better results. Quantum wires, quantum dots, and quantum dots on a narrow channel, which can be used for nano-scale memory devices (such as single electron memory devices), were fabricated using these lithography techniques.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"11 1","pages":"163-166"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88860503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820913
Wookyeong Jeong, S. An, M. Kim, Sangkyong Heo, Youngju Kim, Sangook Moon, Yong-Surk Lee
In this paper, a combined architecture, YS-RDSP, which merges a RISC microprocessor with a DSP processor to be suitable for embedded applications is proposed and designed. The YS-RDSP can execute maximum 4 instructions in parallel at the same time. In order to reduce the size of programs, the YS-RDSP has variable instruction length of 16-bit and 32-bit. The YS-RDSP provides DSP processing power as well as control power and programmability of RISC microprocessor on a single chip. The YS-RDSP has 8-kbyte ROM and 8-kbyte RAM on chip. System controller which is a peripheral included in the chip provides three power-down modes for low-power operations, and SLEEP instruction switches the operation states of the CPU core and peripherals. The YS-RDSP processor is modeled in Verilog-HDL with top-down design methodology. Verified model is synthesized with 0.6 /spl mu/m 3.3 V CMOS standard cell library and laid out using automated P&R resulting 10.7 mm by 8.4 mm core area.
本文提出并设计了一种适合嵌入式应用的RISC微处理器与DSP处理器相结合的YS-RDSP组合体系结构。YS-RDSP最多可同时并行执行4条指令。为了减小程序的大小，YS-RDSP有16位和32位的可变指令长度。YS-RDSP提供了DSP处理能力以及RISC微处理器在单片上的控制能力和可编程性。YS-RDSP芯片上有8kb的ROM和8kb的RAM。系统控制器是包含在芯片内的外设，为低功耗操作提供三种下电模式，SLEEP指令切换CPU核心和外设的工作状态。YS-RDSP处理器采用自顶向下的设计方法，在Verilog-HDL语言中建模。经过验证的模型是用0.6 /spl mu/m 3.3 V CMOS标准电池库合成的，并使用自动P&R进行布局，得到10.7 mm × 8.4 mm的核心面积。
{"title":"Design of a combined processor containing a 32-bit RISC microprocessor and a 16-bit fixed-point DSP on a chip","authors":"Wookyeong Jeong, S. An, M. Kim, Sangkyong Heo, Youngju Kim, Sangook Moon, Yong-Surk Lee","doi":"10.1109/ICVC.1999.820913","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820913","url":null,"abstract":"In this paper, a combined architecture, YS-RDSP, which merges a RISC microprocessor with a DSP processor to be suitable for embedded applications is proposed and designed. The YS-RDSP can execute maximum 4 instructions in parallel at the same time. In order to reduce the size of programs, the YS-RDSP has variable instruction length of 16-bit and 32-bit. The YS-RDSP provides DSP processing power as well as control power and programmability of RISC microprocessor on a single chip. The YS-RDSP has 8-kbyte ROM and 8-kbyte RAM on chip. System controller which is a peripheral included in the chip provides three power-down modes for low-power operations, and SLEEP instruction switches the operation states of the CPU core and peripherals. The YS-RDSP processor is modeled in Verilog-HDL with top-down design methodology. Verified model is synthesized with 0.6 /spl mu/m 3.3 V CMOS standard cell library and laid out using automated P&R resulting 10.7 mm by 8.4 mm core area.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"88 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89354176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820929
U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard, F. Maloberti
The continued down scaling of submicron CMOS technology forces innovation of practical and economical circuits that will tolerate reduced headroom (reduced power supply voltage) due to lowering of the technology's maximum allowable voltage. Given the relatively large threshold voltages with respect to the shrinking headroom, a group of widely used analog signal processing building blocks that are made of switched-capacitor (SC) stages will encounter severe overdrive problems when operating at these low-voltage conditions. This tutorial summarizes some of the well-known solutions currently in use and problems associated with these solutions, and proposes novel circuit techniques for truly low-voltage switched-capacitor applications.
{"title":"Switched-capacitor circuit techniques in submicron low-voltage CMOS","authors":"U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard, F. Maloberti","doi":"10.1109/ICVC.1999.820929","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820929","url":null,"abstract":"The continued down scaling of submicron CMOS technology forces innovation of practical and economical circuits that will tolerate reduced headroom (reduced power supply voltage) due to lowering of the technology's maximum allowable voltage. Given the relatively large threshold voltages with respect to the shrinking headroom, a group of widely used analog signal processing building blocks that are made of switched-capacitor (SC) stages will encounter severe overdrive problems when operating at these low-voltage conditions. This tutorial summarizes some of the well-known solutions currently in use and problems associated with these solutions, and proposes novel circuit techniques for truly low-voltage switched-capacitor applications.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"50 1","pages":"349-358"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87375381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821010
Myoung-Su Lee, T. Cheung, W. Choi
A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 /spl mu/m CMOS process technology and evaluated by post-layout simulation.
{"title":"A novel charge pump PLL with reduced jitter characteristics","authors":"Myoung-Su Lee, T. Cheung, W. Choi","doi":"10.1109/ICVC.1999.821010","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821010","url":null,"abstract":"A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 /spl mu/m CMOS process technology and evaluated by post-layout simulation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"44 1","pages":"596-598"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87537653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821001
Seon‐Ho Han, Joo-Ho Lee, H. Yoo
We propose a mixed mode Delay Locked Loop (DLL) for low jitter clock recovery and fast lock-on time. A digital FDL (Fixed Delay Line) compensates initial large phase error and an analog VCDL (Voltage Controlled Delay Line) compensates small static phase error to obtain low jitter. The lock-on time of the mixed mode DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz.
{"title":"A fast lock-on time mixed mode DLL with 10 ps jitter","authors":"Seon‐Ho Han, Joo-Ho Lee, H. Yoo","doi":"10.1109/ICVC.1999.821001","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821001","url":null,"abstract":"We propose a mixed mode Delay Locked Loop (DLL) for low jitter clock recovery and fast lock-on time. A digital FDL (Fixed Delay Line) compensates initial large phase error and an analog VCDL (Voltage Controlled Delay Line) compensates small static phase error to obtain low jitter. The lock-on time of the mixed mode DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"16 1","pages":"564-565"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88004110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820977
Jae-Hyung Kim, J. Choy, Doohee Song, Youngjong Lee, Kyungho Lee
Device characteristics with a barrel-type gate profile caused by the proximity effect were investigated. We show that enhanced hot carrier degradation may result and a decrease of the gate to drain overlap capacitance may occur because of the offset region between the LDD region and the gate electrode. Finally we have recommended a method of measuring gate line width (CD, Critical Dimension) for more precise expectations of the device characteristics.
{"title":"The halo nMOSFET characteristics dependent on the gate profile","authors":"Jae-Hyung Kim, J. Choy, Doohee Song, Youngjong Lee, Kyungho Lee","doi":"10.1109/ICVC.1999.820977","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820977","url":null,"abstract":"Device characteristics with a barrel-type gate profile caused by the proximity effect were investigated. We show that enhanced hot carrier degradation may result and a decrease of the gate to drain overlap capacitance may occur because of the offset region between the LDD region and the gate electrode. Finally we have recommended a method of measuring gate line width (CD, Critical Dimension) for more precise expectations of the device characteristics.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"362 1","pages":"484-486"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80267609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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