Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820810
Tae hoon Kim, Young Hwan Kim
This paper presents a cell selection algorithm that minimizes the area of the cell-based design, while satisfying the given delay constraint. The proposed algorithm visits the given circuit in the forward direction and calculates the lower bound on the delay and area. Then, it visits the circuit in the reverse direction, and binds the logic gates with library cells using the Branch-and-Bound formulations of the lower bound. Experimental results show that the proposed algorithm minimizes the area of test circuits by 27.33% on the average.
{"title":"A cell selection algorithm for area minimization","authors":"Tae hoon Kim, Young Hwan Kim","doi":"10.1109/ICVC.1999.820810","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820810","url":null,"abstract":"This paper presents a cell selection algorithm that minimizes the area of the cell-based design, while satisfying the given delay constraint. The proposed algorithm visits the given circuit in the forward direction and calculates the lower bound on the delay and area. Then, it visits the circuit in the reverse direction, and binds the logic gates with library cells using the Branch-and-Bound formulations of the lower bound. Experimental results show that the proposed algorithm minimizes the area of test circuits by 27.33% on the average.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"8 1","pages":"29-31"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89645259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820872
J. Sim, I. Nam, Sung I. Hong, Jong-Duk Lee, Byung-Gook Park
In this paper, we propose a new experimental technique, namely the parallel stressing method to investigate the breakdown mechanism of MOS capacitors. The SILC characteristics of the region excluding the breakdown spot of a broken-down capacitor can be deduced, utilizing this method. It was shown that HBD as well as SBD takes place locally, as expected. Multiple SBD phenomena at different points on a capacitor have been verified. However, HBD has not occurred multiply, which is thought to be because of the decrease in stress intensity after the event.
{"title":"A study on soft- and hard-breakdowns in MOS capacitors using the parallel stressing method","authors":"J. Sim, I. Nam, Sung I. Hong, Jong-Duk Lee, Byung-Gook Park","doi":"10.1109/ICVC.1999.820872","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820872","url":null,"abstract":"In this paper, we propose a new experimental technique, namely the parallel stressing method to investigate the breakdown mechanism of MOS capacitors. The SILC characteristics of the region excluding the breakdown spot of a broken-down capacitor can be deduced, utilizing this method. It was shown that HBD as well as SBD takes place locally, as expected. Multiple SBD phenomena at different points on a capacitor have been verified. However, HBD has not occurred multiply, which is thought to be because of the decrease in stress intensity after the event.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"55 1","pages":"194-196"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91252561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820839
A. Halambi, P. Grun, H. Tomiyama, N. Dutt, A. Nicolau
Modern embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs.
{"title":"Automatic software toolkit generation for embedded systems-on-chip","authors":"A. Halambi, P. Grun, H. Tomiyama, N. Dutt, A. Nicolau","doi":"10.1109/ICVC.1999.820839","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820839","url":null,"abstract":"Modern embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"65 1","pages":"107-116"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76040670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820985
Younsoo Kim, Kyung-Cheol Jeong, J. Joo, Jongee Park, Jun-Sik Lee, Jong-Woo Yoon, J. Roh
RuO/sub x/ thin films were deposited on TiN/SiO/sub 2//Si substrates by metal organic chemical vapor deposition (MOCVD) at deposition temperatures of 250/spl deg/C-400/spl deg/ C. We have used Ru(mhd), as a metal organic (MO) source. No films were deposited without the addition of O/sub 2/ gas. RuO/sub 2/ films were deposited at high O/sub 2/ addition. For the deposition of Ru films in the surface reaction controlled region, the activation energy was 0.58 eV. The smooth and well-adherent Ru films had very low resistivities. The microstructure of Ru films was greatly dependent on deposition conditions. Ru films deposited at 27/spl deg/C showed a good step coverage.
{"title":"Growth of RuO/sub x/ thin films by metalorganic chemical vapor deposition","authors":"Younsoo Kim, Kyung-Cheol Jeong, J. Joo, Jongee Park, Jun-Sik Lee, Jong-Woo Yoon, J. Roh","doi":"10.1109/ICVC.1999.820985","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820985","url":null,"abstract":"RuO/sub x/ thin films were deposited on TiN/SiO/sub 2//Si substrates by metal organic chemical vapor deposition (MOCVD) at deposition temperatures of 250/spl deg/C-400/spl deg/ C. We have used Ru(mhd), as a metal organic (MO) source. No films were deposited without the addition of O/sub 2/ gas. RuO/sub 2/ films were deposited at high O/sub 2/ addition. For the deposition of Ru films in the surface reaction controlled region, the activation energy was 0.58 eV. The smooth and well-adherent Ru films had very low resistivities. The microstructure of Ru films was greatly dependent on deposition conditions. Ru films deposited at 27/spl deg/C showed a good step coverage.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"9 1","pages":"501-503"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78596660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820990
J. Kahng, J.H. Kim, M. Jo, H. Yoon
Considering effects of nonuniform doping profile in vertical and lateral directions of MOSFET and solving a quasi two-dimensional differential equation for the surface potential, we have proposed a new threshold voltage model. Our model predicts well an initial roll-up of the threshold voltage with decreasing channel lengths and reduction of it due to the reverse short-channel effects and the short-channel effects.
{"title":"Scalable threshold voltage model for deep-submicrometer MOSFET","authors":"J. Kahng, J.H. Kim, M. Jo, H. Yoon","doi":"10.1109/ICVC.1999.820990","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820990","url":null,"abstract":"Considering effects of nonuniform doping profile in vertical and lateral directions of MOSFET and solving a quasi two-dimensional differential equation for the surface potential, we have proposed a new threshold voltage model. Our model predicts well an initial roll-up of the threshold voltage with decreasing channel lengths and reduction of it due to the reverse short-channel effects and the short-channel effects.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"93 1","pages":"518-521"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75847471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820937
Gijung Ahn, D. Jeong
This paper presents a 1.25-GBaud transceiver chip implemented with 0.35-/spl mu/m CMOS technology, which can be used as an IEEE 802.32 Gigabit Ethernet 1000Base-X physical layer. A voltage mode driver and an on-chip termination circuit reduce signal distortion in the pseudo-ECL serial data stream in the presence of parasitic capacitance and inductance as well as reducing the number of external components. A differential voltage swing of output driver is 1400 mV and power consumption is 510 mW at 3.3 V supply under normal operation.
{"title":"A 1.25-GBaud CMOS transceiver with on-chip terminator and voltage mode driver for Gigabit Ethernet 1000Base-X","authors":"Gijung Ahn, D. Jeong","doi":"10.1109/ICVC.1999.820937","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820937","url":null,"abstract":"This paper presents a 1.25-GBaud transceiver chip implemented with 0.35-/spl mu/m CMOS technology, which can be used as an IEEE 802.32 Gigabit Ethernet 1000Base-X physical layer. A voltage mode driver and an on-chip termination circuit reduce signal distortion in the pseudo-ECL serial data stream in the presence of parasitic capacitance and inductance as well as reducing the number of external components. A differential voltage swing of output driver is 1400 mV and power consumption is 510 mW at 3.3 V supply under normal operation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"19 1","pages":"380-383"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72847267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820995
Young-Sang Lee, Jun-Woo Kang, L. Kim, Seung-Ho Hwang
A radix-2 square root implementation for self-timed dividers using redundant signed-digit (RSD) adders is presented. In this method, two self-timed RSD adder stages are used for each result bit selection. A very efficient and simple result bit selection logic compared to the previous designs is implemented by using double self-timed ring stages. The F-term in the RSD format is easily applied to two self-time substages. F-term generation is overlapped with a partial remainder calculation and result-bit selection. This makes the hardware implementation of the F-term generation much easier and less time-constraint. No additional time delay is included in the square-root arithmetic. From the SPICE simulation at 35/spl deg/C and under MOSIS 1.2 /spl mu/m design rule, the speed of this design is estimated to be 124 ns for 54 bit square-root and division calculation.
{"title":"Self-timed shared division and square-root implementation using full redundant signed digit numbers","authors":"Young-Sang Lee, Jun-Woo Kang, L. Kim, Seung-Ho Hwang","doi":"10.1109/ICVC.1999.820995","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820995","url":null,"abstract":"A radix-2 square root implementation for self-timed dividers using redundant signed-digit (RSD) adders is presented. In this method, two self-timed RSD adder stages are used for each result bit selection. A very efficient and simple result bit selection logic compared to the previous designs is implemented by using double self-timed ring stages. The F-term in the RSD format is easily applied to two self-time substages. F-term generation is overlapped with a partial remainder calculation and result-bit selection. This makes the hardware implementation of the F-term generation much easier and less time-constraint. No additional time delay is included in the square-root arithmetic. From the SPICE simulation at 35/spl deg/C and under MOSIS 1.2 /spl mu/m design rule, the speed of this design is estimated to be 124 ns for 54 bit square-root and division calculation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"541-544"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90182918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820868
J. Comfort
As we approach the new millenium DRAM technology is faced with a number of significant new challenges in addition to those associated with the historical DRAM scaling paradigm. Continued lithographic capability scaling is of course required, but this must now be accomplished on an accelerated schedule at a time when the overall development infrastructure (masks, inspection, repair, steppers, resists) is struggling to keep up with historical trends. Similar limitations exist for continued scaling of many cell technologies: node dielectric thickness, array transistor threshold/leakage control, support transistor performance, high aspect ratio metallization and gap fill all face fundamental materials or physics limitations which require significant effort and cost to overcome. At the same time. Continued scaling in support of the historical 27%/bit/yr cost decline requires breakthroughs in both cell technology and product architecture to address the theoretical cell area limit of 8 lithographic squares for the classical folded bitline architecture. Finally, these challenges are appearing at a time when the DRAM marketplace is diverging into multiple high performance interface requirements which stress these technology features even further while market pricing continues to put extreme pressure on process and development cost containment. The author reviews many of these challenges, comments on the details of the technical issues and then outlines some alternatives which may address the concerns.
{"title":"DRAM technology: outlook and challenges","authors":"J. Comfort","doi":"10.1109/ICVC.1999.820868","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820868","url":null,"abstract":"As we approach the new millenium DRAM technology is faced with a number of significant new challenges in addition to those associated with the historical DRAM scaling paradigm. Continued lithographic capability scaling is of course required, but this must now be accomplished on an accelerated schedule at a time when the overall development infrastructure (masks, inspection, repair, steppers, resists) is struggling to keep up with historical trends. Similar limitations exist for continued scaling of many cell technologies: node dielectric thickness, array transistor threshold/leakage control, support transistor performance, high aspect ratio metallization and gap fill all face fundamental materials or physics limitations which require significant effort and cost to overcome. At the same time. Continued scaling in support of the historical 27%/bit/yr cost decline requires breakthroughs in both cell technology and product architecture to address the theoretical cell area limit of 8 lithographic squares for the classical folded bitline architecture. Finally, these challenges are appearing at a time when the DRAM marketplace is diverging into multiple high performance interface requirements which stress these technology features even further while market pricing continues to put extreme pressure on process and development cost containment. The author reviews many of these challenges, comments on the details of the technical issues and then outlines some alternatives which may address the concerns.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"113 1","pages":"182-186"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85914626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820961
Kil-Ho Kim, K. S. Shin, K. Baek, Chang Wook Park, W. Lee
Effects of N/sub 2/ addition on the plasma composition activated with 'Cl/sub 2/+BCl/sub 3/' and on the aluminum alloy etching in an inductively coupled plasma source are studied. Optical emission spectroscopy data reveal that admiring small amount of N/sub 2/ to the 'Cl/sub 2/+BCl/sub 3/'-plasma generally expedites dissociation processes to increase the density of Cl species within it. The N/sub 2/ addition also accelerates the formation of passivation polymers via carbon species, which adhere to the sidewalls of patterned metal lines and protect them against the lateral attacks of deflected diffusive etchants such as Cl species. It seems that the relative abundance of Cl species over the passivation polymers, both which are controlled by the N/sub 2/ addition, is a critical factor in determining the sidewall features of patterned metal lines.
{"title":"Effects of N/sub 2/ addition on aluminum alloy etching: optical emission spectroscopy studies","authors":"Kil-Ho Kim, K. S. Shin, K. Baek, Chang Wook Park, W. Lee","doi":"10.1109/ICVC.1999.820961","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820961","url":null,"abstract":"Effects of N/sub 2/ addition on the plasma composition activated with 'Cl/sub 2/+BCl/sub 3/' and on the aluminum alloy etching in an inductively coupled plasma source are studied. Optical emission spectroscopy data reveal that admiring small amount of N/sub 2/ to the 'Cl/sub 2/+BCl/sub 3/'-plasma generally expedites dissociation processes to increase the density of Cl species within it. The N/sub 2/ addition also accelerates the formation of passivation polymers via carbon species, which adhere to the sidewalls of patterned metal lines and protect them against the lateral attacks of deflected diffusive etchants such as Cl species. It seems that the relative abundance of Cl species over the passivation polymers, both which are controlled by the N/sub 2/ addition, is a critical factor in determining the sidewall features of patterned metal lines.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"39 1","pages":"448-451"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87787513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820998
Sejun Kim, I. Chang, S. Seo, K. Kwack
This paper describes a new architecture and schemes for a high speed SRAM. It is summarized as follows:1) a Folded Bit-Line Architecture (FBLA) to reduce the delay time of bit-line by decreasing the parastic capacitance, to reduce the area. 2) a Double Word-Line Activation (DWLA) technique to increase the data-rate twice and minimize row path delay, and 3) a high speed sensing scheme to decrease the delay time of the sense amplifier. To verify the above, a 8 kb SRAM was designed using 0.6 /spl mu/m CMOS technology. It realized a 600 Mbyte/s(300 M/spl times/8/spl times/2) data-rate and the die size is 2.8 mm/spl times/0.85 mm.
{"title":"A folded bit-line architecture for high speed CMOS SRAM","authors":"Sejun Kim, I. Chang, S. Seo, K. Kwack","doi":"10.1109/ICVC.1999.820998","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820998","url":null,"abstract":"This paper describes a new architecture and schemes for a high speed SRAM. It is summarized as follows:1) a Folded Bit-Line Architecture (FBLA) to reduce the delay time of bit-line by decreasing the parastic capacitance, to reduce the area. 2) a Double Word-Line Activation (DWLA) technique to increase the data-rate twice and minimize row path delay, and 3) a high speed sensing scheme to decrease the delay time of the sense amplifier. To verify the above, a 8 kb SRAM was designed using 0.6 /spl mu/m CMOS technology. It realized a 600 Mbyte/s(300 M/spl times/8/spl times/2) data-rate and the die size is 2.8 mm/spl times/0.85 mm.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"14 1","pages":"553-556"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82061328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：