Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820865
S.M. Nam, B. Lee, S. Hong, C.G. Yu, J. Park, H. Yu
This paper presents the degradation of f/sub T/ and f/sub max/ in CMOS devices at elevated temperature. Since MOS transistors in RF applications are usually in saturation region and f/sub T/ of CMOS devices is proportional to g/sub m/, a simple empirical model for temperature dependence of g/sub m/ at any measurement bias has been suggested by considering the temperature dependence of carrier mobility and a saturation velocity simultaneously. From the empirical temperature behavior of g/sub m/, we can predict the enhanced RF performances of CMOS at low temperature.
{"title":"Experimental investigation of temperature dependent RF performances of RF-CMOS devices","authors":"S.M. Nam, B. Lee, S. Hong, C.G. Yu, J. Park, H. Yu","doi":"10.1109/ICVC.1999.820865","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820865","url":null,"abstract":"This paper presents the degradation of f/sub T/ and f/sub max/ in CMOS devices at elevated temperature. Since MOS transistors in RF applications are usually in saturation region and f/sub T/ of CMOS devices is proportional to g/sub m/, a simple empirical model for temperature dependence of g/sub m/ at any measurement bias has been suggested by considering the temperature dependence of carrier mobility and a saturation velocity simultaneously. From the empirical temperature behavior of g/sub m/, we can predict the enhanced RF performances of CMOS at low temperature.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"84 1","pages":"174-177"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83828776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820805
E. Takeda, T. Wantanabe, S. Kimura, K. Suzuki, K. Sasaki
The development of silicon technology is opening the new era of "systems on silicon". That is, a large-scale memory will be integrated with a CPU and other logic macros. These kinds of chips, so-called system LSIs, have a promising future, especially in mobile systems for advanced multimedia applications since they feature high data-transfer rate, low I/O power dissipation, and system miniaturization. However, such a system-oriented LSI causes new technical problems such as increases in subthreshold leakage current, process cost, and design complexity. It will also have a significant influence on the business strategies of LSI makers. This paper reviews the features and issues of embedded DRAMs and system LSIs and then introduces advanced technologies for designing and fabricating them.
{"title":"Technology frontiers towards the 21st century: embedded DRAM and the system LSIs-process, circuits, and design technology","authors":"E. Takeda, T. Wantanabe, S. Kimura, K. Suzuki, K. Sasaki","doi":"10.1109/ICVC.1999.820805","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820805","url":null,"abstract":"The development of silicon technology is opening the new era of \"systems on silicon\". That is, a large-scale memory will be integrated with a CPU and other logic macros. These kinds of chips, so-called system LSIs, have a promising future, especially in mobile systems for advanced multimedia applications since they feature high data-transfer rate, low I/O power dissipation, and system miniaturization. However, such a system-oriented LSI causes new technical problems such as increases in subthreshold leakage current, process cost, and design complexity. It will also have a significant influence on the business strategies of LSI makers. This paper reviews the features and issues of embedded DRAMs and system LSIs and then introduces advanced technologies for designing and fabricating them.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"18 1","pages":"11-21"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80491754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820813
Sang-Yaol Hao, Ki-Hyan Kim, Young Hwan Kim
This paper proposes a critical path analysis algorithm that considers the effects of the signal transition time. First, the proposed algorithm finds the possible minimum transition time and the possible maximum transition time. Then, within the range, it extracts the maximum delay of each gate and computes the PERT delay. Finally, it performs depth first search under searching condition that the sum of a current searching path and a PERT delay is larger than that of critical path evaluated already. Experimental results show that the proposed algorithm finds the correct critical paths of the ISCAS 85 benchmark circuits where the existing critical path analysis methods fail. Experimental results also show that the complexity of the proposed algorithm is linear with the circuit size.
{"title":"Critical path analysis considering the signal transition time","authors":"Sang-Yaol Hao, Ki-Hyan Kim, Young Hwan Kim","doi":"10.1109/ICVC.1999.820813","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820813","url":null,"abstract":"This paper proposes a critical path analysis algorithm that considers the effects of the signal transition time. First, the proposed algorithm finds the possible minimum transition time and the possible maximum transition time. Then, within the range, it extracts the maximum delay of each gate and computes the PERT delay. Finally, it performs depth first search under searching condition that the sum of a current searching path and a PERT delay is larger than that of critical path evaluated already. Experimental results show that the proposed algorithm finds the correct critical paths of the ISCAS 85 benchmark circuits where the existing critical path analysis methods fail. Experimental results also show that the complexity of the proposed algorithm is linear with the circuit size.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"37-40"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88068654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820895
S. Lee, I. Cho, S. Park, H. Choi, N. Kim, Jong-Kwan Kim, S. Han, Kyungho Lee
We have investigated the degradation of thick gate oxide in the conventional dual gate oxide process. To meet the requirement of integrating 3 and 6 nm dual gate oxide operating under the bias of 1.8 and 2.5 V, respectively, on a single chip, a novel dual gate oxide process flow, without gate oxide thinning at STI corner, is presented. Our new integration of dual gate oxide shows an improved gate oxide reliability compared to the conventional process.
{"title":"Gate oxide thinning effects at the edge of shallow trench isolation in the dual gate oxide process","authors":"S. Lee, I. Cho, S. Park, H. Choi, N. Kim, Jong-Kwan Kim, S. Han, Kyungho Lee","doi":"10.1109/ICVC.1999.820895","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820895","url":null,"abstract":"We have investigated the degradation of thick gate oxide in the conventional dual gate oxide process. To meet the requirement of integrating 3 and 6 nm dual gate oxide operating under the bias of 1.8 and 2.5 V, respectively, on a single chip, a novel dual gate oxide process flow, without gate oxide thinning at STI corner, is presented. Our new integration of dual gate oxide shows an improved gate oxide reliability compared to the conventional process.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"31 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88512058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820907
Chi-Weon Yoon, Yon-Kyun Im, Seon‐Ho Han, H. Yoo, T. Jung
We propose a Synchronous Pipelined DRAM (SP-DRAM) architecture which has a fast row-cycle. Pipeline circuitry is inserted in the row path and multiple SRAM buffers are integrated in the DRAM to reduce row latency. The data transfer rate of the SP-DRAM is measured to be faster by 40% than SDRAM and by 20% than VCM as a result of system level performance analysis. A partial activation scheme is adopted in the cell core to reduce unnecessary power consumption. The SP-DRAM can maintain compatibility with a conventional SDRAM interface with negligible performance degradation.
{"title":"A fast synchronous pipelined DRAM (SP-DRAM) architecture with SRAM buffers","authors":"Chi-Weon Yoon, Yon-Kyun Im, Seon‐Ho Han, H. Yoo, T. Jung","doi":"10.1109/ICVC.1999.820907","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820907","url":null,"abstract":"We propose a Synchronous Pipelined DRAM (SP-DRAM) architecture which has a fast row-cycle. Pipeline circuitry is inserted in the row path and multiple SRAM buffers are integrated in the DRAM to reduce row latency. The data transfer rate of the SP-DRAM is measured to be faster by 40% than SDRAM and by 20% than VCM as a result of system level performance analysis. A partial activation scheme is adopted in the cell core to reduce unnecessary power consumption. The SP-DRAM can maintain compatibility with a conventional SDRAM interface with negligible performance degradation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"133 1","pages":"285-288"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74177048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820993
Dong-Chual Kang, Chang-Il Kim, Han Park, Sang-Bock Cho, Jong-Hwa Lee
An 8-bit subranging neuron MOSFET A/D converter circuit was designed and implemented. This neuron MOS A/D converter shows flexible operation and simple structure comparing with the common CMOS A/DC circuit. It is composed of two 4-bit A/D subconverters, 4-bit D/A subconverter, subtracter and 8-bit output latch, each subcircuit was simulated separately by using HSPICE.
{"title":"Design of an 8-bit neuron MOSFET A/D converter using subranging method","authors":"Dong-Chual Kang, Chang-Il Kim, Han Park, Sang-Bock Cho, Jong-Hwa Lee","doi":"10.1109/ICVC.1999.820993","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820993","url":null,"abstract":"An 8-bit subranging neuron MOSFET A/D converter circuit was designed and implemented. This neuron MOS A/D converter shows flexible operation and simple structure comparing with the common CMOS A/DC circuit. It is composed of two 4-bit A/D subconverters, 4-bit D/A subconverter, subtracter and 8-bit output latch, each subcircuit was simulated separately by using HSPICE.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"55 1","pages":"533-536"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74668439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821011
Joo-Ho Lee, Seon‐Ho Han, H. Yoo
This paper describes a temperature sensor and an ADC (analog-to-digital converter) for use in the DTCXO (Digitally Temperature Compensated Crystal Oscillator). The circuits were implemented in a standard 0.6 um CMOS process with two-poly and three-metal layers. The combination of the sensor and ADC draws 1.14 mW at 3.3 kS/s from a 3.3-V supply and total area is only 1 mm/sup 2/.
本文介绍了用于数字温度补偿晶体振荡器(DTCXO)的温度传感器和模数转换器(ADC)。电路在标准的0.6 um CMOS工艺中实现，具有双聚层和三金属层。传感器和ADC的组合在3.3 k /s下从3.3 v电源输出1.14 mW，总面积仅为1 mm/sup 2/。
{"title":"The CMOS temperature sensor and cyclic ADC for low power single chip DTCXO","authors":"Joo-Ho Lee, Seon‐Ho Han, H. Yoo","doi":"10.1109/ICVC.1999.821011","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821011","url":null,"abstract":"This paper describes a temperature sensor and an ADC (analog-to-digital converter) for use in the DTCXO (Digitally Temperature Compensated Crystal Oscillator). The circuits were implemented in a standard 0.6 um CMOS process with two-poly and three-metal layers. The combination of the sensor and ADC draws 1.14 mW at 3.3 kS/s from a 3.3-V supply and total area is only 1 mm/sup 2/.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"599-601"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76635434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820948
Jae-Jin Kim, S. Byun, Hi-Seok Kim
In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algorithm.
{"title":"Development of technology mapping algorithm for CPLD under time constraint","authors":"Jae-Jin Kim, S. Byun, Hi-Seok Kim","doi":"10.1109/ICVC.1999.820948","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820948","url":null,"abstract":"In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algorithm.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"279 1","pages":"411-414"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77551998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820987
J. Lim, Y.K. Kim, S. Choi, J. Lee, Y. Kim, B.T. Lee, H.S. Park, Y.W. Park, S.I. Lee
A poly-Si/Al/sub 2/O/sub 3//poly-Si capacitor is developed for the simple integration of 256 Mb DRAM and beyond. The oxide equivalent thickness (T/sub 0xeq/) of the Al/sub 2/O/sub 3/ capacitor was achieved as small as 28 nm, which is about 1.7 times smaller than that of advanced NO capacitor. Especially, the pre-treatment before the deposition of Al/sub 2/O/sub 3/ film plays a crucial role for stable device performance. Moreover, one of the distinguished characteristics of the Al/sub 2/O/sub 3/ capacitor is that the capacitance was even enhanced by performing the conventional DRAM processes, including the high temperature planarization method known as BPSG flow, without degrading the leakage characteristics.
{"title":"Novel Al/sub 2/O/sub 3/ capacitor for high density DRAMs","authors":"J. Lim, Y.K. Kim, S. Choi, J. Lee, Y. Kim, B.T. Lee, H.S. Park, Y.W. Park, S.I. Lee","doi":"10.1109/ICVC.1999.820987","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820987","url":null,"abstract":"A poly-Si/Al/sub 2/O/sub 3//poly-Si capacitor is developed for the simple integration of 256 Mb DRAM and beyond. The oxide equivalent thickness (T/sub 0xeq/) of the Al/sub 2/O/sub 3/ capacitor was achieved as small as 28 nm, which is about 1.7 times smaller than that of advanced NO capacitor. Especially, the pre-treatment before the deposition of Al/sub 2/O/sub 3/ film plays a crucial role for stable device performance. Moreover, one of the distinguished characteristics of the Al/sub 2/O/sub 3/ capacitor is that the capacitance was even enhanced by performing the conventional DRAM processes, including the high temperature planarization method known as BPSG flow, without degrading the leakage characteristics.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"26 1","pages":"506-509"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79047077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820908
B. Kong, D. Kang, Young-Hyun Jun
Novel low-voltage CMOS logic family, called bootstrapped latched CMOS logic (BLCL), and demand-on-boosting bootstrapped latched CMOS logic (DB-BLCL) are proposed for low-voltage and low-power applications. These circuits improve operation speed at low supply voltage region for driving a large capacitive load by boosting internal nodes beyond the power supply or below the ground using a single bootstrap capacitor. They provide larger bootstrap voltages than the conventional CMOS bootstrap circuit by eliminating charge loss from the bootstrap nodes. Moreover, each bootstrap node in DB-BLCL circuit is boosted on demand depending on the input and output values to minimize the average power consumption and the drivers are transiently overdriven during only the output transition period for device reliability. These circuits were designed using 0.35 /spl mu/m CMOS process technology. The comparison result indicates that BLCL provides switching speed improvements of 15-30% with comparable power consumption as compared to the conventional bootstrapped circuit. In addition, DB-BLCL obtains the same switching speed improvement as BLCL with 33% less power consumption due to unique demand-on bootstrapping capability.
{"title":"A bootstrapped CMOS circuit technique for low-voltage application","authors":"B. Kong, D. Kang, Young-Hyun Jun","doi":"10.1109/ICVC.1999.820908","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820908","url":null,"abstract":"Novel low-voltage CMOS logic family, called bootstrapped latched CMOS logic (BLCL), and demand-on-boosting bootstrapped latched CMOS logic (DB-BLCL) are proposed for low-voltage and low-power applications. These circuits improve operation speed at low supply voltage region for driving a large capacitive load by boosting internal nodes beyond the power supply or below the ground using a single bootstrap capacitor. They provide larger bootstrap voltages than the conventional CMOS bootstrap circuit by eliminating charge loss from the bootstrap nodes. Moreover, each bootstrap node in DB-BLCL circuit is boosted on demand depending on the input and output values to minimize the average power consumption and the drivers are transiently overdriven during only the output transition period for device reliability. These circuits were designed using 0.35 /spl mu/m CMOS process technology. The comparison result indicates that BLCL provides switching speed improvements of 15-30% with comparable power consumption as compared to the conventional bootstrapped circuit. In addition, DB-BLCL obtains the same switching speed improvement as BLCL with 33% less power consumption due to unique demand-on bootstrapping capability.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"4 1","pages":"289-292"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80890337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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