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ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)最新文献

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A low-complexity VLSI architecture of multidimensional TCM decoder for ADSL ADSL多维TCM解码器的低复杂度VLSI结构
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.821005
Keum-Seok Lee, Jaeseok Kim
We propose a low complexity M-D (multidimensional) TCM decoder VLSI architecture for ADSL System. We use the shared subset decoder module by modifying the whole decoding procedure. Also we improve the decoding speed by using the MSA (module set area) operation, which removes multiplication in 4D metric calculation. So the proposed TCM decoder reduces chip area and can be adopted in high-speed xDSL system.
提出了一种用于ADSL系统的低复杂度M-D(多维)TCM解码器VLSI架构。我们通过修改整个解码过程,使用了共享子集解码器模块。此外,我们还采用了MSA(模块集面积)运算,消除了四维度量计算中的乘法运算,提高了解码速度。因此,该解码器减小了芯片面积,可用于高速xDSL系统。
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引用次数: 0
Analysis of sidewall films formed during Si etching with photoresist and nitride mask 光刻胶和氮化掩膜在Si蚀刻过程中形成的侧壁膜分析
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820856
So‐Young Nam, Sang‐Do Lee, J. Ha, Jin-Won Park
The trench sidewall passivation films produced with photoresist (PR) mask and nitride mask were examined in two different etching systems of helicon and inductively coupled plasma (ICP) types. Compared to the trench profiles obtained from the helicon etching system, under the ICP etching system, the trench profiles were observed to be more tapered with thicker sidewall films. X-ray Photoelectron Spectroscopy (XPS) analysis results indicated that N/sub 2/ addition to Cl/sub 2//HBr/O/sub 2/ plasma induced the formation of Si-N bonds in the sidewall films in addition to Si-O and Si-Br bonds. Moreover, the sidewall films formed in Cl/sub 2//HBr/O/sub 2/ plasma showed higher oxygen intensities and higher binding energies compared to those formed in Cl/sub 2//HBr/N/sub 2//O/sub 2/ plasma. Nitride mask polymer films seem to be deposited thicker on the mask film for both helicon and ICP type etchers in comparison with the PR mask scheme. The oxygen component appeared more intensely on the silicon substrate in the helicon plasma etcher with the PR mask scheme, contrary to the nitride mask scheme. Cone-shaped microscopic Si defects were detected during Si trench etching regardless of etching system, but wafers etched with the nitride mask showed more defects than those etched with photoresist mask.
在螺旋和电感耦合等离子体两种不同的蚀刻体系中,研究了光刻胶(PR)掩膜和氮化膜制备的沟槽侧壁钝化膜。与螺旋刻蚀系统得到的沟槽轮廓相比,ICP刻蚀系统得到的沟槽轮廓更加锥形,侧壁膜也更厚。x射线光电子能谱(XPS)分析结果表明,除了Si-O和Si-Br键外,N/sub - 2/ Cl/sub - 2/ HBr/O/sub - 2/等离子体的加入还诱导了侧壁膜中Si-N键的形成。与Cl/sub 2//HBr/N/sub 2//O/sub 2/等离子体相比,在Cl/sub 2//HBr/O/sub 2/等离子体中形成的侧壁膜表现出更高的氧强度和结合能。与PR掩膜方案相比,氮化物掩膜聚合物薄膜似乎在螺旋和ICP型蚀刻器的掩膜上沉积得更厚。与氮化掩膜方案相反,PR掩膜方案在螺旋等离子体蚀刻器的硅衬底上出现了更强烈的氧组分。无论采用何种蚀刻体系,在硅沟槽蚀刻过程中都能检测到锥形的微观硅缺陷,但氮化膜蚀刻的硅缺陷比光刻膜蚀刻的硅缺陷多。
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引用次数: 0
A 2048 complex point FFT processor for DAB systems 用于DAB系统的2048复点FFT处理器
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820915
Se Ho Park, Dong Hwan Kim, D. Han, Kyu Lee, S. Park, J. Choi
In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result, the proposed structure brings about the 55% chip size reduction compared with the conventional approach.
本文从顺序数据处理的角度提出了一种单片2048复点FFT的实现方法。为了减少顺序处理2k复杂数据所需的芯片面积,采用了类似dram的流水线换向器结构。16点FFT是整个FFT芯片的基本构建块,2048点FFT由具有5级基数4和1级基数2的级联块组成。由于每个阶段都需要在保持适当信噪比的同时对结果位进行舍入,因此使用收敛块浮点(CBFP)算法进行有效的内部位舍入。因此,与传统方法相比,所提出的结构使芯片尺寸减小55%。
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引用次数: 5
A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method 一个4- 400mhz抖动抑制延迟锁定环分频方法
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820925
Y. Koo, Joonbae Park, Joonbae Park, Wonchan Kim
This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.
本文描述了一种用于片上时钟缓冲器的新的DLL结构。它通过粗调和精调两步实现采集。基于分频方法的粗调谐在有限的采集时间下扩大了操作范围。它允许微调块的小增益,这有助于抑制抖动。采用0.8 /spl mu/m CMOS技术制造的测试芯片工作在4-400 MHz范围内。它具有8.13 ps的RMS抖动,在300 MHz时耗散70.0 mW。
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引用次数: 2
Silicon MOS memory with self-aligned quantum dot on narrow channel 窄通道自对准量子点硅MOS存储器
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820869
Sangyeon Han, T. Hwang, Hyungcheol Shin
The essential technology for fabricating the quantum dot flash memory is nanolithography. With E-beam patterning technology and Cl/sub 2/ based RIE (Reactive Ion Etching), a self-aligned 100 nm wide quantum dot and 100 nm wide narrow channel were fabricated. Also, quantum dot flash memory was fabricated. The memory operation was observed. The threshold voltage shift was about 1.0 V and the corresponding number of electrons involved in this operation was estimated to be about 70. The memory also showed excellent retention characteristics.
制造量子点闪存的关键技术是纳米光刻技术。利用电子束图像化技术和基于Cl/sub - 2/的RIE(反应离子蚀刻)技术,制备了自对准的100 nm宽量子点和100 nm宽窄通道。同时,制备了量子点闪存。观察内存操作。阈值电压位移约为1.0 V,该操作所涉及的相应电子数估计约为70个。记忆也表现出优异的保留特性。
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引用次数: 0
A SPICE compatible single electron transistor (SET) transient model SPICE兼容单电子晶体管(SET)瞬态模型
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820945
Y. Yu, Y. Jung, S. Hwang, D. Ahn
In this paper, we introduce a SPICE compatibile SET transient model. The basic recipe of our model is similar to CAMSET but we have adopted a much simpler way for the truncation of the number of charge states required in the calculation. The validity of our model has been checked by comparing our transient calculation with the result of the steady-state master equation method.
本文介绍了一种与SPICE兼容的SET瞬态模型。我们的模型的基本配方与CAMSET相似,但我们采用了一种更简单的方法来截断计算中所需的电荷状态数。通过与稳态主方程法计算结果的比较,验证了模型的有效性。
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引用次数: 1
Thermally stable W-bit line technology for ULSI device application 用于ULSI器件的热稳定w位线技术
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820975
Young Soo Kim, N. Park, J. K. Kim, S. Han, Kyungho Lee
We have investigated the various types of diffusion barriers for the thermally stable W-bit line structure. We estimated the thermal stability and the electrical characteristics of various barrier structures after annealing at 850/spl deg/C and then optimized the W-bit line process. A newly developed PVD-Ti/PVD-TiN/RTP/Strip/PVD-TiN/CVD-W structure showed good integrity with the W-bit line after high temperature processing. It is concluded that the prevention of oxygen penetration during silicidation is most important for the formation of a uniform silicide layer and better contact characteristics.
我们研究了热稳定w位线结构中不同类型的扩散势垒。我们估计了850/spl℃退火后各种势垒结构的热稳定性和电学特性,并对W-bit线工艺进行了优化。经高温处理后的PVD-Ti/PVD-TiN/RTP/Strip/PVD-TiN/CVD-W结构与w位线具有良好的完整性。结果表明,防止氧在硅化过程中的渗透对硅化层的形成和接触特性的改善至关重要。
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引用次数: 0
High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme 采用动态超驱动和自适应传感方案的高速低摆接口电路
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820940
Chang-Ki Kwon, KwangMyoung Rho, Kwyro Lee
In this paper, we propose novel interface circuits using Dynamic Over-Driving (DOD) and Adaptive Sensing (AS) scheme for high speed and energy-efficient interface on a chip. Our AS-receiver makes it possible to use very low swing because of its good noise immunity against the threshold voltage variations, and our DOD-driver reduces data transmission time even through heavy load capacitances. The simulation results show that the reduction of approximately 20% speed and 40% energy consumption is achieved for the proposed circuits, as compared with the conventional full CMOS inverters at low supply voltage (=1.5 V).
在本文中,我们提出了一种新的接口电路,采用动态过度驱动(DOD)和自适应传感(AS)方案实现芯片上的高速节能接口。我们的as接收器可以使用非常低的摆幅,因为它对阈值电压变化具有良好的抗噪声性,我们的dod驱动器即使在高负载电容下也可以减少数据传输时间。仿真结果表明,在低电源电压(=1.5 V)下,与传统的全CMOS逆变器相比,该电路的速度降低了约20%,能耗降低了40%。
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引用次数: 13
Enhancing uniformity of borderless via resistance by HDP oxide technology 利用HDP氧化技术提高无边界通孔电阻的均匀性
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820962
Yong-Sik Jung, C. Kim, J. Kim, J. Han, Y. Seo, Y. Jeon
This paper describes part of the technology of a five level metal interconnection method for a 25C07 (gate CD: 0.25 /spl mu/m, metal1 pitch design rule: 0.76 /spl mu/m) CMOS device. In order to achieve the stable interconnection of metal lines, first we should open the via holes very clearly and uniformly through a via patterning/etching process, and not only the strong barrier metal (Ti/TiN) property for surrounding the via hole, especially the bottom corner, but also the proper W filling in the via hole, is required. Another important factor is the Intermetal Dielectric Material (IMD). When we have no room (almost zero) of the via hole to endlap the bottom metal, the IMD material can give effect to the via resistance. The objective of this experiment is to look at the via resistance difference in the zig-zag test pattern (via CD: 0.33 /spl mu/m, via endlap to bottom metal: 0.1 /spl mu/m, via sidelap to bottom metal: 0.02 /spl mu/m, metal width/space: 0.4 /spl mu/m/0.36 /spl mu/m) due to the IMD materials (HDP USG vs. SOG) and, finally, compare the device yield. High Density Plasma CVD (HDP USG) and SOG (Spin On Glass) were performed as a split corner of IMD layer deposition. Every process step, from pad oxidation to passivation, except IMD layer deposition( HDP CVD and. SOG coating and cure), was done simultaneously under the completely same condition. In this work, we monitored the "process in line data" such as global planarization of post IMD CMP and via photo CD/etch CD to correlate the electrical via resistance data with "process in line data".
本文介绍了25C07(栅极CD: 0.25 /spl mu/m,金属节距设计规则:0.76 /spl mu/m) CMOS器件的五级金属互连方法的部分技术。为了实现金属线的稳定互连,首先我们应该通过通孔图案/蚀刻工艺非常清晰和均匀地打开通孔,并且不仅需要在通孔周围,特别是底角具有强阻挡金属(Ti/TiN)性能,而且还需要在通孔中填充适当的W。另一个重要因素是金属间介电材料(IMD)。当我们没有空间(几乎为零)的通孔来接底金属时,IMD材料可以对通孔电阻产生影响。本实验的目的是观察由于IMD材料(HDP USG与SOG)导致的锯齿形测试模式(通过CD: 0.33 /spl mu/m,通过端接到底部金属:0.1 /spl mu/m,通过侧接到底部金属:0.02 /spl mu/m,金属宽度/空间:0.4 /spl mu/m/0.36 /spl mu/m)中的通孔电阻差异,最后比较器件成品率。高密度等离子体CVD (HDP USG)和SOG (Spin On Glass)作为IMD层沉积的分角。从焊盘氧化到钝化,除了IMD层沉积(HDP CVD和。SOG涂层和固化在完全相同的条件下同时进行。在这项工作中,我们监测了“在线过程数据”,如IMD后CMP的全球平面化,并通过照片CD/蚀刻CD将电阻数据与“在线过程数据”联系起来。
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引用次数: 0
Optimum barrier layer for Al-PMD (preferential metal deposition) process Al-PMD(优先金属沉积)工艺的最佳阻挡层
Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820884
B. Kim, Jong Myeong Lee, Y. Chae, S. Kang, G. Choi, Y. Park, Sang In Lee
The barrier properties and the reliability of Al to Si contacts using different types of TiN in the Al-PMD process are investigated. The Al-PMD process is shown to be an excellent metallization technique for high density devices such as Giga-bit DRAMs and beyond when ACVD-TiN is used as a barrier layer. ACVD-TiN has the best diffusion barrier properties due to its high density and good conformality.
研究了Al- pmd工艺中不同类型TiN对Al- Si触点的阻挡性能和可靠性。当ACVD-TiN用作阻挡层时,Al-PMD工艺被证明是一种出色的高密度器件金属化技术,如千兆比特dram及以上。ACVD-TiN密度高,共形性好,具有较好的扩散阻挡性能。
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引用次数: 0
期刊
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)
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