Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821005
Keum-Seok Lee, Jaeseok Kim
We propose a low complexity M-D (multidimensional) TCM decoder VLSI architecture for ADSL System. We use the shared subset decoder module by modifying the whole decoding procedure. Also we improve the decoding speed by using the MSA (module set area) operation, which removes multiplication in 4D metric calculation. So the proposed TCM decoder reduces chip area and can be adopted in high-speed xDSL system.
{"title":"A low-complexity VLSI architecture of multidimensional TCM decoder for ADSL","authors":"Keum-Seok Lee, Jaeseok Kim","doi":"10.1109/ICVC.1999.821005","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821005","url":null,"abstract":"We propose a low complexity M-D (multidimensional) TCM decoder VLSI architecture for ADSL System. We use the shared subset decoder module by modifying the whole decoding procedure. Also we improve the decoding speed by using the MSA (module set area) operation, which removes multiplication in 4D metric calculation. So the proposed TCM decoder reduces chip area and can be adopted in high-speed xDSL system.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"63 1","pages":"578-581"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86500203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820856
So‐Young Nam, Sang‐Do Lee, J. Ha, Jin-Won Park
The trench sidewall passivation films produced with photoresist (PR) mask and nitride mask were examined in two different etching systems of helicon and inductively coupled plasma (ICP) types. Compared to the trench profiles obtained from the helicon etching system, under the ICP etching system, the trench profiles were observed to be more tapered with thicker sidewall films. X-ray Photoelectron Spectroscopy (XPS) analysis results indicated that N/sub 2/ addition to Cl/sub 2//HBr/O/sub 2/ plasma induced the formation of Si-N bonds in the sidewall films in addition to Si-O and Si-Br bonds. Moreover, the sidewall films formed in Cl/sub 2//HBr/O/sub 2/ plasma showed higher oxygen intensities and higher binding energies compared to those formed in Cl/sub 2//HBr/N/sub 2//O/sub 2/ plasma. Nitride mask polymer films seem to be deposited thicker on the mask film for both helicon and ICP type etchers in comparison with the PR mask scheme. The oxygen component appeared more intensely on the silicon substrate in the helicon plasma etcher with the PR mask scheme, contrary to the nitride mask scheme. Cone-shaped microscopic Si defects were detected during Si trench etching regardless of etching system, but wafers etched with the nitride mask showed more defects than those etched with photoresist mask.
{"title":"Analysis of sidewall films formed during Si etching with photoresist and nitride mask","authors":"So‐Young Nam, Sang‐Do Lee, J. Ha, Jin-Won Park","doi":"10.1109/ICVC.1999.820856","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820856","url":null,"abstract":"The trench sidewall passivation films produced with photoresist (PR) mask and nitride mask were examined in two different etching systems of helicon and inductively coupled plasma (ICP) types. Compared to the trench profiles obtained from the helicon etching system, under the ICP etching system, the trench profiles were observed to be more tapered with thicker sidewall films. X-ray Photoelectron Spectroscopy (XPS) analysis results indicated that N/sub 2/ addition to Cl/sub 2//HBr/O/sub 2/ plasma induced the formation of Si-N bonds in the sidewall films in addition to Si-O and Si-Br bonds. Moreover, the sidewall films formed in Cl/sub 2//HBr/O/sub 2/ plasma showed higher oxygen intensities and higher binding energies compared to those formed in Cl/sub 2//HBr/N/sub 2//O/sub 2/ plasma. Nitride mask polymer films seem to be deposited thicker on the mask film for both helicon and ICP type etchers in comparison with the PR mask scheme. The oxygen component appeared more intensely on the silicon substrate in the helicon plasma etcher with the PR mask scheme, contrary to the nitride mask scheme. Cone-shaped microscopic Si defects were detected during Si trench etching regardless of etching system, but wafers etched with the nitride mask showed more defects than those etched with photoresist mask.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"21 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87281595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820915
Se Ho Park, Dong Hwan Kim, D. Han, Kyu Lee, S. Park, J. Choi
In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result, the proposed structure brings about the 55% chip size reduction compared with the conventional approach.
{"title":"A 2048 complex point FFT processor for DAB systems","authors":"Se Ho Park, Dong Hwan Kim, D. Han, Kyu Lee, S. Park, J. Choi","doi":"10.1109/ICVC.1999.820915","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820915","url":null,"abstract":"In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result, the proposed structure brings about the 55% chip size reduction compared with the conventional approach.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"15 1","pages":"309-312"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90910597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820925
Y. Koo, Joonbae Park, Joonbae Park, Wonchan Kim
This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.
{"title":"A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method","authors":"Y. Koo, Joonbae Park, Joonbae Park, Wonchan Kim","doi":"10.1109/ICVC.1999.820925","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820925","url":null,"abstract":"This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 /spl mu/m CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"60 1","pages":"339-341"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91233519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820869
Sangyeon Han, T. Hwang, Hyungcheol Shin
The essential technology for fabricating the quantum dot flash memory is nanolithography. With E-beam patterning technology and Cl/sub 2/ based RIE (Reactive Ion Etching), a self-aligned 100 nm wide quantum dot and 100 nm wide narrow channel were fabricated. Also, quantum dot flash memory was fabricated. The memory operation was observed. The threshold voltage shift was about 1.0 V and the corresponding number of electrons involved in this operation was estimated to be about 70. The memory also showed excellent retention characteristics.
{"title":"Silicon MOS memory with self-aligned quantum dot on narrow channel","authors":"Sangyeon Han, T. Hwang, Hyungcheol Shin","doi":"10.1109/ICVC.1999.820869","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820869","url":null,"abstract":"The essential technology for fabricating the quantum dot flash memory is nanolithography. With E-beam patterning technology and Cl/sub 2/ based RIE (Reactive Ion Etching), a self-aligned 100 nm wide quantum dot and 100 nm wide narrow channel were fabricated. Also, quantum dot flash memory was fabricated. The memory operation was observed. The threshold voltage shift was about 1.0 V and the corresponding number of electrons involved in this operation was estimated to be about 70. The memory also showed excellent retention characteristics.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"6 1","pages":"187-189"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84595889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820945
Y. Yu, Y. Jung, S. Hwang, D. Ahn
In this paper, we introduce a SPICE compatibile SET transient model. The basic recipe of our model is similar to CAMSET but we have adopted a much simpler way for the truncation of the number of charge states required in the calculation. The validity of our model has been checked by comparing our transient calculation with the result of the steady-state master equation method.
{"title":"A SPICE compatible single electron transistor (SET) transient model","authors":"Y. Yu, Y. Jung, S. Hwang, D. Ahn","doi":"10.1109/ICVC.1999.820945","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820945","url":null,"abstract":"In this paper, we introduce a SPICE compatibile SET transient model. The basic recipe of our model is similar to CAMSET but we have adopted a much simpler way for the truncation of the number of charge states required in the calculation. The validity of our model has been checked by comparing our transient calculation with the result of the steady-state master equation method.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"3 1","pages":"403-406"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83265814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820975
Young Soo Kim, N. Park, J. K. Kim, S. Han, Kyungho Lee
We have investigated the various types of diffusion barriers for the thermally stable W-bit line structure. We estimated the thermal stability and the electrical characteristics of various barrier structures after annealing at 850/spl deg/C and then optimized the W-bit line process. A newly developed PVD-Ti/PVD-TiN/RTP/Strip/PVD-TiN/CVD-W structure showed good integrity with the W-bit line after high temperature processing. It is concluded that the prevention of oxygen penetration during silicidation is most important for the formation of a uniform silicide layer and better contact characteristics.
{"title":"Thermally stable W-bit line technology for ULSI device application","authors":"Young Soo Kim, N. Park, J. K. Kim, S. Han, Kyungho Lee","doi":"10.1109/ICVC.1999.820975","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820975","url":null,"abstract":"We have investigated the various types of diffusion barriers for the thermally stable W-bit line structure. We estimated the thermal stability and the electrical characteristics of various barrier structures after annealing at 850/spl deg/C and then optimized the W-bit line process. A newly developed PVD-Ti/PVD-TiN/RTP/Strip/PVD-TiN/CVD-W structure showed good integrity with the W-bit line after high temperature processing. It is concluded that the prevention of oxygen penetration during silicidation is most important for the formation of a uniform silicide layer and better contact characteristics.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"7 1","pages":"480-483"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83896171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820940
Chang-Ki Kwon, KwangMyoung Rho, Kwyro Lee
In this paper, we propose novel interface circuits using Dynamic Over-Driving (DOD) and Adaptive Sensing (AS) scheme for high speed and energy-efficient interface on a chip. Our AS-receiver makes it possible to use very low swing because of its good noise immunity against the threshold voltage variations, and our DOD-driver reduces data transmission time even through heavy load capacitances. The simulation results show that the reduction of approximately 20% speed and 40% energy consumption is achieved for the proposed circuits, as compared with the conventional full CMOS inverters at low supply voltage (=1.5 V).
{"title":"High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme","authors":"Chang-Ki Kwon, KwangMyoung Rho, Kwyro Lee","doi":"10.1109/ICVC.1999.820940","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820940","url":null,"abstract":"In this paper, we propose novel interface circuits using Dynamic Over-Driving (DOD) and Adaptive Sensing (AS) scheme for high speed and energy-efficient interface on a chip. Our AS-receiver makes it possible to use very low swing because of its good noise immunity against the threshold voltage variations, and our DOD-driver reduces data transmission time even through heavy load capacitances. The simulation results show that the reduction of approximately 20% speed and 40% energy consumption is achieved for the proposed circuits, as compared with the conventional full CMOS inverters at low supply voltage (=1.5 V).","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"4 1","pages":"388-391"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84116986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820962
Yong-Sik Jung, C. Kim, J. Kim, J. Han, Y. Seo, Y. Jeon
This paper describes part of the technology of a five level metal interconnection method for a 25C07 (gate CD: 0.25 /spl mu/m, metal1 pitch design rule: 0.76 /spl mu/m) CMOS device. In order to achieve the stable interconnection of metal lines, first we should open the via holes very clearly and uniformly through a via patterning/etching process, and not only the strong barrier metal (Ti/TiN) property for surrounding the via hole, especially the bottom corner, but also the proper W filling in the via hole, is required. Another important factor is the Intermetal Dielectric Material (IMD). When we have no room (almost zero) of the via hole to endlap the bottom metal, the IMD material can give effect to the via resistance. The objective of this experiment is to look at the via resistance difference in the zig-zag test pattern (via CD: 0.33 /spl mu/m, via endlap to bottom metal: 0.1 /spl mu/m, via sidelap to bottom metal: 0.02 /spl mu/m, metal width/space: 0.4 /spl mu/m/0.36 /spl mu/m) due to the IMD materials (HDP USG vs. SOG) and, finally, compare the device yield. High Density Plasma CVD (HDP USG) and SOG (Spin On Glass) were performed as a split corner of IMD layer deposition. Every process step, from pad oxidation to passivation, except IMD layer deposition( HDP CVD and. SOG coating and cure), was done simultaneously under the completely same condition. In this work, we monitored the "process in line data" such as global planarization of post IMD CMP and via photo CD/etch CD to correlate the electrical via resistance data with "process in line data".
{"title":"Enhancing uniformity of borderless via resistance by HDP oxide technology","authors":"Yong-Sik Jung, C. Kim, J. Kim, J. Han, Y. Seo, Y. Jeon","doi":"10.1109/ICVC.1999.820962","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820962","url":null,"abstract":"This paper describes part of the technology of a five level metal interconnection method for a 25C07 (gate CD: 0.25 /spl mu/m, metal1 pitch design rule: 0.76 /spl mu/m) CMOS device. In order to achieve the stable interconnection of metal lines, first we should open the via holes very clearly and uniformly through a via patterning/etching process, and not only the strong barrier metal (Ti/TiN) property for surrounding the via hole, especially the bottom corner, but also the proper W filling in the via hole, is required. Another important factor is the Intermetal Dielectric Material (IMD). When we have no room (almost zero) of the via hole to endlap the bottom metal, the IMD material can give effect to the via resistance. The objective of this experiment is to look at the via resistance difference in the zig-zag test pattern (via CD: 0.33 /spl mu/m, via endlap to bottom metal: 0.1 /spl mu/m, via sidelap to bottom metal: 0.02 /spl mu/m, metal width/space: 0.4 /spl mu/m/0.36 /spl mu/m) due to the IMD materials (HDP USG vs. SOG) and, finally, compare the device yield. High Density Plasma CVD (HDP USG) and SOG (Spin On Glass) were performed as a split corner of IMD layer deposition. Every process step, from pad oxidation to passivation, except IMD layer deposition( HDP CVD and. SOG coating and cure), was done simultaneously under the completely same condition. In this work, we monitored the \"process in line data\" such as global planarization of post IMD CMP and via photo CD/etch CD to correlate the electrical via resistance data with \"process in line data\".","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"23 1","pages":"452-455"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78175742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820884
B. Kim, Jong Myeong Lee, Y. Chae, S. Kang, G. Choi, Y. Park, Sang In Lee
The barrier properties and the reliability of Al to Si contacts using different types of TiN in the Al-PMD process are investigated. The Al-PMD process is shown to be an excellent metallization technique for high density devices such as Giga-bit DRAMs and beyond when ACVD-TiN is used as a barrier layer. ACVD-TiN has the best diffusion barrier properties due to its high density and good conformality.
{"title":"Optimum barrier layer for Al-PMD (preferential metal deposition) process","authors":"B. Kim, Jong Myeong Lee, Y. Chae, S. Kang, G. Choi, Y. Park, Sang In Lee","doi":"10.1109/ICVC.1999.820884","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820884","url":null,"abstract":"The barrier properties and the reliability of Al to Si contacts using different types of TiN in the Al-PMD process are investigated. The Al-PMD process is shown to be an excellent metallization technique for high density devices such as Giga-bit DRAMs and beyond when ACVD-TiN is used as a barrier layer. ACVD-TiN has the best diffusion barrier properties due to its high density and good conformality.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"36 1","pages":"222-224"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75461415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}