Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380790
N. S. Ismail, I. Ahmad, H. Husain, S. Chuah
The objective of this research is to study electrical overstress (EOS) defect at gate oxide for various pulse widths in n-channel power metal-oxide-semiconductor field effect transistor (MOSFET). Moreover, this research also intent to develop power failure model for n-channel power MOSFET according to Tasca method. Electrical overstress does not have EOS standards and quantitative EOS design objectives to tackle this problem. Square pulse testing is used in this research due to easy to generate and simple to analyze. Time-to-failure (tf) is taken for power profiles modeling by observing abrupt drop in voltage waveform seen on oscilloscope. Tasca derived the thermal model by regarded the defect area as a sphere immersed in an infinite medium at ambient temperature. Result from failure analysis on all failed units had shown that hot spot formations begin at gate runner of the die and pulse stress given on VGS has cause gate oxide breakdown. Pulse power failure model for device n-channel power MOSFET can be obtained using Tasca method.
{"title":"Pulse Power Failure Model Of Power MOSFET Due To Electrical Overstress Using Tasca Method","authors":"N. S. Ismail, I. Ahmad, H. Husain, S. Chuah","doi":"10.1109/SMELEC.2006.380790","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380790","url":null,"abstract":"The objective of this research is to study electrical overstress (EOS) defect at gate oxide for various pulse widths in n-channel power metal-oxide-semiconductor field effect transistor (MOSFET). Moreover, this research also intent to develop power failure model for n-channel power MOSFET according to Tasca method. Electrical overstress does not have EOS standards and quantitative EOS design objectives to tackle this problem. Square pulse testing is used in this research due to easy to generate and simple to analyze. Time-to-failure (tf) is taken for power profiles modeling by observing abrupt drop in voltage waveform seen on oscilloscope. Tasca derived the thermal model by regarded the defect area as a sphere immersed in an infinite medium at ambient temperature. Result from failure analysis on all failed units had shown that hot spot formations begin at gate runner of the die and pulse stress given on VGS has cause gate oxide breakdown. Pulse power failure model for device n-channel power MOSFET can be obtained using Tasca method.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121322047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380733
M. Norman Fadhil Idham, O. Nurul Afzan, H. Soetedjo, A.R. Ahmad Ismat, I. Sabtu, Y. Mohamed Razman, A.M. Abdul Fatah
This paper presents a novel technique to obtain device characteristics of high electron mobility transistors (HEMT) structures based on the backgate contact method, thus avoiding the need for complete gate formation. The gate contact was prepared on the back side of the substrate. Measurements performed on various HEMT structures shows typical transistor characteristics. Significant changes in drain- source current as a function of backgate voltage bias was observed for different HEMT structures. Increasing the channel thickness from 8 to 26 nm shows an increase in the threshold voltage of the transistor and a noticeable variation in drain-source current. This result leads to an effective and novel technique for the determination of sample quality prior to the further fabrication process to obtain the complete device.
{"title":"Device Characteristics of HEMT Structures based on Backgate Contact Method","authors":"M. Norman Fadhil Idham, O. Nurul Afzan, H. Soetedjo, A.R. Ahmad Ismat, I. Sabtu, Y. Mohamed Razman, A.M. Abdul Fatah","doi":"10.1109/SMELEC.2006.380733","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380733","url":null,"abstract":"This paper presents a novel technique to obtain device characteristics of high electron mobility transistors (HEMT) structures based on the backgate contact method, thus avoiding the need for complete gate formation. The gate contact was prepared on the back side of the substrate. Measurements performed on various HEMT structures shows typical transistor characteristics. Significant changes in drain- source current as a function of backgate voltage bias was observed for different HEMT structures. Increasing the channel thickness from 8 to 26 nm shows an increase in the threshold voltage of the transistor and a noticeable variation in drain-source current. This result leads to an effective and novel technique for the determination of sample quality prior to the further fabrication process to obtain the complete device.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121952615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380768
Y. Teh, F. Mohd-Yasin, M. Reaz, A. Kordesch
This work presents a PC-based freeware CAD environment to design and tape out VLSI microelectronic circuits, starting from schematic capture all the way to a foundry compatible GDS II database. These free tools will help more Malaysian universities to set up low cost VLSI CAD laboratories and tape out circuits using Silterra's University Program. This will help grow local IC design culture and skills. FreeVLSI uses common freeware CAD tools: 5SPICE, LASI, and WinSPICE, and some custom scripts to interface between these tools. Currently FreeVLSI is able to cater to full custom design flow from schematic capture to circuit layout.
{"title":"A VLSI Design Framework with Freeware CAD Tools","authors":"Y. Teh, F. Mohd-Yasin, M. Reaz, A. Kordesch","doi":"10.1109/SMELEC.2006.380768","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380768","url":null,"abstract":"This work presents a PC-based freeware CAD environment to design and tape out VLSI microelectronic circuits, starting from schematic capture all the way to a foundry compatible GDS II database. These free tools will help more Malaysian universities to set up low cost VLSI CAD laboratories and tape out circuits using Silterra's University Program. This will help grow local IC design culture and skills. FreeVLSI uses common freeware CAD tools: 5SPICE, LASI, and WinSPICE, and some custom scripts to interface between these tools. Currently FreeVLSI is able to cater to full custom design flow from schematic capture to circuit layout.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122465136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380765
H. Younan, Tan Sock Khim, Li Kun, Z. Siping
In this paper, an ET high via resistance case was investigated. TEM/EDX technique was used for identification of the root cause. Failure mechanism of Al fluoride defects is discussed. Some preventive actions/solutions were implemented to improve the process margin and eliminate the problem.
{"title":"Studies on Failure Mechanism of ET High Via Resistance in Wafer Fabrication","authors":"H. Younan, Tan Sock Khim, Li Kun, Z. Siping","doi":"10.1109/SMELEC.2006.380765","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380765","url":null,"abstract":"In this paper, an ET high via resistance case was investigated. TEM/EDX technique was used for identification of the root cause. Failure mechanism of Al fluoride defects is discussed. Some preventive actions/solutions were implemented to improve the process margin and eliminate the problem.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123970337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381095
Chia-Yuan Chang, E. Chang, Y. Lien, Y. Miyamoto, Szu-Hung Chen, L. Chu
A 70-nm In0.52Al0.48As/In0.6Ga0.4 power MHEMT with double delta-doping was fabricated and evaluated. The device has a high transconductance of 827 mS/mni. The saturated drain-source current of the device is 890 niA/mm. A current gain cutoff frequency (fT) of 200 GHz and a maximum oscillation frequency (fmax ) of 300 GHz were achieved due to the nanometer gate length and the high Indium content in the channel. When measured at 32 GHz, the 4 times 40 mum device demonstrates a maximum output power of 14.5 dBm with PldB of 11.1 dBm and the power gain is 9.5 dB. The excellent DC and RF performance of the 70-nm MHEMT shows a great potential for Ka-band power applications.
{"title":"High-Performance In0.52Al0.48As/In0.6Ga0.4As Power Metamorphic HEMT for Ka-Band Applications","authors":"Chia-Yuan Chang, E. Chang, Y. Lien, Y. Miyamoto, Szu-Hung Chen, L. Chu","doi":"10.1109/SMELEC.2006.381095","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381095","url":null,"abstract":"A 70-nm In0.52Al0.48As/In0.6Ga0.4 power MHEMT with double delta-doping was fabricated and evaluated. The device has a high transconductance of 827 mS/mni. The saturated drain-source current of the device is 890 niA/mm. A current gain cutoff frequency (fT) of 200 GHz and a maximum oscillation frequency (fmax ) of 300 GHz were achieved due to the nanometer gate length and the high Indium content in the channel. When measured at 32 GHz, the 4 times 40 mum device demonstrates a maximum output power of 14.5 dBm with PldB of 11.1 dBm and the power gain is 9.5 dB. The excellent DC and RF performance of the 70-nm MHEMT shows a great potential for Ka-band power applications.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127752402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381012
N. A. Aziz, B. Majlis
This paper presents an approach for the process development of the out of plane silicon microneedles array fabrication. This study utilizes the wet etching technology using HNA to build a structure of sharp-tipped microneedles; biconvex-conical shaped. The height of the fabricated microneedle is 41.8 mum and the tip radii is 1.4 mum. Investigation on the effect of varying the mask opening window had been carried out. The design approach and the fabrication process are well explained here.
{"title":"Fabrication Study of Solid Microneedles Array Using HNA","authors":"N. A. Aziz, B. Majlis","doi":"10.1109/SMELEC.2006.381012","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381012","url":null,"abstract":"This paper presents an approach for the process development of the out of plane silicon microneedles array fabrication. This study utilizes the wet etching technology using HNA to build a structure of sharp-tipped microneedles; biconvex-conical shaped. The height of the fabricated microneedle is 41.8 mum and the tip radii is 1.4 mum. Investigation on the effect of varying the mask opening window had been carried out. The design approach and the fabrication process are well explained here.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129081686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381081
A.Y.K. Lim, K. Ibrahim
Abstract Silicon carbide (SiC) has received special attention in recent years because of its remarkable properties. This work presents the investigation on the growth of Si-based SiC using carbon monoxide (CO) compared to the treated carbon dioxide (CO2) as reported earlier. Experiments results has revealed the existence of Si-C bond and the bond formed on silicon (Si) surface through the characterization using X-ray diffraction (XRD) and Raman spectroscopy (RS). Thickness study is carried out show that growth using carbon monoxide has a thicker layer of SiC at the same growth condition compared to treated carbon dioxide. The reflective index (RI) of the growth SiC was measured. This growth technique is promising and shows great potential of producing relatively desirable quality SiC films for electronic devices fabrication.
{"title":"Comparison of the Growth Si-based Crystalline Silicon Carbide (SiC) by Chemical Vapor Deposition (CVD) using Carbon Monoxide (CO) and Treated Carbon Dioxide (CO2)","authors":"A.Y.K. Lim, K. Ibrahim","doi":"10.1109/SMELEC.2006.381081","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381081","url":null,"abstract":"Abstract Silicon carbide (SiC) has received special attention in recent years because of its remarkable properties. This work presents the investigation on the growth of Si-based SiC using carbon monoxide (CO) compared to the treated carbon dioxide (CO2) as reported earlier. Experiments results has revealed the existence of Si-C bond and the bond formed on silicon (Si) surface through the characterization using X-ray diffraction (XRD) and Raman spectroscopy (RS). Thickness study is carried out show that growth using carbon monoxide has a thicker layer of SiC at the same growth condition compared to treated carbon dioxide. The reflective index (RI) of the growth SiC was measured. This growth technique is promising and shows great potential of producing relatively desirable quality SiC films for electronic devices fabrication.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129293979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380712
Mahmud Benhamid, Masuri Othman
This paper proposes a novel fully parallel FFT architecture based on canonical signed digit (CSD) multiplier-less targeting wireless communication applications, such as IEEE802.15.3a wireless personal area network (WPAN) baseband. The proposed architecture has the advantages of high throughput, less latency, and smaller area. The multiplier-less architecture uses shift- and-add operations to realize the complex multiplier and uses the CSD to optimize these operations. The design has been coded in Verilog HDL targeting Xilinx Virtex-II FPGA series. It is fully implemented and tested on real hardware using Virtex-II FG456 prototype board. Based on this architecture, the implementation of 8-points FFT on Virtex-II can run at a maximum clock frequency of about 400 MHz which lead to about 3.2 GS/s throughput with a latency of 6 clock cycles using 16,580 equivalent gates. Comparison with a conventional parallel architecture design of the same size can run only at a maximum clock frequency of 220 MHz or 1.76 GS/s throughput with a latency of 12 clock cycles using 77,418 equivalent gates for the design. The resulting throughput increases by about 82% while the equivalent gates and latency decrease by about 79% and 50% respectively.
{"title":"FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Applications","authors":"Mahmud Benhamid, Masuri Othman","doi":"10.1109/SMELEC.2006.380712","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380712","url":null,"abstract":"This paper proposes a novel fully parallel FFT architecture based on canonical signed digit (CSD) multiplier-less targeting wireless communication applications, such as IEEE802.15.3a wireless personal area network (WPAN) baseband. The proposed architecture has the advantages of high throughput, less latency, and smaller area. The multiplier-less architecture uses shift- and-add operations to realize the complex multiplier and uses the CSD to optimize these operations. The design has been coded in Verilog HDL targeting Xilinx Virtex-II FPGA series. It is fully implemented and tested on real hardware using Virtex-II FG456 prototype board. Based on this architecture, the implementation of 8-points FFT on Virtex-II can run at a maximum clock frequency of about 400 MHz which lead to about 3.2 GS/s throughput with a latency of 6 clock cycles using 16,580 equivalent gates. Comparison with a conventional parallel architecture design of the same size can run only at a maximum clock frequency of 220 MHz or 1.76 GS/s throughput with a latency of 12 clock cycles using 77,418 equivalent gates for the design. The resulting throughput increases by about 82% while the equivalent gates and latency decrease by about 79% and 50% respectively.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115521594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381045
M. Al Khusheiny, B. Majlis
In this paper a new structure of clamped-clamped muresonator (CCMR) of resonance frequency (fo) of 180 kHz, is designed, modeled, fabricated and tested, using aluminum as structural material. IntelliSuite simulator is used to model the mechanical properties of the new MEMS resonator using a static displacement analysis and to get the optimum values of the beams parameters. The effective spring constant and mass of the resonator were calculated using a special proposed simulator, based on Mapple, besides using it to model the mechanical parameters into equivalent electrical circuit for the resonator, and determine the electrical properties just by giving the physical dimensions of the muresonator. Surface micromachining technology was used to fabricate the proposed MEMS resonator in IMEN's Clean Room.
{"title":"Aluminum based Two-Port-Clamped-Clamped Resonators","authors":"M. Al Khusheiny, B. Majlis","doi":"10.1109/SMELEC.2006.381045","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381045","url":null,"abstract":"In this paper a new structure of clamped-clamped muresonator (CCMR) of resonance frequency (fo) of 180 kHz, is designed, modeled, fabricated and tested, using aluminum as structural material. IntelliSuite simulator is used to model the mechanical properties of the new MEMS resonator using a static displacement analysis and to get the optimum values of the beams parameters. The effective spring constant and mass of the resonator were calculated using a special proposed simulator, based on Mapple, besides using it to model the mechanical parameters into equivalent electrical circuit for the resonator, and determine the electrical properties just by giving the physical dimensions of the muresonator. Surface micromachining technology was used to fabricate the proposed MEMS resonator in IMEN's Clean Room.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115560611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380777
Y. A. Wahab, A. Ahmad, Z. Awang
As design rules shrink beyond 0.1.3 mum the development focus has been a gradual shift in the defectivity on copper electroplating integrated circuit manufacturing applications. Effective process inspection and defect identification are key issues for the failure mechanisms in semiconductor manufacturing. In this paper, copper deposition with He in-situ and furnace anneal splits were performed on the Applied Materials SlimCellTM ECP system. The paper outlines the queue time challenges from a defectivity perspective and the solutions implemented that addresses each issue. The analytical techniques used to classify these defects and the methods used to determine their origin is discussed. This paper will attempt to describe the impact of queue time on defectivity challenges and we introduce a new defect characterization scheme that takes the defect generation mechanism and the potential source into account. Further investigation implemented to study the possibility of imposing a time window between seed deposition and plating, plating to anneal duration as well as anneal to CMP in order to posed a significant challenge in differentiating between plating and CMP induced defects. Most defects were observed after chemical-mechanical planarization (CMP) was performed and defects that were generally categorized as missing copper could have resulted from corrosion, from scratches during CMP process from incomplete filling of fine features after plating.
{"title":"Queue Time Impact on Defectivity at Post Copper Barrier Seed, Electrochemical Plating, Anneals and Chemical Mechanical Polishing","authors":"Y. A. Wahab, A. Ahmad, Z. Awang","doi":"10.1109/SMELEC.2006.380777","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380777","url":null,"abstract":"As design rules shrink beyond 0.1.3 mum the development focus has been a gradual shift in the defectivity on copper electroplating integrated circuit manufacturing applications. Effective process inspection and defect identification are key issues for the failure mechanisms in semiconductor manufacturing. In this paper, copper deposition with He in-situ and furnace anneal splits were performed on the Applied Materials SlimCellTM ECP system. The paper outlines the queue time challenges from a defectivity perspective and the solutions implemented that addresses each issue. The analytical techniques used to classify these defects and the methods used to determine their origin is discussed. This paper will attempt to describe the impact of queue time on defectivity challenges and we introduce a new defect characterization scheme that takes the defect generation mechanism and the potential source into account. Further investigation implemented to study the possibility of imposing a time window between seed deposition and plating, plating to anneal duration as well as anneal to CMP in order to posed a significant challenge in differentiating between plating and CMP induced defects. Most defects were observed after chemical-mechanical planarization (CMP) was performed and defects that were generally categorized as missing copper could have resulted from corrosion, from scratches during CMP process from incomplete filling of fine features after plating.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126747453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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