Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00043
P. M. Souare, C. Bouchard, É. Duchesne, James Zaccardi, David Pettit, Francois Vachon
A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure modes in microelectronics packaging such as module warpage, solder fatigue cracking, TIM tearing or delamination and underfill corner cracking causing chip circuits delamination and increased flip chip solder joint fatigue. The numerical simulations were performed using a specialized cloud software infrastructure named PACK using a one-way macro to micro model approach. Model validation was split into two main aspects. First, the linear behavior of the macro model was based on bottom surface metallurgy (BSM) warpage. BSM module warpage of several packages from ICOS data was used to validate the numerical model, and both room temperature warpage as well as the shape predicted by the FEM model agreed with the ICOS data. Second, the fatigue modeling accuracy was evaluated based on data issued from devices built and subjected to thermal cycles akin to the models. The non-linear simulation of creep was then performed using Norton’s creep model, using SAC material properties obtained from experimental sources. The strain energy density (SEND) was used as a metric to quantify solder creep and interconnect fatigue. The SEND was averaged over a few layers of elements at the top and bottom of the interconnects, forming a normalized volume where creep (and failure probability) was the highest. Early thermal cycles solder fatigue fails were detected electrically on the prototypes, located on the memory module’s corners. These observations were confirmed with dye and pry which corresponded with the computed SEND map and distribution given by the numerical model. Failure analysis (FA) showed that cracks initiated near the bottom side pad neck and propagating along the BGA which was also in agreement with the modeled metric’s distribution across critical BGAs. Finally, laminate BGA resin cracking fail was found under the shadow of a silicon die. Laminate BSM solder mask von Mises stress mapping was shown to be predictive of the critical locations where delamination and Cu line cracking was observed. In conclusion, the study was able to leverage available reliability stress data to calibrate the numerical model and set reference baseline while providing IBM development team guidance to narrow down the selection of best reliable lower cost package configurations for qualification decision, demonstrating the effectiveness of our modeling platform to predict module warpage despite the complexity of the package and the failure modes encountered in the design and manufacture of microelectronics packaging.
{"title":"Applied Modeling Framework in Integrated Circuit Design and Reliability","authors":"P. M. Souare, C. Bouchard, É. Duchesne, James Zaccardi, David Pettit, Francois Vachon","doi":"10.1109/ectc51906.2022.00043","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00043","url":null,"abstract":"A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure modes in microelectronics packaging such as module warpage, solder fatigue cracking, TIM tearing or delamination and underfill corner cracking causing chip circuits delamination and increased flip chip solder joint fatigue. The numerical simulations were performed using a specialized cloud software infrastructure named PACK using a one-way macro to micro model approach. Model validation was split into two main aspects. First, the linear behavior of the macro model was based on bottom surface metallurgy (BSM) warpage. BSM module warpage of several packages from ICOS data was used to validate the numerical model, and both room temperature warpage as well as the shape predicted by the FEM model agreed with the ICOS data. Second, the fatigue modeling accuracy was evaluated based on data issued from devices built and subjected to thermal cycles akin to the models. The non-linear simulation of creep was then performed using Norton’s creep model, using SAC material properties obtained from experimental sources. The strain energy density (SEND) was used as a metric to quantify solder creep and interconnect fatigue. The SEND was averaged over a few layers of elements at the top and bottom of the interconnects, forming a normalized volume where creep (and failure probability) was the highest. Early thermal cycles solder fatigue fails were detected electrically on the prototypes, located on the memory module’s corners. These observations were confirmed with dye and pry which corresponded with the computed SEND map and distribution given by the numerical model. Failure analysis (FA) showed that cracks initiated near the bottom side pad neck and propagating along the BGA which was also in agreement with the modeled metric’s distribution across critical BGAs. Finally, laminate BGA resin cracking fail was found under the shadow of a silicon die. Laminate BSM solder mask von Mises stress mapping was shown to be predictive of the critical locations where delamination and Cu line cracking was observed. In conclusion, the study was able to leverage available reliability stress data to calibrate the numerical model and set reference baseline while providing IBM development team guidance to narrow down the selection of best reliable lower cost package configurations for qualification decision, demonstrating the effectiveness of our modeling platform to predict module warpage despite the complexity of the package and the failure modes encountered in the design and manufacture of microelectronics packaging.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134410104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a Cu-Cu bonding approach utilizing Au nanoparticles (NPs) fabricated by Physical Vapor Deposition (PVD) method as intermediate to realize time-saving, low-temperature and fine-pitch bonding. Confocal microscope was used to observe the morphology of electroplated Cu bumps. Moreover, atomic force microscope (AFM) measurement was employed to detect surface morphology of electroplated Cu bumps with and without modification of Au NPs. In addition, to reveal underlying bonding mechanisms, surface topography of Au NPs was also observed by transmission electron microscope (TEM). Furthermore, shear strength tests of bonded chips were carried out after the bonding process, and fracture surfaces were investigated by scanning electron microscopy (SEM) along with energy-dispersive spectrometer (EDS) analysis. Test results illustrate that average bonding strength above 10 MPa was realized, and demonstrate that the reliable Cu-Cu bonding utilizing Au NPs as a surface modification layer was accomplished at the low temperature of 200 °C for 3 mins under the pressure of 30 MPa without annealing.
{"title":"Low Temperature Fine-pitch Cu-Cu Bonding Using Au Nanoparticles as Intermediate","authors":"Jun-Peng Fang, Jian Cai, Qian Wang, Xiuyu Shi, K. Zheng, Yikang Zhou","doi":"10.1109/ectc51906.2022.00117","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00117","url":null,"abstract":"In this paper, we propose a Cu-Cu bonding approach utilizing Au nanoparticles (NPs) fabricated by Physical Vapor Deposition (PVD) method as intermediate to realize time-saving, low-temperature and fine-pitch bonding. Confocal microscope was used to observe the morphology of electroplated Cu bumps. Moreover, atomic force microscope (AFM) measurement was employed to detect surface morphology of electroplated Cu bumps with and without modification of Au NPs. In addition, to reveal underlying bonding mechanisms, surface topography of Au NPs was also observed by transmission electron microscope (TEM). Furthermore, shear strength tests of bonded chips were carried out after the bonding process, and fracture surfaces were investigated by scanning electron microscopy (SEM) along with energy-dispersive spectrometer (EDS) analysis. Test results illustrate that average bonding strength above 10 MPa was realized, and demonstrate that the reliable Cu-Cu bonding utilizing Au NPs as a surface modification layer was accomplished at the low temperature of 200 °C for 3 mins under the pressure of 30 MPa without annealing.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130300995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00310
Guilian Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, Thomas Workman, C. Uzoh, Bongsub Lee, K.M. Bang, Gabe Guevara
The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding, is a platform technology that offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. DBI wafer to wafer (W2W) bonding has been in high volume production since 2015. Advancement in D2W hybrid bonding technology in recent years has enabled recent adoption the technology by Sony [1]. AMD [2] and Intel [3]. The DBI Ultra D2W technology offers die-on-tape processing with bonding speeds comparable to mass reflow flip chip assembly. The bonding takes place at room temperature in an ambient environment in a class 1000 cleanroom. A low temperature batch anneal following bonding creates a solid Cu-Cu connection with no solder and no underfill.The value of the DBI Ultra technology can be realized in diverse products ranging from very small die to reticle-size large die. Applications such as RF, sensors and microcontrollers are in the small die domain, while GPUs and FPGAs require bonding of very large die. Ultimate SoC disaggregation implementations may include D2W bonding of mid-large sized memory die (e.g. SRAM in V-Cache) as well as ultra-small die for analog functionalities. In this paper, we present the results of D2W bonding development in die size ranging from 0.4x0.4mm to 3.2x3.0mm. The module build process includes dicing, die preparation on tape, and direct pick & place from a tape frame. The bonding quality is characterized with C-mode scanning acoustic microscopy (CSAM) and cross-section microscopy analysis.
{"title":"Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects Evaluation-Small Die Applications","authors":"Guilian Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, Thomas Workman, C. Uzoh, Bongsub Lee, K.M. Bang, Gabe Guevara","doi":"10.1109/ectc51906.2022.00310","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00310","url":null,"abstract":"The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding, is a platform technology that offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. DBI wafer to wafer (W2W) bonding has been in high volume production since 2015. Advancement in D2W hybrid bonding technology in recent years has enabled recent adoption the technology by Sony [1]. AMD [2] and Intel [3]. The DBI Ultra D2W technology offers die-on-tape processing with bonding speeds comparable to mass reflow flip chip assembly. The bonding takes place at room temperature in an ambient environment in a class 1000 cleanroom. A low temperature batch anneal following bonding creates a solid Cu-Cu connection with no solder and no underfill.The value of the DBI Ultra technology can be realized in diverse products ranging from very small die to reticle-size large die. Applications such as RF, sensors and microcontrollers are in the small die domain, while GPUs and FPGAs require bonding of very large die. Ultimate SoC disaggregation implementations may include D2W bonding of mid-large sized memory die (e.g. SRAM in V-Cache) as well as ultra-small die for analog functionalities. In this paper, we present the results of D2W bonding development in die size ranging from 0.4x0.4mm to 3.2x3.0mm. The module build process includes dicing, die preparation on tape, and direct pick & place from a tape frame. The bonding quality is characterized with C-mode scanning acoustic microscopy (CSAM) and cross-section microscopy analysis.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115454196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00066
I-Hung Lin, Cheng-Chen Lin, Ying-Chieh Pan, B. Lwo, Tom Ni
This paper first presents the architecture of a self-designed, slot-coupled patch antenna unit in a glass-embedded fan-out antenna in package. Due to the embedded glass, design flexible and the radiation properties of the antenna structure was improved by single or double-sided patch made by redistribution layers (RDLs) on the embedded glass surfaces. The FOAiP is an extended application of fan-out technology in the advanced electronics package. It provides an ideal approach for millimeter-wave (mmWave) chip with low transmission loss of chip-to-antenna interconnect and greater design flexibilities. However, mmWave signals from a single antenna cannot be concentrated over a long distance because of its limited transmission power. Therefore, an antenna array was explored to enhance the antenna gain and the transmission distance in this study, and the full wave 3D electromagnetic (EM) simulation software (ANSYS HFSS) was employed to simulate the antenna characteristics of the FOAiP with varying structural designs and the characteristics of the array antenna with various array forms. In the slot-coupled antenna structure, the microstrip and the grounding coplanar waveguide (CPW) layer are located at RDL-1 (the feeding interconnection) and RDL-2 (beneath the glass), respectively, and the reflector layer is located on the PCB surface. As a result, a single antenna model was optimized with center frequency of 60 GHz with 5.5db gain and the bandwidth was 3.89 GHz. With the optimized antenna unit, the simulation results on antenna arrays revealed that the radiation field patterns were efficiently concentrated and the gains were increased with the array size, but the antenna bandwidths were slightly different. Furthermore, the four-by-four array antenna exhibited gain increased by 3.2 times than a single antenna. That is, the optimal characteristics of the antenna array had 59.83 GHz center frequency, 17.6 dB gain, and its bandwidth was 4.1 GHz.
{"title":"Characteristics of Glass-Embedded FOAiP with Antenna Arrays for 60GHz mmWave Applications","authors":"I-Hung Lin, Cheng-Chen Lin, Ying-Chieh Pan, B. Lwo, Tom Ni","doi":"10.1109/ectc51906.2022.00066","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00066","url":null,"abstract":"This paper first presents the architecture of a self-designed, slot-coupled patch antenna unit in a glass-embedded fan-out antenna in package. Due to the embedded glass, design flexible and the radiation properties of the antenna structure was improved by single or double-sided patch made by redistribution layers (RDLs) on the embedded glass surfaces. The FOAiP is an extended application of fan-out technology in the advanced electronics package. It provides an ideal approach for millimeter-wave (mmWave) chip with low transmission loss of chip-to-antenna interconnect and greater design flexibilities. However, mmWave signals from a single antenna cannot be concentrated over a long distance because of its limited transmission power. Therefore, an antenna array was explored to enhance the antenna gain and the transmission distance in this study, and the full wave 3D electromagnetic (EM) simulation software (ANSYS HFSS) was employed to simulate the antenna characteristics of the FOAiP with varying structural designs and the characteristics of the array antenna with various array forms. In the slot-coupled antenna structure, the microstrip and the grounding coplanar waveguide (CPW) layer are located at RDL-1 (the feeding interconnection) and RDL-2 (beneath the glass), respectively, and the reflector layer is located on the PCB surface. As a result, a single antenna model was optimized with center frequency of 60 GHz with 5.5db gain and the bandwidth was 3.89 GHz. With the optimized antenna unit, the simulation results on antenna arrays revealed that the radiation field patterns were efficiently concentrated and the gains were increased with the array size, but the antenna bandwidths were slightly different. Furthermore, the four-by-four array antenna exhibited gain increased by 3.2 times than a single antenna. That is, the optimal characteristics of the antenna array had 59.83 GHz center frequency, 17.6 dB gain, and its bandwidth was 4.1 GHz.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115194742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00009
X. Sun, J. Slabbekoorn, S. Sinha, P. Bex, N. Pinho, T. Webers, D. Velenis, A. Miller, N. Collaert, G. van der Plas, E. Beyne
We present a highly-scaled packaging and system-integration RF interposer platform on low-resistivity Si (15-25 Ωcm). The heterogenous platform has been processed and characterized by measurements in the frequency range from 10 MHz to 110 GHz, revealing an interconnect insertion loss less than 0.3 dB/mm at 100 GHz and Qmax above 40 for integrated inductors. The excellent performance of the RF Si interposer enables high frequency interconnects between the ICs and the partial matching network in the package. The narrow pitch of the μbumps further enables flip-chip performance up to 500 GHz, allowing for heterogenous integration of multiple mm-wave ICs in different technologies, together with integrated high-Q passives, as well as antennas-in-package for RF to beyond-5G applications.
{"title":"Cost-effective RF interposer platform on low-resistivity Si enabling heterogeneous integration opportunities for beyond 5G","authors":"X. Sun, J. Slabbekoorn, S. Sinha, P. Bex, N. Pinho, T. Webers, D. Velenis, A. Miller, N. Collaert, G. van der Plas, E. Beyne","doi":"10.1109/ectc51906.2022.00009","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00009","url":null,"abstract":"We present a highly-scaled packaging and system-integration RF interposer platform on low-resistivity Si (15-25 Ωcm). The heterogenous platform has been processed and characterized by measurements in the frequency range from 10 MHz to 110 GHz, revealing an interconnect insertion loss less than 0.3 dB/mm at 100 GHz and Qmax above 40 for integrated inductors. The excellent performance of the RF Si interposer enables high frequency interconnects between the ICs and the partial matching network in the package. The narrow pitch of the μbumps further enables flip-chip performance up to 500 GHz, allowing for heterogenous integration of multiple mm-wave ICs in different technologies, together with integrated high-Q passives, as well as antennas-in-package for RF to beyond-5G applications.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00055
Je-An Yu, Dongsu Kim, Insub Han, J. Yook
In this work, we propose a Ni-Zn ferrite core embedding process in a photosensitive glass substrate and demonstrate the design and fabrication of substrate embedded inductors and integrated voltage regulators (IVRs) using the substrate embedded ferrite cores. We developed a ferrite core embedding process inside a vertical cavity of a photosensitive glass substrate, so that ferrite core solenoid inductors can be embedded in the substrate. The measured inductance, DC resistance and Q-factor of a 1600μm × 1500μm ferrite core inductor were 209nH, 240mOhm, 15.8 at 18.2Mhz respectively. And a 920μm × 1050μm inductor has inductance of 252nH, DC resistance of 663mOhm, and Q-factor of 16.6 at 20Mhz. The power conversion efficiency of an integrated voltage regulator module was measured up to 85.2%.
{"title":"Demonstration of Substrate Embedded Ni-Zn Ferrite Core Solenoid Inductors Using a Photosensitive Glass Substrate","authors":"Je-An Yu, Dongsu Kim, Insub Han, J. Yook","doi":"10.1109/ectc51906.2022.00055","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00055","url":null,"abstract":"In this work, we propose a Ni-Zn ferrite core embedding process in a photosensitive glass substrate and demonstrate the design and fabrication of substrate embedded inductors and integrated voltage regulators (IVRs) using the substrate embedded ferrite cores. We developed a ferrite core embedding process inside a vertical cavity of a photosensitive glass substrate, so that ferrite core solenoid inductors can be embedded in the substrate. The measured inductance, DC resistance and Q-factor of a 1600μm × 1500μm ferrite core inductor were 209nH, 240mOhm, 15.8 at 18.2Mhz respectively. And a 920μm × 1050μm inductor has inductance of 252nH, DC resistance of 663mOhm, and Q-factor of 16.6 at 20Mhz. The power conversion efficiency of an integrated voltage regulator module was measured up to 85.2%.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114270009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00320
V. S. Bhaskar, Jong Ming Chinq, Kazunori Yamamoto, G. Tang
In this paper, electrical design and modeling of silicon carbide power modules for inverter applications are discussed. A 6-in-l silicon carbide MOSFET power module is proposed, and its package is described and analyzed. The electrical design and modeling are done using Ansys Q3D simulation to extract the parasitic inductances and capacitances. The computed power loop inductance is 6.21 nH, gate loop inductance is 1.94 nH, while the parasitic capacitance is 29.98 pF.
{"title":"Electrical Design and Modeling of Silicon Carbide Power Modules for Inverter Applications","authors":"V. S. Bhaskar, Jong Ming Chinq, Kazunori Yamamoto, G. Tang","doi":"10.1109/ectc51906.2022.00320","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00320","url":null,"abstract":"In this paper, electrical design and modeling of silicon carbide power modules for inverter applications are discussed. A 6-in-l silicon carbide MOSFET power module is proposed, and its package is described and analyzed. The electrical design and modeling are done using Ansys Q3D simulation to extract the parasitic inductances and capacitances. The computed power loop inductance is 6.21 nH, gate loop inductance is 1.94 nH, while the parasitic capacitance is 29.98 pF.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114318402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00256
F. Che, Yeow Chon Ong, H. Ng, L. Pan, Christopher D. Glancey, K. Sinha, Richard Fan
First failure (FF) fatigue life model of lead-free solder is not available from literature, especially for package used in mobile application. In this study, fatigue life model for FF prediction under temperature cycling test has been developed for low-Ag content solder joint used in board level assembly through reliability test and finite element analysis and simulation. The developed life model is validated and has a good accuracy with +/-20% error between prediction and physical testing data. Volume selection is discussed for better understanding the failure mode and site. Relationship between FF and characteristic life is also studied.
{"title":"Development on Fatigue Life Model of Lead-Free Solder for First Failure Prediction","authors":"F. Che, Yeow Chon Ong, H. Ng, L. Pan, Christopher D. Glancey, K. Sinha, Richard Fan","doi":"10.1109/ectc51906.2022.00256","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00256","url":null,"abstract":"First failure (FF) fatigue life model of lead-free solder is not available from literature, especially for package used in mobile application. In this study, fatigue life model for FF prediction under temperature cycling test has been developed for low-Ag content solder joint used in board level assembly through reliability test and finite element analysis and simulation. The developed life model is validated and has a good accuracy with +/-20% error between prediction and physical testing data. Volume selection is discussed for better understanding the failure mode and site. Relationship between FF and characteristic life is also studied.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114341980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00235
M. A. Haq, M. A. Hoque, G. R. Mazumder, J. Suhling, P. Lall
Solder joints in electronic packages often experience fatigue failures due to cyclic mechanical stresses and strains in fluctuating temperature environments. This cyclic loading of the solder is induced by mismatches in coefficients of thermal expansion and leads to damage accumulation that contributes to crack initiation, crack propagation, and eventually to failure. In our previous papers, we have investigated the accumulation of damage in several lead free solder materials (SAC305, SAC+Bi, and SAC+Bi-Ni-Sb) during mechanical cycling at room temperature (25 C) and elevated temperature (100 C). Circular cross-section solder specimens were first reflowed, and these samples were then mechanically cycled for various durations using a Micro-Mechanical tester. Monotonic stress-strain and creep tests were subsequently conducted on the prior cycled samples to characterize the change in mechanical behavior occurring in the solder due to damage accumulation. Using the data from these tests, we have been able to characterize and quantify the cycling induced damage through the observed degradations of several mechanical properties (initial elastic modulus, ultimate tensile strength, yield stress, and creep strain rate) with the amount of prior cycling. All of the mechanical cyclic testing in our prior work were performed for a single applied level of cyclic strain = +/- 0.01 (single level of damage per cycle), which corresponded to a hysteresis loop area (energy dissipated per cycle) during room temperature cycling of SAC305 of ΔW = 1.2 MJ/m3.In the current work, we have extended the experimental work in our prior studies on SAC305 to examine several levels of damage during cycling, as well as several cycling temperatures. Material behaviors of the pre-cycled solder were characterized for the various damage levels per cycle and durations of cycling. One goal of this investigation was to identify a damage parameter that can be used to predict the observed material property degradations occurring during cyclic loading of solder irrespective of the way that the damage is accumulated. The total energy dissipation occurring in the solder during cycling was found to correlate well with the evolution of mechanical properties, independent of the damage level applied during each cycle.In the experimental testing, small uniaxial cylindrical samples of SAC305 solder were prepared and reflowed in a reflow oven. These specimens were then mechanically cycled under several different sets of conditions to induce various levels of damage in the samples. In particular, four levels of initial damage per cycle were considered (ΔW = 0.25, 0.50, 0.75 and 1.00 MJ/m3), as well as three cycling temperatures (T = 25, 100, and 125 °C). For each of these damage levels per cycle, various durations of cycling were applied (e.g. 0, 50, 100, 200, 300, 600, and 1200 cycles). This test matrix generated a large set of prior damaged samples, where the damage had been accumulated at different
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Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00275
Saw Lip Teng, M. Devarajan
This work explores underfill with improved properties for rework-ability and package reliability. Reworkable underfills (Epoxy-R1 – R5) were customized by a material supplier and benchmarked with an existing non-reworkable underfill (Epoxy-E). R1 shows similar glass transition temperature (Tg), coefficient of thermal expansion 1&2 (CTE) with Epoxy-E, lower storage modulus (30% of Epoxy-E), yet still poor for rework due to major damage on printed circuit board (PCB) detected. R2 was refined with much lower modulus, 10% of Epoxy-E, but failed to meet target Tg and CTE. R3 used smaller filler size (10um) in formulation, reliability related properties were significantly improved, however, same overheat issue on adjacent component and insufficient coverage was found. For R4 and R5, both Tg reached above 130°C and low CTE-2 around 100ppm/°C, which is only 70% of Epoxy-E. For rework evaluation, R4 and R5 showed good results, no adjacent defects which are suspected due to lower adhesion, underfill is easier to remove. R5 was selected for reliability test due to its similarity in viscosity and process condition compared to Epoxy-E with minimal change in dispensing process setup. R5 test vehicle survived 1000 thermal cycling (-40°C to 85°C) meeting mechanical shock and vibration tests qualification. Lastly, it was observed that R5 achieved both rework-ability and package reliability expectations with a new defined thermo-mechanical property.
{"title":"Thermo-Mechanical Reworkable Epoxy Underfill in Board-Level Package: Material Characteristics and Reliability Criteria","authors":"Saw Lip Teng, M. Devarajan","doi":"10.1109/ectc51906.2022.00275","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00275","url":null,"abstract":"This work explores underfill with improved properties for rework-ability and package reliability. Reworkable underfills (Epoxy-R1 – R5) were customized by a material supplier and benchmarked with an existing non-reworkable underfill (Epoxy-E). R1 shows similar glass transition temperature (Tg), coefficient of thermal expansion 1&2 (CTE) with Epoxy-E, lower storage modulus (30% of Epoxy-E), yet still poor for rework due to major damage on printed circuit board (PCB) detected. R2 was refined with much lower modulus, 10% of Epoxy-E, but failed to meet target Tg and CTE. R3 used smaller filler size (10um) in formulation, reliability related properties were significantly improved, however, same overheat issue on adjacent component and insufficient coverage was found. For R4 and R5, both Tg reached above 130°C and low CTE-2 around 100ppm/°C, which is only 70% of Epoxy-E. For rework evaluation, R4 and R5 showed good results, no adjacent defects which are suspected due to lower adhesion, underfill is easier to remove. R5 was selected for reliability test due to its similarity in viscosity and process condition compared to Epoxy-E with minimal change in dispensing process setup. R5 test vehicle survived 1000 thermal cycling (-40°C to 85°C) meeting mechanical shock and vibration tests qualification. Lastly, it was observed that R5 achieved both rework-ability and package reliability expectations with a new defined thermo-mechanical property.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116876072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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