Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00107
S. Lim, S. Chong, D. Wee, T. Chai
Antenna-in-package (AiP) technology is a packaging solution where antennas are incorporated into an integrated circuit (IC) package with a RF chip [1], [2]. One of the promising technology is the Fan-out wafer level technology especially for its excellent RF performance in mobile and automotive applications [3], [4].This paper demonstrates a double FOWLP based AiP package for 77 GHz automotive radar applications with package attachment to PCB board. The ultra large package size is 32 x 16 mm2 with 0.6mm mold thickness after singulation. The lower mold layer consists of a Monolithic microwave integrated circuit (MMIC) chip and lithography process is done to reroute chip I/O pads to the mold compound top layer. The through mold vias (TMV) are interconnect vias formed through the mold compound to connect to the M3 RDL layer. The antenna excitation elements are then fabricated onto the surface of the 2nd mold EMC 2. The package is then attached to an interposer PCB and functional application board with double-side surface mount components for electrical testing and characterization. Detailed assembly process parameters on wafer reconfiguration, die placement shift compensation, compression wafer molding and debonding process to establish die placement accuracy and die protrusion of ±10um will be discussed in this work. Details of the thermocompression bonding process (TCB) for the package attachment to the PCB will also be summarized in this paper.
{"title":"Assembly challenges and demonstrations of ultra-large Antenna in Package for Automotive Radar applications","authors":"S. Lim, S. Chong, D. Wee, T. Chai","doi":"10.1109/ectc51906.2022.00107","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00107","url":null,"abstract":"Antenna-in-package (AiP) technology is a packaging solution where antennas are incorporated into an integrated circuit (IC) package with a RF chip [1], [2]. One of the promising technology is the Fan-out wafer level technology especially for its excellent RF performance in mobile and automotive applications [3], [4].This paper demonstrates a double FOWLP based AiP package for 77 GHz automotive radar applications with package attachment to PCB board. The ultra large package size is 32 x 16 mm2 with 0.6mm mold thickness after singulation. The lower mold layer consists of a Monolithic microwave integrated circuit (MMIC) chip and lithography process is done to reroute chip I/O pads to the mold compound top layer. The through mold vias (TMV) are interconnect vias formed through the mold compound to connect to the M3 RDL layer. The antenna excitation elements are then fabricated onto the surface of the 2nd mold EMC 2. The package is then attached to an interposer PCB and functional application board with double-side surface mount components for electrical testing and characterization. Detailed assembly process parameters on wafer reconfiguration, die placement shift compensation, compression wafer molding and debonding process to establish die placement accuracy and die protrusion of ±10um will be discussed in this work. Details of the thermocompression bonding process (TCB) for the package attachment to the PCB will also be summarized in this paper.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128009860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00043
P. M. Souare, C. Bouchard, É. Duchesne, James Zaccardi, David Pettit, Francois Vachon
A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure modes in microelectronics packaging such as module warpage, solder fatigue cracking, TIM tearing or delamination and underfill corner cracking causing chip circuits delamination and increased flip chip solder joint fatigue. The numerical simulations were performed using a specialized cloud software infrastructure named PACK using a one-way macro to micro model approach. Model validation was split into two main aspects. First, the linear behavior of the macro model was based on bottom surface metallurgy (BSM) warpage. BSM module warpage of several packages from ICOS data was used to validate the numerical model, and both room temperature warpage as well as the shape predicted by the FEM model agreed with the ICOS data. Second, the fatigue modeling accuracy was evaluated based on data issued from devices built and subjected to thermal cycles akin to the models. The non-linear simulation of creep was then performed using Norton’s creep model, using SAC material properties obtained from experimental sources. The strain energy density (SEND) was used as a metric to quantify solder creep and interconnect fatigue. The SEND was averaged over a few layers of elements at the top and bottom of the interconnects, forming a normalized volume where creep (and failure probability) was the highest. Early thermal cycles solder fatigue fails were detected electrically on the prototypes, located on the memory module’s corners. These observations were confirmed with dye and pry which corresponded with the computed SEND map and distribution given by the numerical model. Failure analysis (FA) showed that cracks initiated near the bottom side pad neck and propagating along the BGA which was also in agreement with the modeled metric’s distribution across critical BGAs. Finally, laminate BGA resin cracking fail was found under the shadow of a silicon die. Laminate BSM solder mask von Mises stress mapping was shown to be predictive of the critical locations where delamination and Cu line cracking was observed. In conclusion, the study was able to leverage available reliability stress data to calibrate the numerical model and set reference baseline while providing IBM development team guidance to narrow down the selection of best reliable lower cost package configurations for qualification decision, demonstrating the effectiveness of our modeling platform to predict module warpage despite the complexity of the package and the failure modes encountered in the design and manufacture of microelectronics packaging.
{"title":"Applied Modeling Framework in Integrated Circuit Design and Reliability","authors":"P. M. Souare, C. Bouchard, É. Duchesne, James Zaccardi, David Pettit, Francois Vachon","doi":"10.1109/ectc51906.2022.00043","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00043","url":null,"abstract":"A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure modes in microelectronics packaging such as module warpage, solder fatigue cracking, TIM tearing or delamination and underfill corner cracking causing chip circuits delamination and increased flip chip solder joint fatigue. The numerical simulations were performed using a specialized cloud software infrastructure named PACK using a one-way macro to micro model approach. Model validation was split into two main aspects. First, the linear behavior of the macro model was based on bottom surface metallurgy (BSM) warpage. BSM module warpage of several packages from ICOS data was used to validate the numerical model, and both room temperature warpage as well as the shape predicted by the FEM model agreed with the ICOS data. Second, the fatigue modeling accuracy was evaluated based on data issued from devices built and subjected to thermal cycles akin to the models. The non-linear simulation of creep was then performed using Norton’s creep model, using SAC material properties obtained from experimental sources. The strain energy density (SEND) was used as a metric to quantify solder creep and interconnect fatigue. The SEND was averaged over a few layers of elements at the top and bottom of the interconnects, forming a normalized volume where creep (and failure probability) was the highest. Early thermal cycles solder fatigue fails were detected electrically on the prototypes, located on the memory module’s corners. These observations were confirmed with dye and pry which corresponded with the computed SEND map and distribution given by the numerical model. Failure analysis (FA) showed that cracks initiated near the bottom side pad neck and propagating along the BGA which was also in agreement with the modeled metric’s distribution across critical BGAs. Finally, laminate BGA resin cracking fail was found under the shadow of a silicon die. Laminate BSM solder mask von Mises stress mapping was shown to be predictive of the critical locations where delamination and Cu line cracking was observed. In conclusion, the study was able to leverage available reliability stress data to calibrate the numerical model and set reference baseline while providing IBM development team guidance to narrow down the selection of best reliable lower cost package configurations for qualification decision, demonstrating the effectiveness of our modeling platform to predict module warpage despite the complexity of the package and the failure modes encountered in the design and manufacture of microelectronics packaging.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134410104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a Cu-Cu bonding approach utilizing Au nanoparticles (NPs) fabricated by Physical Vapor Deposition (PVD) method as intermediate to realize time-saving, low-temperature and fine-pitch bonding. Confocal microscope was used to observe the morphology of electroplated Cu bumps. Moreover, atomic force microscope (AFM) measurement was employed to detect surface morphology of electroplated Cu bumps with and without modification of Au NPs. In addition, to reveal underlying bonding mechanisms, surface topography of Au NPs was also observed by transmission electron microscope (TEM). Furthermore, shear strength tests of bonded chips were carried out after the bonding process, and fracture surfaces were investigated by scanning electron microscopy (SEM) along with energy-dispersive spectrometer (EDS) analysis. Test results illustrate that average bonding strength above 10 MPa was realized, and demonstrate that the reliable Cu-Cu bonding utilizing Au NPs as a surface modification layer was accomplished at the low temperature of 200 °C for 3 mins under the pressure of 30 MPa without annealing.
{"title":"Low Temperature Fine-pitch Cu-Cu Bonding Using Au Nanoparticles as Intermediate","authors":"Jun-Peng Fang, Jian Cai, Qian Wang, Xiuyu Shi, K. Zheng, Yikang Zhou","doi":"10.1109/ectc51906.2022.00117","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00117","url":null,"abstract":"In this paper, we propose a Cu-Cu bonding approach utilizing Au nanoparticles (NPs) fabricated by Physical Vapor Deposition (PVD) method as intermediate to realize time-saving, low-temperature and fine-pitch bonding. Confocal microscope was used to observe the morphology of electroplated Cu bumps. Moreover, atomic force microscope (AFM) measurement was employed to detect surface morphology of electroplated Cu bumps with and without modification of Au NPs. In addition, to reveal underlying bonding mechanisms, surface topography of Au NPs was also observed by transmission electron microscope (TEM). Furthermore, shear strength tests of bonded chips were carried out after the bonding process, and fracture surfaces were investigated by scanning electron microscopy (SEM) along with energy-dispersive spectrometer (EDS) analysis. Test results illustrate that average bonding strength above 10 MPa was realized, and demonstrate that the reliable Cu-Cu bonding utilizing Au NPs as a surface modification layer was accomplished at the low temperature of 200 °C for 3 mins under the pressure of 30 MPa without annealing.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130300995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00207
Luke Prenger, Xavier Martinez, Andrea M. Chacko, Vikram Turkani, Lauren Reimnitz, V. Akhavan, K. Schroder
Advanced packaging technology has continuously evolved over the past 10-20 years to become a major driving force in improving integrated circuit (IC) performance. This improvement in IC performance is assisted by the ability to place specialized components near each other for shorter interconnects in the IC packages. Temporary bond and debond (TB/DB) is an enabling technique for this work. TB/DB facilitates many advanced packaging methods such as 2.5D, 3D-IC, fan-out wafer-level packaging (FOWLP), and system-in-package (SiP). All these architectures require a carrier support system to allow for backside processing of device wafers, including wafer thinning. A variety of TB/DB methods exist, such as thermal slide debond, mechanical debond, chemical release, and laser debond. Each of these methods has its own advantages and disadvantages and require proper material selection particular for each method.This paper describes a recently developed debond method called photonic debond. We compare this method with existing TB/DB methods and demonstrate the feasibility of this technique to process a wide range of devices. Additionally, the photonic debond method has a fundamentally different thermal load profile on the devices, enabling novel material selection. This is modeled in this paper.Photonic debond has transitioned from a manually operated debond method to an automated debond system. The new automated debond system enables higher wafer throughput as compared to the four existing debond methods. Advancements made with new debond system enables TB/DB from variety of device wafer sizes and types. Evaluation of debonding for wafers with device topography will be presented.
{"title":"Photonic Debond: Scalability and Advancements","authors":"Luke Prenger, Xavier Martinez, Andrea M. Chacko, Vikram Turkani, Lauren Reimnitz, V. Akhavan, K. Schroder","doi":"10.1109/ectc51906.2022.00207","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00207","url":null,"abstract":"Advanced packaging technology has continuously evolved over the past 10-20 years to become a major driving force in improving integrated circuit (IC) performance. This improvement in IC performance is assisted by the ability to place specialized components near each other for shorter interconnects in the IC packages. Temporary bond and debond (TB/DB) is an enabling technique for this work. TB/DB facilitates many advanced packaging methods such as 2.5D, 3D-IC, fan-out wafer-level packaging (FOWLP), and system-in-package (SiP). All these architectures require a carrier support system to allow for backside processing of device wafers, including wafer thinning. A variety of TB/DB methods exist, such as thermal slide debond, mechanical debond, chemical release, and laser debond. Each of these methods has its own advantages and disadvantages and require proper material selection particular for each method.This paper describes a recently developed debond method called photonic debond. We compare this method with existing TB/DB methods and demonstrate the feasibility of this technique to process a wide range of devices. Additionally, the photonic debond method has a fundamentally different thermal load profile on the devices, enabling novel material selection. This is modeled in this paper.Photonic debond has transitioned from a manually operated debond method to an automated debond system. The new automated debond system enables higher wafer throughput as compared to the four existing debond methods. Advancements made with new debond system enables TB/DB from variety of device wafer sizes and types. Evaluation of debonding for wafers with device topography will be presented.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115857704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00355
Chengjie Xi, Nathan Jessurun, John True, Aslam A. Khan, M. Tehranipoor, N. Asadizanjani
Nowadays, counterfeit integrated circuits (IC) are increasingly common due to the continuous growth of supply chain globalization. This supply chain vulnerability results in unreliable and insecure counterfeit ICs integrated into the end-user devices in many applications, including consumer, corporate, and military domains. Various methods such as aging detection sensors, Physical Unclonable Functions (PUFs), and hardware metering have been developed to detect such counterfeits before they become integrated into critical systems. However, several complicated aspects of detection and prevention limit their use as a stopgap to the counterfeit problem. Hence, there is a critical need for novel inspection and assurance techniques that require minimal or no additional changes/modifications to the device circuit or material while remaining low-cost per sample. In this paper, the possibility of using IC packaging material characterization for counterfeit detection is proved by a preliminary material survey between the counterfeit and authentic ICs. Diffuse Reflectance Infrared Fourier Transform Spectroscopy (DRIFT) is used as the material characterization in this research, and the material spectrums will be utilized for training machine learning classification models. Several machine learning classification methods will be tested, such as Linear discriminant analysis (LDA), Support Vector Machine (SVM), random forest(RF), and multi-layer perceptron (MLP). With the help of the Standard Normal Variate (SNV) data preprocessing and MPL model, over 92 percent accuracy of counterfeit versus genuine sample discrimination has been achieved. This proves the existence of packaging material differences between counterfeit and authentic IC samples.
{"title":"Machine Learning Assisted Counterfeit IC Detection through Non-destructive Infrared (IR) Spectroscopy Material Characterization","authors":"Chengjie Xi, Nathan Jessurun, John True, Aslam A. Khan, M. Tehranipoor, N. Asadizanjani","doi":"10.1109/ectc51906.2022.00355","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00355","url":null,"abstract":"Nowadays, counterfeit integrated circuits (IC) are increasingly common due to the continuous growth of supply chain globalization. This supply chain vulnerability results in unreliable and insecure counterfeit ICs integrated into the end-user devices in many applications, including consumer, corporate, and military domains. Various methods such as aging detection sensors, Physical Unclonable Functions (PUFs), and hardware metering have been developed to detect such counterfeits before they become integrated into critical systems. However, several complicated aspects of detection and prevention limit their use as a stopgap to the counterfeit problem. Hence, there is a critical need for novel inspection and assurance techniques that require minimal or no additional changes/modifications to the device circuit or material while remaining low-cost per sample. In this paper, the possibility of using IC packaging material characterization for counterfeit detection is proved by a preliminary material survey between the counterfeit and authentic ICs. Diffuse Reflectance Infrared Fourier Transform Spectroscopy (DRIFT) is used as the material characterization in this research, and the material spectrums will be utilized for training machine learning classification models. Several machine learning classification methods will be tested, such as Linear discriminant analysis (LDA), Support Vector Machine (SVM), random forest(RF), and multi-layer perceptron (MLP). With the help of the Standard Normal Variate (SNV) data preprocessing and MPL model, over 92 percent accuracy of counterfeit versus genuine sample discrimination has been achieved. This proves the existence of packaging material differences between counterfeit and authentic IC samples.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132322210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00293
Goeun Kim, Doohee Lim, Tamal Das, Eunjung Lee, S. You
This paper presents a system-level co-optimization approach with Chip Power Model based power integrity simulation of the power delivery network and jitter sensitivity transfer function (JTF). Due to the need to merge multiple power domains and to locate adjacent power domains close to each other for enhancing cost effectiveness and space efficiency, the coupling resonance severely affects the whole system. To meet the rigorous performance requirements, a system-level co-design is mandatory. An approach which analyzes the V-by-One IP circuit blocks and finds the critical path based on the JTF is suggested within the case studies. An on-chip level optimization to bring higher voltage controlled oscillator output frequency and to add sufficient On-die-cap was analyzed. In the off-chip design stage, various design modifications to split the power domain, reinforce the ground path, and add package decoupling capacitors were attempted to decrease total jitter by the JTF. Finally, a co-optimization design process workflow which controls the total jitter budgeting is presented. The total jitter is decreased by 68.49% compared to the worst design case.
本文提出了一种基于芯片功率模型的输电网络功率完整性仿真和抖动灵敏度传递函数(JTF)的系统级协同优化方法。由于需要合并多个功率域，并且为了提高成本效益和空间效率，需要对相邻功率域进行较近的定位，因此耦合共振严重影响了整个系统。为了满足严格的性能需求，系统级协同设计是必需的。在案例研究中，提出了一种基于JTF分析v by one IP电路块并找到关键路径的方法。分析了一种片上级优化方法，以提高压控振荡器的输出频率，并增加足够的片上电容。在片外设计阶段，为了减少JTF的总抖动，尝试了各种设计修改，以分割功率域、加强接地路径和添加封装去耦电容器。最后，提出了一种控制总抖动预算的协同优化设计流程。与最坏设计情况相比，总抖动减小了68.49%。
{"title":"System Level Power Supply Induced Jitter Suppression for multi-lane high speed serial links","authors":"Goeun Kim, Doohee Lim, Tamal Das, Eunjung Lee, S. You","doi":"10.1109/ectc51906.2022.00293","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00293","url":null,"abstract":"This paper presents a system-level co-optimization approach with Chip Power Model based power integrity simulation of the power delivery network and jitter sensitivity transfer function (JTF). Due to the need to merge multiple power domains and to locate adjacent power domains close to each other for enhancing cost effectiveness and space efficiency, the coupling resonance severely affects the whole system. To meet the rigorous performance requirements, a system-level co-design is mandatory. An approach which analyzes the V-by-One IP circuit blocks and finds the critical path based on the JTF is suggested within the case studies. An on-chip level optimization to bring higher voltage controlled oscillator output frequency and to add sufficient On-die-cap was analyzed. In the off-chip design stage, various design modifications to split the power domain, reinforce the ground path, and add package decoupling capacitors were attempted to decrease total jitter by the JTF. Finally, a co-optimization design process workflow which controls the total jitter budgeting is presented. The total jitter is decreased by 68.49% compared to the worst design case.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"79 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132330703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00032
P. Zhao, Hong Yu Li, Yu Dian Lim, W. Seit, L. Guidoni, C. S. Tan
In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of the TSV. CMOS back-end-of-line process on 12-inch wafer platform is used for the trap fabrication. Upon the integration of grounding plane, the on-chip insertion loss is reduced to 0.06 dB (at RF frequency of 50 MHz). Based on the finite element modelling results, for trap with additional grounding plane, the Joule heating-induced temperature rise is reduced from >15 K to 2 K. This work demonstrates the compatibility of grounding plane and TSV in the application of scalable ion trap, enriching the integration toolbox for large scale ion trapping devices.
{"title":"The Integration of Grounding Plane into TSV Integrated Ion Trap for Efficient Thermal Management in Large Scale Quantum Computing Device","authors":"P. Zhao, Hong Yu Li, Yu Dian Lim, W. Seit, L. Guidoni, C. S. Tan","doi":"10.1109/ectc51906.2022.00032","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00032","url":null,"abstract":"In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of the TSV. CMOS back-end-of-line process on 12-inch wafer platform is used for the trap fabrication. Upon the integration of grounding plane, the on-chip insertion loss is reduced to 0.06 dB (at RF frequency of 50 MHz). Based on the finite element modelling results, for trap with additional grounding plane, the Joule heating-induced temperature rise is reduced from >15 K to 2 K. This work demonstrates the compatibility of grounding plane and TSV in the application of scalable ion trap, enriching the integration toolbox for large scale ion trapping devices.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"16 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132934478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00194
K. Pan, C. Okoro, Yangyang Lai, Dhananjay Joshi, Seungbae Park, S. Pollard
This study investigates the thermomechanical response of the copper TGV during thermal cycling. Two different geometries of copper TGV, the fully-filled TGV and conformal TGV, are compared concerning their in-plane and out-of-plane deformation. The TGV samples were heated from room temperature (RT) 23 °C to 400 °C and then cooled to RT. The protrusion height of the copper TGV was recorded as a function of temperature, and unrecoverable copper protrusions were observed because of the creep of the copper at high temperatures. Two-dimensional digital image correlation (2D DIC) measurements were employed to obtain the in-plane deformation of the glass substrate near the copper TGV. It was found the copper protrusion height and the in-plane deformation of the glass substrate were significantly reduced in the conformal TGVs compared to the fully-filled TGVs.
{"title":"A comparative study of the thermomechanical reliability of fully-filled and conformal through-glass via","authors":"K. Pan, C. Okoro, Yangyang Lai, Dhananjay Joshi, Seungbae Park, S. Pollard","doi":"10.1109/ectc51906.2022.00194","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00194","url":null,"abstract":"This study investigates the thermomechanical response of the copper TGV during thermal cycling. Two different geometries of copper TGV, the fully-filled TGV and conformal TGV, are compared concerning their in-plane and out-of-plane deformation. The TGV samples were heated from room temperature (RT) 23 °C to 400 °C and then cooled to RT. The protrusion height of the copper TGV was recorded as a function of temperature, and unrecoverable copper protrusions were observed because of the creep of the copper at high temperatures. Two-dimensional digital image correlation (2D DIC) measurements were employed to obtain the in-plane deformation of the glass substrate near the copper TGV. It was found the copper protrusion height and the in-plane deformation of the glass substrate were significantly reduced in the conformal TGVs compared to the fully-filled TGVs.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00074
Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya
Due to the increase in the amount of data handled and evolving data center architectures, there is a growing demand to use high-performance optical transceivers within and between the data centers. We propose a new heterogeneous packaging platform for optical transceivers that can handle higher data rates addressing cost, performance, and form-factor requirements. In this paper, the proof of concept is demonstrated by developing a passive optical engine package with a size of 11mmx11mm integrating electronic and photonic chips. To realize this, a fan-out wafer-level packaging method is employed that can provide high-speed electrical interconnects and integrated photonic chip with suspended optical couplers. By employing this platform, discrete chiplets can be optimized independently and integrated into small-form-factor packages that are otherwise not possible with monolithic integration and provide a clear differentiation compared to other approaches currently in the industry.
{"title":"A Novel Packaging Platform for High-Performance Optical Engines in Hyperscale Data Center Applications","authors":"Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya","doi":"10.1109/ectc51906.2022.00074","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00074","url":null,"abstract":"Due to the increase in the amount of data handled and evolving data center architectures, there is a growing demand to use high-performance optical transceivers within and between the data centers. We propose a new heterogeneous packaging platform for optical transceivers that can handle higher data rates addressing cost, performance, and form-factor requirements. In this paper, the proof of concept is demonstrated by developing a passive optical engine package with a size of 11mmx11mm integrating electronic and photonic chips. To realize this, a fan-out wafer-level packaging method is employed that can provide high-speed electrical interconnects and integrated photonic chip with suspended optical couplers. By employing this platform, discrete chiplets can be optimized independently and integrated into small-form-factor packages that are otherwise not possible with monolithic integration and provide a clear differentiation compared to other approaches currently in the industry.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"933 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116632129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00206
Zhijian Sun, Michael Yu, Jiaxiong Li, Macleary Moran, M. Kathaperumal, K. Moon, Madhavan Swaminathan, C. Wong
Recent advances in two-dimensional (2D) nanomaterials have generated great interest in the investigations of these materials for wide ranging applications in the micro-to nano-scale electronics, healthcare, and energy storage areas. In particular, 2D materialas such as boron nitride nanosheets (BNNS) have been studied extensively due to their unique material properties that include a large specific surface area, high thermal conductivity (~750 W/mK), and wide bandgap (~5.5 eV), along with the associated electrical insulation. In this paper, we prepared BNNS by liquid exfoliation of hexagonal boron nitride (h-BN). Liquid exfoliation is an enhanced method to achieve large-scale and low-cost production, which is more suitable for large volume applications. In this paper, we have combined low-energy ball milling and sonication methods to produce BNNS on a large scale.BNNS have a high in-plane thermal conductivity due to their 2D morphology but a lower through-plane thermal conductivity. Also, the thermal interface resistance between BNNS is also an important factor that impedes the through-plane thermal conductivity. Thus, we employed a vacuum filtration method to obtain thick BNNS cakes. These cakes have a high x-y/in-plane thermal conductivity and a low z/through plane thermal conductivity. After slicing the cake vertically, it is rolled over to covert the strong x-y plane thermal conductivity to the z-plane. The now high thermal conductivity z-plane allows for effective 3D electronic packaging. Following this, BNNS are infiltrated into epoxy resins to fabricate epoxy nanocomposites with a low filler loading. This paper presents detailed studies on the coefficient of thermal expansion (CTE), electrical resistivity, thermal stability, and thermomechanical properties of the synthesized BNNS-epoxy nanocomposites. This study reveals the promising applications of high performance, thermally conductive epoxy nanocomposites in advanced packaging technologies such as 2.5D/ 3D packaging.
{"title":"Large-scale production of boron nitride nanosheets-based epoxy nanocomposites with ultrahigh through-plane thermal conductivity for electronic encapsulation","authors":"Zhijian Sun, Michael Yu, Jiaxiong Li, Macleary Moran, M. Kathaperumal, K. Moon, Madhavan Swaminathan, C. Wong","doi":"10.1109/ectc51906.2022.00206","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00206","url":null,"abstract":"Recent advances in two-dimensional (2D) nanomaterials have generated great interest in the investigations of these materials for wide ranging applications in the micro-to nano-scale electronics, healthcare, and energy storage areas. In particular, 2D materialas such as boron nitride nanosheets (BNNS) have been studied extensively due to their unique material properties that include a large specific surface area, high thermal conductivity (~750 W/mK), and wide bandgap (~5.5 eV), along with the associated electrical insulation. In this paper, we prepared BNNS by liquid exfoliation of hexagonal boron nitride (h-BN). Liquid exfoliation is an enhanced method to achieve large-scale and low-cost production, which is more suitable for large volume applications. In this paper, we have combined low-energy ball milling and sonication methods to produce BNNS on a large scale.BNNS have a high in-plane thermal conductivity due to their 2D morphology but a lower through-plane thermal conductivity. Also, the thermal interface resistance between BNNS is also an important factor that impedes the through-plane thermal conductivity. Thus, we employed a vacuum filtration method to obtain thick BNNS cakes. These cakes have a high x-y/in-plane thermal conductivity and a low z/through plane thermal conductivity. After slicing the cake vertically, it is rolled over to covert the strong x-y plane thermal conductivity to the z-plane. The now high thermal conductivity z-plane allows for effective 3D electronic packaging. Following this, BNNS are infiltrated into epoxy resins to fabricate epoxy nanocomposites with a low filler loading. This paper presents detailed studies on the coefficient of thermal expansion (CTE), electrical resistivity, thermal stability, and thermomechanical properties of the synthesized BNNS-epoxy nanocomposites. This study reveals the promising applications of high performance, thermally conductive epoxy nanocomposites in advanced packaging technologies such as 2.5D/ 3D packaging.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115391570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：