Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00090
Yu Liang, Chia-Peng Sun, Chih Chung Hsu, D. Hu, E. Chen, J. Lee
A novel methodology of 3D CAE modeling of capillary underfill of multi-chip packages with a large number of micro bumps is employed in this study. The capillary underfill flow is mainly driven by the surface-tension force based on the contact angle between bumps and substrate. On the other hand, the propagation of the melt front is mainly dominated by the dispensing design of underfill and the distribution of micro bumps. For the simulation of dispensing behavior, 3D modeling is unavoidable. However, the computing cost will become unaffordable due to the number of bumps. To ease the computing cost, an equivalent technique -The Equivalent Bump Group (EBG) model is proposed to the simulation. A simple package is studied to validate the proposed methodology. The case shows that the modeling solution of melt front by EBG model has a good agreement to the detailed model by according dispensing passes. Therefore, it is convinced that the proposed methodology provides a promising simulation solution for the microchip encapsulation for multi-chip packages with large number of micro bumps. A study for a multi-array package of different dispensing designs by EBG model is also conducted. The result shows that filling time can be predicted to get the best dispensing design with minimum filling time.
{"title":"A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications","authors":"Yu Liang, Chia-Peng Sun, Chih Chung Hsu, D. Hu, E. Chen, J. Lee","doi":"10.1109/ectc51906.2022.00090","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00090","url":null,"abstract":"A novel methodology of 3D CAE modeling of capillary underfill of multi-chip packages with a large number of micro bumps is employed in this study. The capillary underfill flow is mainly driven by the surface-tension force based on the contact angle between bumps and substrate. On the other hand, the propagation of the melt front is mainly dominated by the dispensing design of underfill and the distribution of micro bumps. For the simulation of dispensing behavior, 3D modeling is unavoidable. However, the computing cost will become unaffordable due to the number of bumps. To ease the computing cost, an equivalent technique -The Equivalent Bump Group (EBG) model is proposed to the simulation. A simple package is studied to validate the proposed methodology. The case shows that the modeling solution of melt front by EBG model has a good agreement to the detailed model by according dispensing passes. Therefore, it is convinced that the proposed methodology provides a promising simulation solution for the microchip encapsulation for multi-chip packages with large number of micro bumps. A study for a multi-array package of different dispensing designs by EBG model is also conducted. The result shows that filling time can be predicted to get the best dispensing design with minimum filling time.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129362114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00154
Yu-Tao Yang, Haoxiang Ren, S. Chong, Gang Qiu, Shu-Yun Ku, Yang Cheng, Chaowei Hu, Tiema Qian, Kuan-Neng Chen, Ni Ni, Kang L. Wang, S. Iyer
To preserve delicate quantum signals (few hundreds to a few tens of µV), low-loss and low-crosstalk inter-dielet communication is a must in a wafer-scale integrated quantum system using Superconducting-IF. In this paper, inter-dielet links (short: 125 μm and 500 μm; long: 1750 μm) with L/S (2/2 and 5/5 μm) are characterized in a broadband 20 GHz range through simulation and experiments at 4K A compact assembly (inter-dielet spacing of 100 μm) through the quantum-compatible fine-pitch (10 um) Au interlayer is conducted. For insertion loss and crosstalk characterization, the simulated and measured results are presented to be low-loss (<1 dB) and low-crosstalk (< -23 dB) in the broadband 20 GHz range with short (≤ 500 um) and long (1750 um) links and two L/S (2/2 and 5/5 um). It is one of the first 20 GHz broadband RF characterization of short superconducting links (≤ 500 um) through advanced packaging for cryogenic inter-dielet quantum communication. This work brings large-scale quantum computing closer to being realized through compact heterogeneous integration.
{"title":"RF Characterization on Nb-based Superconducting Silicon Interconnect Fabric for Future Large Scale Quantum Applications","authors":"Yu-Tao Yang, Haoxiang Ren, S. Chong, Gang Qiu, Shu-Yun Ku, Yang Cheng, Chaowei Hu, Tiema Qian, Kuan-Neng Chen, Ni Ni, Kang L. Wang, S. Iyer","doi":"10.1109/ectc51906.2022.00154","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00154","url":null,"abstract":"To preserve delicate quantum signals (few hundreds to a few tens of µV), low-loss and low-crosstalk inter-dielet communication is a must in a wafer-scale integrated quantum system using Superconducting-IF. In this paper, inter-dielet links (short: 125 μm and 500 μm; long: 1750 μm) with L/S (2/2 and 5/5 μm) are characterized in a broadband 20 GHz range through simulation and experiments at 4K A compact assembly (inter-dielet spacing of 100 μm) through the quantum-compatible fine-pitch (10 um) Au interlayer is conducted. For insertion loss and crosstalk characterization, the simulated and measured results are presented to be low-loss (<1 dB) and low-crosstalk (< -23 dB) in the broadband 20 GHz range with short (≤ 500 um) and long (1750 um) links and two L/S (2/2 and 5/5 um). It is one of the first 20 GHz broadband RF characterization of short superconducting links (≤ 500 um) through advanced packaging for cryogenic inter-dielet quantum communication. This work brings large-scale quantum computing closer to being realized through compact heterogeneous integration.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00143
L. Dietrich, H. Oppermann, C. Lopper, P. Mackowiak
A novel bumping and bonding technology using sponge-like gold depots with nanometer-scale skeleton construction has been developed and verified. The nanoporous gold (NPG) is formed up by selective etching the silver content from silver/gold alloys, which have been previously electrodeposited on lithographically patterned wafers. Due to the high resolution of the used photoresist systems, highest I/O densities and smallest bump sizes down to 1 μm are achieved. The desired alloy composition is adjustable in a wide range by adequate choice of the metal ion concentration in the electrolyte and by adaption of the deposition rate. The final porosity of the gold can be adjusted by sufficient choice of the etching conditions, and a final coarsening of the NPG texture can be achieved by thermal treatment prior to the bonding process. Thermal as well as mechanical tests were performed to get statements about the characteristics of the skeleton substructure and the reliability of the NPG interconnection. Exemplarily, some thermocompression (TC) bonding results are presented with focus on the NPG interconnect formation.
{"title":"Fabrication and Characterization of Nanoporous Gold (NPG) Interconnects for Wafer Level Packaging","authors":"L. Dietrich, H. Oppermann, C. Lopper, P. Mackowiak","doi":"10.1109/ectc51906.2022.00143","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00143","url":null,"abstract":"A novel bumping and bonding technology using sponge-like gold depots with nanometer-scale skeleton construction has been developed and verified. The nanoporous gold (NPG) is formed up by selective etching the silver content from silver/gold alloys, which have been previously electrodeposited on lithographically patterned wafers. Due to the high resolution of the used photoresist systems, highest I/O densities and smallest bump sizes down to 1 μm are achieved. The desired alloy composition is adjustable in a wide range by adequate choice of the metal ion concentration in the electrolyte and by adaption of the deposition rate. The final porosity of the gold can be adjusted by sufficient choice of the etching conditions, and a final coarsening of the NPG texture can be achieved by thermal treatment prior to the bonding process. Thermal as well as mechanical tests were performed to get statements about the characteristics of the skeleton substructure and the reliability of the NPG interconnection. Exemplarily, some thermocompression (TC) bonding results are presented with focus on the NPG interconnect formation.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130044461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00345
Jotham Kasule, Shokat Ganjeheizadeh Rohani, M. Pothier, Yuri Piro, A. Akyurtlu, C. Armiento
This paper describes the development of a printed, planar microwave connector operating from 1-7 GHz. The connector, which is based on a Grounded Coplanar Waveguide (GCPW) transmission line structure, is fabricated using 3D-printed thermoplastic material (PEEK) and conductive nanoparticle silver ink. Electromagnetic models were established to provide guidance on design tradeoffs and their impact on microwave performance. New mechanical designs were also developed to provide accurate alignment and robust connection of the two halves of the planar connector structure. Initial connector prototypes were fabricated to validate the new planar design using conventional double-sided copper laminates (Isola MT40). The designs were then implemented in an all-printed version of the connector. Electromagnetic models of the printed connectors were developed using the measured dielectric properties of printed PEEK. The insertion loss of the printed connectors was measured to be less than 1.7dB across the band.
{"title":"Printed Microwave Connector","authors":"Jotham Kasule, Shokat Ganjeheizadeh Rohani, M. Pothier, Yuri Piro, A. Akyurtlu, C. Armiento","doi":"10.1109/ectc51906.2022.00345","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00345","url":null,"abstract":"This paper describes the development of a printed, planar microwave connector operating from 1-7 GHz. The connector, which is based on a Grounded Coplanar Waveguide (GCPW) transmission line structure, is fabricated using 3D-printed thermoplastic material (PEEK) and conductive nanoparticle silver ink. Electromagnetic models were established to provide guidance on design tradeoffs and their impact on microwave performance. New mechanical designs were also developed to provide accurate alignment and robust connection of the two halves of the planar connector structure. Initial connector prototypes were fabricated to validate the new planar design using conventional double-sided copper laminates (Isola MT40). The designs were then implemented in an all-printed version of the connector. Electromagnetic models of the printed connectors were developed using the measured dielectric properties of printed PEEK. The insertion loss of the printed connectors was measured to be less than 1.7dB across the band.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116291546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00239
T. Uhrmann, B. Povazay, T. Zenger, Bemd Thallner, R. Holly, Bozena Matuskova Lednicka, Mario Reybrouck, Niels Van Herck, Bart Persijn, D. Janssen, S. Vanclooster, Stef Heirbaut
The updated roadmap for advanced packaging shows an increased need for denser next-generation heterogeneous integration designs. With the goal of further reducing the currently achieved via diameters in critical dielectric layers tailored for FOWLP, we evaluated high performing polyimide (PI) and polybenzoxazole (PBO) materials using a maskless exposure lithography system that enables instant design changes.
{"title":"Optimization of PI & PBO Layers Lithography Process for High Density Fan-Out Wafer Level Packaging & Next Generation Heterogeneous Integration Applications Employing Digitally Driven Maskless Lithography","authors":"T. Uhrmann, B. Povazay, T. Zenger, Bemd Thallner, R. Holly, Bozena Matuskova Lednicka, Mario Reybrouck, Niels Van Herck, Bart Persijn, D. Janssen, S. Vanclooster, Stef Heirbaut","doi":"10.1109/ectc51906.2022.00239","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00239","url":null,"abstract":"The updated roadmap for advanced packaging shows an increased need for denser next-generation heterogeneous integration designs. With the goal of further reducing the currently achieved via diameters in critical dielectric layers tailored for FOWLP, we evaluated high performing polyimide (PI) and polybenzoxazole (PBO) materials using a maskless exposure lithography system that enables instant design changes.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126947858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00180
Siddharth Ravichandran, V. Smet, Madhavan Swaminathan, R. Tummala
This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.
{"title":"Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing","authors":"Siddharth Ravichandran, V. Smet, Madhavan Swaminathan, R. Tummala","doi":"10.1109/ectc51906.2022.00180","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00180","url":null,"abstract":"This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127118997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00158
B. Kumari, Rohit Sharma, Manodipan Sahoo
Copper Carbon (Cu-Carbon) hybrid interconnect is a new and an extremely promising candidate for future VLSI circuit applications, so it needs to be analyzed for not only propagation delay but its stability should also be examined in order to consolidate its claim as an alternative to existing interconnect configurations. In this work, stability analysis of the recently proposed Cu-Carbon hybrid interconnect is performed and compared with existing alternate hybrid interconnect candidates (i.e. copper, copper-graphene hybrid and copper-carbon nanotube composite). A three-line coupled interconnect system for 7 nm technology node is considered in this study whose dimensional parameters are adopted as per the IRDS roadmap guidelines. The unit-step response of Cu-Carbon hybrid interconnect is steepest as compared to others because of its lowest switching delay. Cu-Carbon hybrid appears to be the most stable as its nyquist plot intersects farthest from the critical point (-1, j0) towards origin. The effect of crosstalk leads to undershoots as seen in the time domain response of copper interconnects, but it does not have any notable effect on Cu-Carbon hybrid interconnects. It is evident that as the fraction of carbon nanotube in Cu-Carbon hybrid (Fcnt) increases, bandwidth increases due to decrease in resistance. Also, Cu-Carbon with Fcnt = 0.8 is most stable amongst all configurations. We conclude that Cu-Carbon hybrid is the most stable candidate among all the alternative interconnect configurations, claiming it to be a desirable interconnect alternative for near-future VLSI applications.
{"title":"Stability Analysis of Nanoscale Copper-Carbon Hybrid Interconnects","authors":"B. Kumari, Rohit Sharma, Manodipan Sahoo","doi":"10.1109/ectc51906.2022.00158","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00158","url":null,"abstract":"Copper Carbon (Cu-Carbon) hybrid interconnect is a new and an extremely promising candidate for future VLSI circuit applications, so it needs to be analyzed for not only propagation delay but its stability should also be examined in order to consolidate its claim as an alternative to existing interconnect configurations. In this work, stability analysis of the recently proposed Cu-Carbon hybrid interconnect is performed and compared with existing alternate hybrid interconnect candidates (i.e. copper, copper-graphene hybrid and copper-carbon nanotube composite). A three-line coupled interconnect system for 7 nm technology node is considered in this study whose dimensional parameters are adopted as per the IRDS roadmap guidelines. The unit-step response of Cu-Carbon hybrid interconnect is steepest as compared to others because of its lowest switching delay. Cu-Carbon hybrid appears to be the most stable as its nyquist plot intersects farthest from the critical point (-1, j0) towards origin. The effect of crosstalk leads to undershoots as seen in the time domain response of copper interconnects, but it does not have any notable effect on Cu-Carbon hybrid interconnects. It is evident that as the fraction of carbon nanotube in Cu-Carbon hybrid (Fcnt) increases, bandwidth increases due to decrease in resistance. Also, Cu-Carbon with Fcnt = 0.8 is most stable amongst all configurations. We conclude that Cu-Carbon hybrid is the most stable candidate among all the alternative interconnect configurations, claiming it to be a desirable interconnect alternative for near-future VLSI applications.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125916534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00289
Jinfeng Li
A new 0-360° continuously-variable true-time-delay phase shifter (delay line) based on liquid crystal (LC) is prototyped targeting 60 GHz inter-satellite cross-links. The device is developed on a stray-modes-free conductor-backed fully-enclosed coplanar waveguide (CB-ECPW). The novelty is underpinned by an electric field homogenisation concept, as well as insertion losses balancing at various phase-delay states by smart impedance-matching to remove beam-steering distortions without using amplitude compensation networks. The manufacturing features nickel-free gold-plating and vias plated shut. Measured worst-case insertion loss being -7.04 dB (0-360° phase-shifting) and phase-tuning rise time being 0.6 seconds at 60 GHz, the device demonstrates an improvement of up to 1 dB for the forward transmission coefficient, as well as a reduction of 3.4 seconds for the response time compared against our previously optimised LC-based ECPW phase shifter. These enable the new device to compete with existing waveguide-based LC analog delay lines in terms of various figure-of-merits and agility.
{"title":"60 GHz 0-360˚ Passive Analog Delay Line in Liquid Crystal Technology based on a Novel Conductor-backed Fully-enclosed Coplanar Waveguide","authors":"Jinfeng Li","doi":"10.1109/ectc51906.2022.00289","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00289","url":null,"abstract":"A new 0-360° continuously-variable true-time-delay phase shifter (delay line) based on liquid crystal (LC) is prototyped targeting 60 GHz inter-satellite cross-links. The device is developed on a stray-modes-free conductor-backed fully-enclosed coplanar waveguide (CB-ECPW). The novelty is underpinned by an electric field homogenisation concept, as well as insertion losses balancing at various phase-delay states by smart impedance-matching to remove beam-steering distortions without using amplitude compensation networks. The manufacturing features nickel-free gold-plating and vias plated shut. Measured worst-case insertion loss being -7.04 dB (0-360° phase-shifting) and phase-tuning rise time being 0.6 seconds at 60 GHz, the device demonstrates an improvement of up to 1 dB for the forward transmission coefficient, as well as a reduction of 3.4 seconds for the response time compared against our previously optimised LC-based ECPW phase shifter. These enable the new device to compete with existing waveguide-based LC analog delay lines in terms of various figure-of-merits and agility.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125480930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00132
Cong Gan, Hai-Jun Huang, Bin Hou, Min-bo Zhou, Xin-Ping Zhang
In this work, bimodal Cu particles have been synthesized by using 2-amino-2-methyl-1-propanol (AMP)-based hybrid capping agent for the first time. A novel hybrid Cu ink is prepared by combining bimodal Cu particles with solvents and Cu-based metal-organic decomposition (MOD) ink composed of Cu(II) formate, AMP and octylamine. The printed Cu patterns (films) by using the hybrid Cu ink show resistivity as low as 60 μΩ•cm after sintering under mid processing conditions (e.g., sintering at 110°C for 20 min in nitrogen atmosphere). The results also show that sintered Cu films of the hybrid Cu ink have good adhesion property on glass, polyimide (PI) and polyethylene terephthalate (PET) substrates, and the flexible Cu circuits on flattening and bending PI or PET substrates play the function well, in terms of easily lighting LEDs (light emitting diodes) in the circuits. Finally, the wearable strain sensor fabricated by using the hybrid Cu ink can also be well used to monitor the movement of human finger. All these results show that the hybrid Cu ink has high potential for application in printed flexible electronics.
{"title":"Fabrication of wearable strain sensor by using a novel hybrid Cu ink composed of bimodal Cu particle ink and Cu-based metal-organic decomposition ink","authors":"Cong Gan, Hai-Jun Huang, Bin Hou, Min-bo Zhou, Xin-Ping Zhang","doi":"10.1109/ectc51906.2022.00132","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00132","url":null,"abstract":"In this work, bimodal Cu particles have been synthesized by using 2-amino-2-methyl-1-propanol (AMP)-based hybrid capping agent for the first time. A novel hybrid Cu ink is prepared by combining bimodal Cu particles with solvents and Cu-based metal-organic decomposition (MOD) ink composed of Cu(II) formate, AMP and octylamine. The printed Cu patterns (films) by using the hybrid Cu ink show resistivity as low as 60 μΩ•cm after sintering under mid processing conditions (e.g., sintering at 110°C for 20 min in nitrogen atmosphere). The results also show that sintered Cu films of the hybrid Cu ink have good adhesion property on glass, polyimide (PI) and polyethylene terephthalate (PET) substrates, and the flexible Cu circuits on flattening and bending PI or PET substrates play the function well, in terms of easily lighting LEDs (light emitting diodes) in the circuits. Finally, the wearable strain sensor fabricated by using the hybrid Cu ink can also be well used to monitor the movement of human finger. All these results show that the hybrid Cu ink has high potential for application in printed flexible electronics.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127872034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00311
Ser Choong Chong, Ismael Cereno Daniel, S. Lim Pei Siang, Joseph Shim Cheng Yi, Alvin Lai Wai Song, Woon Leng Loh
Chip to Wafer Hybrid Bonding is an attractive way to achieve ultra-fine pitch interconnect down to 6μm. Conventional way such as solder interconnects has issues of solder merging, underfill voids, and weak intermetallic solder joints that unable to implement in ultra-fine pitch interconnects.Hybrid Bonding itself also has many issues such as Cu dishing or protrusion, oxide surface roughness and the cleanliness of the bonding surface. Singulation process is known to introduce particles such as silicon debris on the wafer’s surface. A protective layer is deposited on the wafer before the singulation process to prevent the silicon debris from sticking on the wafer’s surface. Detail optimization of cleaning process involving different protective layer and cleaning parameters were done. Yield of the diced wafer with respect to the cleanliness of the wafer’s surface has improved with optimized cleaning parameters and the right protective layer. The improved cleaning process was adopted in the preparation of the diced wafer for chip to wafer bonding. The study clearly showed that the void has drastically reduced to less than 3% in the diced wafer prepared with protective layer as compared to range of 0.2 to 91% voids for the diced wafer prepared without protective layer.
{"title":"Yield Improvement in Chip to Wafer Hybrid Bonding","authors":"Ser Choong Chong, Ismael Cereno Daniel, S. Lim Pei Siang, Joseph Shim Cheng Yi, Alvin Lai Wai Song, Woon Leng Loh","doi":"10.1109/ectc51906.2022.00311","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00311","url":null,"abstract":"Chip to Wafer Hybrid Bonding is an attractive way to achieve ultra-fine pitch interconnect down to 6μm. Conventional way such as solder interconnects has issues of solder merging, underfill voids, and weak intermetallic solder joints that unable to implement in ultra-fine pitch interconnects.Hybrid Bonding itself also has many issues such as Cu dishing or protrusion, oxide surface roughness and the cleanliness of the bonding surface. Singulation process is known to introduce particles such as silicon debris on the wafer’s surface. A protective layer is deposited on the wafer before the singulation process to prevent the silicon debris from sticking on the wafer’s surface. Detail optimization of cleaning process involving different protective layer and cleaning parameters were done. Yield of the diced wafer with respect to the cleanliness of the wafer’s surface has improved with optimized cleaning parameters and the right protective layer. The improved cleaning process was adopted in the preparation of the diced wafer for chip to wafer bonding. The study clearly showed that the void has drastically reduced to less than 3% in the diced wafer prepared with protective layer as compared to range of 0.2 to 91% voids for the diced wafer prepared without protective layer.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127978586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}