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2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)最新文献

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A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications 一种适用于高性能2.2D结构下填充成型工艺的新型等效模型
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00090
Yu Liang, Chia-Peng Sun, Chih Chung Hsu, D. Hu, E. Chen, J. Lee
A novel methodology of 3D CAE modeling of capillary underfill of multi-chip packages with a large number of micro bumps is employed in this study. The capillary underfill flow is mainly driven by the surface-tension force based on the contact angle between bumps and substrate. On the other hand, the propagation of the melt front is mainly dominated by the dispensing design of underfill and the distribution of micro bumps. For the simulation of dispensing behavior, 3D modeling is unavoidable. However, the computing cost will become unaffordable due to the number of bumps. To ease the computing cost, an equivalent technique -The Equivalent Bump Group (EBG) model is proposed to the simulation. A simple package is studied to validate the proposed methodology. The case shows that the modeling solution of melt front by EBG model has a good agreement to the detailed model by according dispensing passes. Therefore, it is convinced that the proposed methodology provides a promising simulation solution for the microchip encapsulation for multi-chip packages with large number of micro bumps. A study for a multi-array package of different dispensing designs by EBG model is also conducted. The result shows that filling time can be predicted to get the best dispensing design with minimum filling time.
本文采用了一种新型的多芯片封装毛细管下充填体的三维CAE建模方法。毛细下填土流动主要受基于凸点与衬底接触角的表面张力驱动。另一方面,熔体前缘的扩展主要受下填料的分配设计和微凸起的分布所支配。对于点胶行为的仿真,三维建模是不可避免的。然而,由于大量的颠簸,计算成本将变得难以承受。为了降低计算成本,提出了一种等效技术——等效碰撞组(EBG)模型。研究了一个简单的包来验证所提出的方法。实例表明,EBG模型对熔体前缘的建模解与按点胶道次计算的详细模型吻合较好。因此,该方法为具有大量微凸点的多芯片封装提供了一种有前途的仿真解决方案。利用EBG模型对不同点胶设计的多阵列封装进行了研究。结果表明,通过对灌装时间的预测,可以在最短的灌装时间内得到最佳的配药方案。
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引用次数: 3
RF Characterization on Nb-based Superconducting Silicon Interconnect Fabric for Future Large Scale Quantum Applications 面向未来大规模量子应用的铌基超导硅互连结构的射频特性研究
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00154
Yu-Tao Yang, Haoxiang Ren, S. Chong, Gang Qiu, Shu-Yun Ku, Yang Cheng, Chaowei Hu, Tiema Qian, Kuan-Neng Chen, Ni Ni, Kang L. Wang, S. Iyer
To preserve delicate quantum signals (few hundreds to a few tens of µV), low-loss and low-crosstalk inter-dielet communication is a must in a wafer-scale integrated quantum system using Superconducting-IF. In this paper, inter-dielet links (short: 125 μm and 500 μm; long: 1750 μm) with L/S (2/2 and 5/5 μm) are characterized in a broadband 20 GHz range through simulation and experiments at 4K A compact assembly (inter-dielet spacing of 100 μm) through the quantum-compatible fine-pitch (10 um) Au interlayer is conducted. For insertion loss and crosstalk characterization, the simulated and measured results are presented to be low-loss (<1 dB) and low-crosstalk (< -23 dB) in the broadband 20 GHz range with short (≤ 500 um) and long (1750 um) links and two L/S (2/2 and 5/5 um). It is one of the first 20 GHz broadband RF characterization of short superconducting links (≤ 500 um) through advanced packaging for cryogenic inter-dielet quantum communication. This work brings large-scale quantum computing closer to being realized through compact heterogeneous integration.
为了保持微妙的量子信号(几百到几十µV),在使用超导中频的晶圆级集成量子系统中,低损耗和低串扰的介子间通信是必须的。在本文中,介子间链路(短:125 μm和500 μm;通过在4K条件下的模拟和实验,对长1750 μm、L/S(2/2和5/5 μm)的光纤在宽带20 GHz范围内的特性进行了表征。对于插入损耗和串扰特性,模拟和测量结果表明,在宽带20ghz范围内,具有短(≤500 um)和长(1750 um)链路和两个L/S(2/2和5/5 um),低损耗(<1 dB)和低串扰(< -23 dB)。这是第一个通过先进封装实现低温介子间量子通信的短超导链路(≤500 um)的20 GHz宽带RF表征之一。这项工作使大规模量子计算更接近于通过紧凑的异构集成实现。
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引用次数: 0
Fabrication and Characterization of Nanoporous Gold (NPG) Interconnects for Wafer Level Packaging 晶圆级封装用纳米孔金互连的制备与表征
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00143
L. Dietrich, H. Oppermann, C. Lopper, P. Mackowiak
A novel bumping and bonding technology using sponge-like gold depots with nanometer-scale skeleton construction has been developed and verified. The nanoporous gold (NPG) is formed up by selective etching the silver content from silver/gold alloys, which have been previously electrodeposited on lithographically patterned wafers. Due to the high resolution of the used photoresist systems, highest I/O densities and smallest bump sizes down to 1 μm are achieved. The desired alloy composition is adjustable in a wide range by adequate choice of the metal ion concentration in the electrolyte and by adaption of the deposition rate. The final porosity of the gold can be adjusted by sufficient choice of the etching conditions, and a final coarsening of the NPG texture can be achieved by thermal treatment prior to the bonding process. Thermal as well as mechanical tests were performed to get statements about the characteristics of the skeleton substructure and the reliability of the NPG interconnection. Exemplarily, some thermocompression (TC) bonding results are presented with focus on the NPG interconnect formation.
开发并验证了一种基于纳米骨架结构的海绵状金库碰撞键合新技术。纳米孔金(NPG)是通过选择性蚀刻银/金合金中的银含量而形成的,银/金合金先前已被电沉积在光刻图案的晶圆上。由于所使用的光刻胶系统具有高分辨率,因此可以实现最高的I/O密度和最小的凹凸尺寸(小至1 μm)。通过适当选择电解液中的金属离子浓度和适应沉积速率,所期望的合金成分可在很宽的范围内调节。通过充分选择蚀刻条件可以调整金的最终孔隙率,并且可以通过在粘合过程之前的热处理来实现NPG织构的最终粗化。进行了热学和力学测试,以获得骨架子结构特性和NPG互连可靠性的陈述。举例来说,一些热压(TC)键合的结果,重点是NPG互连的形成。
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引用次数: 1
Printed Microwave Connector 印刷微波连接器
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00345
Jotham Kasule, Shokat Ganjeheizadeh Rohani, M. Pothier, Yuri Piro, A. Akyurtlu, C. Armiento
This paper describes the development of a printed, planar microwave connector operating from 1-7 GHz. The connector, which is based on a Grounded Coplanar Waveguide (GCPW) transmission line structure, is fabricated using 3D-printed thermoplastic material (PEEK) and conductive nanoparticle silver ink. Electromagnetic models were established to provide guidance on design tradeoffs and their impact on microwave performance. New mechanical designs were also developed to provide accurate alignment and robust connection of the two halves of the planar connector structure. Initial connector prototypes were fabricated to validate the new planar design using conventional double-sided copper laminates (Isola MT40). The designs were then implemented in an all-printed version of the connector. Electromagnetic models of the printed connectors were developed using the measured dielectric properties of printed PEEK. The insertion loss of the printed connectors was measured to be less than 1.7dB across the band.
本文介绍了一种工作频率为1-7 GHz的印刷平面微波连接器的研制。该连接器基于接地共面波导(GCPW)传输线结构,使用3d打印热塑性材料(PEEK)和导电纳米颗粒银墨水制造。建立了电磁模型,为设计权衡及其对微波性能的影响提供指导。新的机械设计也被开发,以提供精确的对准和坚固的连接两半的平面连接器结构。最初的连接器原型是使用传统的双面铜层压板(Isola MT40)制作的,以验证新的平面设计。然后在连接器的全打印版本中实现这些设计。通过测量印刷PEEK的介电性能,建立了印刷连接器的电磁模型。经测量,打印连接器的插入损耗在整个频带内小于1.7dB。
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引用次数: 1
Optimization of PI & PBO Layers Lithography Process for High Density Fan-Out Wafer Level Packaging & Next Generation Heterogeneous Integration Applications Employing Digitally Driven Maskless Lithography 采用数字驱动无掩膜光刻技术的高密度扇出晶圆级封装和下一代异构集成应用的PI和PBO层光刻工艺优化
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00239
T. Uhrmann, B. Povazay, T. Zenger, Bemd Thallner, R. Holly, Bozena Matuskova Lednicka, Mario Reybrouck, Niels Van Herck, Bart Persijn, D. Janssen, S. Vanclooster, Stef Heirbaut
The updated roadmap for advanced packaging shows an increased need for denser next-generation heterogeneous integration designs. With the goal of further reducing the currently achieved via diameters in critical dielectric layers tailored for FOWLP, we evaluated high performing polyimide (PI) and polybenzoxazole (PBO) materials using a maskless exposure lithography system that enables instant design changes.
先进封装的更新路线图表明,对更密集的下一代异构集成设计的需求增加了。为了进一步减少目前为FOWLP量身定制的关键介电层的直径,我们使用无掩模曝光光刻系统评估了高性能聚酰亚胺(PI)和聚苯并恶唑(PBO)材料,该系统可以实现即时设计更改。
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引用次数: 2
Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing 基于玻璃的3D封装架构与嵌入式芯片的高性能计算演示
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00180
Siddharth Ravichandran, V. Smet, Madhavan Swaminathan, R. Tummala
This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.
本文介绍了两种新型的基于三维玻璃的高性能计算架构的技术演示。目前的3D技术受到硅通孔(tsv)的限制,而基于玻璃面板嵌入(GPE)的方法消除了tsv,从而形成了一个更强大的3D封装平台,支持各种架构。本文设计并演示了两个这样的体系结构。第一辆测试车展示了多个嵌在玻璃腔内并相互连接的模具,以及使用微碰撞接口组装在顶部的模具。第二辆测试车展示了一个50x50毫米的玻璃中间层封装,核心中嵌入了4个芯片,8个HBM模拟器和2个大型soc,顶部以35微米的凹凸间距组装。
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引用次数: 1
Stability Analysis of Nanoscale Copper-Carbon Hybrid Interconnects 纳米级铜碳杂化互连的稳定性分析
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00158
B. Kumari, Rohit Sharma, Manodipan Sahoo
Copper Carbon (Cu-Carbon) hybrid interconnect is a new and an extremely promising candidate for future VLSI circuit applications, so it needs to be analyzed for not only propagation delay but its stability should also be examined in order to consolidate its claim as an alternative to existing interconnect configurations. In this work, stability analysis of the recently proposed Cu-Carbon hybrid interconnect is performed and compared with existing alternate hybrid interconnect candidates (i.e. copper, copper-graphene hybrid and copper-carbon nanotube composite). A three-line coupled interconnect system for 7 nm technology node is considered in this study whose dimensional parameters are adopted as per the IRDS roadmap guidelines. The unit-step response of Cu-Carbon hybrid interconnect is steepest as compared to others because of its lowest switching delay. Cu-Carbon hybrid appears to be the most stable as its nyquist plot intersects farthest from the critical point (-1, j0) towards origin. The effect of crosstalk leads to undershoots as seen in the time domain response of copper interconnects, but it does not have any notable effect on Cu-Carbon hybrid interconnects. It is evident that as the fraction of carbon nanotube in Cu-Carbon hybrid (Fcnt) increases, bandwidth increases due to decrease in resistance. Also, Cu-Carbon with Fcnt = 0.8 is most stable amongst all configurations. We conclude that Cu-Carbon hybrid is the most stable candidate among all the alternative interconnect configurations, claiming it to be a desirable interconnect alternative for near-future VLSI applications.
铜碳(Cu-Carbon)混合互连是未来VLSI电路应用中极有前途的新候选,因此不仅需要分析其传播延迟,还应检查其稳定性,以巩固其作为现有互连配置替代方案的主张。在这项工作中,对最近提出的cu -碳杂化互连进行了稳定性分析,并与现有的替代杂化互连候选(即铜,铜-石墨烯杂化和铜-碳纳米管复合材料)进行了比较。本研究考虑7纳米技术节点的三线耦合互连系统,其尺寸参数采用IRDS路线图指南。铜碳混合互连的单位阶跃响应是最快的,因为它的切换延迟最低。cu -碳杂化的奈奎斯特图在离原点(- 1,0)最远的地方相交最稳定。串扰的影响导致铜互连的时域响应出现欠冲现象,但对铜碳杂化互连没有显著影响。结果表明,随着碳纳米管在铜碳杂化材料(Fcnt)中所占比例的增加,由于电阻的降低,带宽增加。此外,Fcnt = 0.8的Cu-Carbon是所有构型中最稳定的。我们得出结论,铜碳混合是所有替代互连配置中最稳定的候选者,声称它是近期VLSI应用的理想互连替代方案。
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引用次数: 2
60 GHz 0-360˚ Passive Analog Delay Line in Liquid Crystal Technology based on a Novel Conductor-backed Fully-enclosed Coplanar Waveguide 基于新型全封装共面波导的60 GHz 0-360˚液晶无源模拟延迟线
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00289
Jinfeng Li
A new 0-360° continuously-variable true-time-delay phase shifter (delay line) based on liquid crystal (LC) is prototyped targeting 60 GHz inter-satellite cross-links. The device is developed on a stray-modes-free conductor-backed fully-enclosed coplanar waveguide (CB-ECPW). The novelty is underpinned by an electric field homogenisation concept, as well as insertion losses balancing at various phase-delay states by smart impedance-matching to remove beam-steering distortions without using amplitude compensation networks. The manufacturing features nickel-free gold-plating and vias plated shut. Measured worst-case insertion loss being -7.04 dB (0-360° phase-shifting) and phase-tuning rise time being 0.6 seconds at 60 GHz, the device demonstrates an improvement of up to 1 dB for the forward transmission coefficient, as well as a reduction of 3.4 seconds for the response time compared against our previously optimised LC-based ECPW phase shifter. These enable the new device to compete with existing waveguide-based LC analog delay lines in terms of various figure-of-merits and agility.
针对60ghz星间交叉链路,研制了一种基于液晶(LC)的新型0-360°连续可变真时延移相器(延迟线)。该器件是在无杂散模式的全封闭式共面波导(CB-ECPW)上开发的。该新颖技术的基础是电场均匀化概念,以及通过智能阻抗匹配在各种相位延迟状态下平衡插入损耗,从而消除波束转向畸变,而无需使用幅度补偿网络。制造特点是无镍镀金和镀孔关闭。测量的最坏情况插入损耗为-7.04 dB(0-360°相移),相位调谐上升时间为0.6秒,在60 GHz下,该器件的正向传输系数提高了1 dB,与我们之前优化的基于lc的ECPW移相器相比,响应时间缩短了3.4秒。这使得新器件能够在各种优点和敏捷性方面与现有的基于波导的LC模拟延迟线竞争。
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引用次数: 2
Fabrication of wearable strain sensor by using a novel hybrid Cu ink composed of bimodal Cu particle ink and Cu-based metal-organic decomposition ink 由双峰铜颗粒油墨和铜基金属有机分解油墨组成的新型混合铜油墨制备可穿戴应变传感器
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00132
Cong Gan, Hai-Jun Huang, Bin Hou, Min-bo Zhou, Xin-Ping Zhang
In this work, bimodal Cu particles have been synthesized by using 2-amino-2-methyl-1-propanol (AMP)-based hybrid capping agent for the first time. A novel hybrid Cu ink is prepared by combining bimodal Cu particles with solvents and Cu-based metal-organic decomposition (MOD) ink composed of Cu(II) formate, AMP and octylamine. The printed Cu patterns (films) by using the hybrid Cu ink show resistivity as low as 60 μΩ•cm after sintering under mid processing conditions (e.g., sintering at 110°C for 20 min in nitrogen atmosphere). The results also show that sintered Cu films of the hybrid Cu ink have good adhesion property on glass, polyimide (PI) and polyethylene terephthalate (PET) substrates, and the flexible Cu circuits on flattening and bending PI or PET substrates play the function well, in terms of easily lighting LEDs (light emitting diodes) in the circuits. Finally, the wearable strain sensor fabricated by using the hybrid Cu ink can also be well used to monitor the movement of human finger. All these results show that the hybrid Cu ink has high potential for application in printed flexible electronics.
本文首次采用2-氨基-2-甲基-1-丙醇(AMP)基杂化封盖剂合成了双峰铜颗粒。将双峰态铜颗粒与溶剂结合,制备了一种新型的铜基金属有机分解(MOD)油墨,该油墨由甲酸铜、AMP和辛胺组成。在中等工艺条件下(例如,在氮气气氛中110℃烧结20 min),使用混合铜墨水打印的Cu图案(薄膜)在烧结后的电阻率低至60 μΩ•cm。结果还表明,混合Cu油墨的烧结Cu膜在玻璃、聚酰亚胺(PI)和聚对苯二甲酸乙二醇酯(PET)基板上具有良好的粘附性能,并且在PI或PET基板上的柔性Cu电路可以很好地发挥作用,易于点亮电路中的led(发光二极管)。最后,利用混合铜墨水制作的可穿戴应变传感器也可以很好地用于监测人体手指的运动。这些结果表明,混合铜油墨在印刷柔性电子领域具有很大的应用潜力。
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引用次数: 0
Yield Improvement in Chip to Wafer Hybrid Bonding 晶片-晶片混合键合的良率提升
Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00311
Ser Choong Chong, Ismael Cereno Daniel, S. Lim Pei Siang, Joseph Shim Cheng Yi, Alvin Lai Wai Song, Woon Leng Loh
Chip to Wafer Hybrid Bonding is an attractive way to achieve ultra-fine pitch interconnect down to 6μm. Conventional way such as solder interconnects has issues of solder merging, underfill voids, and weak intermetallic solder joints that unable to implement in ultra-fine pitch interconnects.Hybrid Bonding itself also has many issues such as Cu dishing or protrusion, oxide surface roughness and the cleanliness of the bonding surface. Singulation process is known to introduce particles such as silicon debris on the wafer’s surface. A protective layer is deposited on the wafer before the singulation process to prevent the silicon debris from sticking on the wafer’s surface. Detail optimization of cleaning process involving different protective layer and cleaning parameters were done. Yield of the diced wafer with respect to the cleanliness of the wafer’s surface has improved with optimized cleaning parameters and the right protective layer. The improved cleaning process was adopted in the preparation of the diced wafer for chip to wafer bonding. The study clearly showed that the void has drastically reduced to less than 3% in the diced wafer prepared with protective layer as compared to range of 0.2 to 91% voids for the diced wafer prepared without protective layer.
芯片与晶圆之间的混合键合是实现低至6μm的超细间距互连的一种有吸引力的方法。传统的焊料互连方式存在焊料合并、欠填充空隙和弱金属间焊点等问题,无法实现超细间距互连。混合键合本身也存在许多问题,如铜盘或突出,氧化物表面粗糙度和键合表面的清洁度。众所周知,模拟过程会在晶圆表面引入硅碎片等颗粒。在模拟过程之前,在晶圆上沉积一保护层,以防止硅屑粘附在晶圆表面。对不同保护层和清洗参数的清洗工艺进行了详细的优化。通过优化的清洗参数和正确的保护层,晶圆片的成品率与晶圆片表面的清洁度有关。采用改进的清洗工艺制备了片与片之间键合的晶圆片。研究清楚地表明,与没有保护层的晶圆片的0.2 - 91%的空隙相比,有保护层的晶圆片的空隙急剧减少到3%以下。
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引用次数: 4
期刊
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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