Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00201
Vigneshwarram Kumaresan, M. Devarajan
Liquid thermal gap fillers play a vital role in dissipating heat from electronic components to enclosure surfaces. However, oil bleed from silicone-based liquid thermal gap filler causes contamination on enclosure substrates. It is essential to develop a non-oil bleed, thermally reliable thermal gap filler for solid state drive (SSD). In this work, a novel two-part thermal gap filler was synthesized. The long-term stability and reliability of thermal gap filler were evaluated using a highly accelerated temperature and humidity stress test (HAST). Thermal conductivity of cured thermal gap fillers were investigated before and after HAST. It was found that newly formulated thermal gap filler was stable even at high temperature and high humidity environments. Thus, the newly formulated thermal gap filler can effectively dissipate heat and enhance the performance and reliability of SSD.
{"title":"Non-oil bleed thermal gap fillers for long-term reliability of Solid State Drive","authors":"Vigneshwarram Kumaresan, M. Devarajan","doi":"10.1109/ectc51906.2022.00201","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00201","url":null,"abstract":"Liquid thermal gap fillers play a vital role in dissipating heat from electronic components to enclosure surfaces. However, oil bleed from silicone-based liquid thermal gap filler causes contamination on enclosure substrates. It is essential to develop a non-oil bleed, thermally reliable thermal gap filler for solid state drive (SSD). In this work, a novel two-part thermal gap filler was synthesized. The long-term stability and reliability of thermal gap filler were evaluated using a highly accelerated temperature and humidity stress test (HAST). Thermal conductivity of cured thermal gap fillers were investigated before and after HAST. It was found that newly formulated thermal gap filler was stable even at high temperature and high humidity environments. Thus, the newly formulated thermal gap filler can effectively dissipate heat and enhance the performance and reliability of SSD.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116073911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00308
Daisuke Hironiwa, Haw Wen Chen, Y. Morikawa, Takashi Kurimoto, R. Kamimura
With the increasing demand for high-performance devices, the achievement of high-density package products become a crucial topic. However, the scale of semiconductor chips is difficult to miniature furthermore. Against this background, the technology of the semiconductor packages is focused to improve device performance. The package structure changes greatly depending on the intended use of the device. Thus, the process of miniaturizing the wiring layer is an important item to improve the performance of almost packaged products. This report describes plasma treatment for the fabrication of redistribution layer (RDL) using photosensitive polyimide (PI) by the dry ashing equipment with the method of surface wave plasma (SWP) and capacitively coupled plasma (CCP). In order to fabricate a high-performance RDL, it is necessary to control the surface situation of copper wiring, PI, and photoresist (PR) more delicately than ever before. In this paper, we report the survey results for each process to fabricate RDL.
{"title":"The investigation of dry plasma technology in each steps for the fabrication of high performance redistribution layer","authors":"Daisuke Hironiwa, Haw Wen Chen, Y. Morikawa, Takashi Kurimoto, R. Kamimura","doi":"10.1109/ectc51906.2022.00308","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00308","url":null,"abstract":"With the increasing demand for high-performance devices, the achievement of high-density package products become a crucial topic. However, the scale of semiconductor chips is difficult to miniature furthermore. Against this background, the technology of the semiconductor packages is focused to improve device performance. The package structure changes greatly depending on the intended use of the device. Thus, the process of miniaturizing the wiring layer is an important item to improve the performance of almost packaged products. This report describes plasma treatment for the fabrication of redistribution layer (RDL) using photosensitive polyimide (PI) by the dry ashing equipment with the method of surface wave plasma (SWP) and capacitively coupled plasma (CCP). In order to fabricate a high-performance RDL, it is necessary to control the surface situation of copper wiring, PI, and photoresist (PR) more delicately than ever before. In this paper, we report the survey results for each process to fabricate RDL.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114890763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00235
M. A. Haq, M. A. Hoque, G. R. Mazumder, J. Suhling, P. Lall
Solder joints in electronic packages often experience fatigue failures due to cyclic mechanical stresses and strains in fluctuating temperature environments. This cyclic loading of the solder is induced by mismatches in coefficients of thermal expansion and leads to damage accumulation that contributes to crack initiation, crack propagation, and eventually to failure. In our previous papers, we have investigated the accumulation of damage in several lead free solder materials (SAC305, SAC+Bi, and SAC+Bi-Ni-Sb) during mechanical cycling at room temperature (25 C) and elevated temperature (100 C). Circular cross-section solder specimens were first reflowed, and these samples were then mechanically cycled for various durations using a Micro-Mechanical tester. Monotonic stress-strain and creep tests were subsequently conducted on the prior cycled samples to characterize the change in mechanical behavior occurring in the solder due to damage accumulation. Using the data from these tests, we have been able to characterize and quantify the cycling induced damage through the observed degradations of several mechanical properties (initial elastic modulus, ultimate tensile strength, yield stress, and creep strain rate) with the amount of prior cycling. All of the mechanical cyclic testing in our prior work were performed for a single applied level of cyclic strain = +/- 0.01 (single level of damage per cycle), which corresponded to a hysteresis loop area (energy dissipated per cycle) during room temperature cycling of SAC305 of ΔW = 1.2 MJ/m3.In the current work, we have extended the experimental work in our prior studies on SAC305 to examine several levels of damage during cycling, as well as several cycling temperatures. Material behaviors of the pre-cycled solder were characterized for the various damage levels per cycle and durations of cycling. One goal of this investigation was to identify a damage parameter that can be used to predict the observed material property degradations occurring during cyclic loading of solder irrespective of the way that the damage is accumulated. The total energy dissipation occurring in the solder during cycling was found to correlate well with the evolution of mechanical properties, independent of the damage level applied during each cycle.In the experimental testing, small uniaxial cylindrical samples of SAC305 solder were prepared and reflowed in a reflow oven. These specimens were then mechanically cycled under several different sets of conditions to induce various levels of damage in the samples. In particular, four levels of initial damage per cycle were considered (ΔW = 0.25, 0.50, 0.75 and 1.00 MJ/m3), as well as three cycling temperatures (T = 25, 100, and 125 °C). For each of these damage levels per cycle, various durations of cycling were applied (e.g. 0, 50, 100, 200, 300, 600, and 1200 cycles). This test matrix generated a large set of prior damaged samples, where the damage had been accumulated at different
{"title":"Evolution of SAC305 Mechanical Behavior Due to Damage Accumulation During Cycling","authors":"M. A. Haq, M. A. Hoque, G. R. Mazumder, J. Suhling, P. Lall","doi":"10.1109/ectc51906.2022.00235","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00235","url":null,"abstract":"Solder joints in electronic packages often experience fatigue failures due to cyclic mechanical stresses and strains in fluctuating temperature environments. This cyclic loading of the solder is induced by mismatches in coefficients of thermal expansion and leads to damage accumulation that contributes to crack initiation, crack propagation, and eventually to failure. In our previous papers, we have investigated the accumulation of damage in several lead free solder materials (SAC305, SAC+Bi, and SAC+Bi-Ni-Sb) during mechanical cycling at room temperature (25 C) and elevated temperature (100 C). Circular cross-section solder specimens were first reflowed, and these samples were then mechanically cycled for various durations using a Micro-Mechanical tester. Monotonic stress-strain and creep tests were subsequently conducted on the prior cycled samples to characterize the change in mechanical behavior occurring in the solder due to damage accumulation. Using the data from these tests, we have been able to characterize and quantify the cycling induced damage through the observed degradations of several mechanical properties (initial elastic modulus, ultimate tensile strength, yield stress, and creep strain rate) with the amount of prior cycling. All of the mechanical cyclic testing in our prior work were performed for a single applied level of cyclic strain = +/- 0.01 (single level of damage per cycle), which corresponded to a hysteresis loop area (energy dissipated per cycle) during room temperature cycling of SAC305 of ΔW = 1.2 MJ/m3.In the current work, we have extended the experimental work in our prior studies on SAC305 to examine several levels of damage during cycling, as well as several cycling temperatures. Material behaviors of the pre-cycled solder were characterized for the various damage levels per cycle and durations of cycling. One goal of this investigation was to identify a damage parameter that can be used to predict the observed material property degradations occurring during cyclic loading of solder irrespective of the way that the damage is accumulated. The total energy dissipation occurring in the solder during cycling was found to correlate well with the evolution of mechanical properties, independent of the damage level applied during each cycle.In the experimental testing, small uniaxial cylindrical samples of SAC305 solder were prepared and reflowed in a reflow oven. These specimens were then mechanically cycled under several different sets of conditions to induce various levels of damage in the samples. In particular, four levels of initial damage per cycle were considered (ΔW = 0.25, 0.50, 0.75 and 1.00 MJ/m3), as well as three cycling temperatures (T = 25, 100, and 125 °C). For each of these damage levels per cycle, various durations of cycling were applied (e.g. 0, 50, 100, 200, 300, 600, and 1200 cycles). This test matrix generated a large set of prior damaged samples, where the damage had been accumulated at different","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116582595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00275
Saw Lip Teng, M. Devarajan
This work explores underfill with improved properties for rework-ability and package reliability. Reworkable underfills (Epoxy-R1 – R5) were customized by a material supplier and benchmarked with an existing non-reworkable underfill (Epoxy-E). R1 shows similar glass transition temperature (Tg), coefficient of thermal expansion 1&2 (CTE) with Epoxy-E, lower storage modulus (30% of Epoxy-E), yet still poor for rework due to major damage on printed circuit board (PCB) detected. R2 was refined with much lower modulus, 10% of Epoxy-E, but failed to meet target Tg and CTE. R3 used smaller filler size (10um) in formulation, reliability related properties were significantly improved, however, same overheat issue on adjacent component and insufficient coverage was found. For R4 and R5, both Tg reached above 130°C and low CTE-2 around 100ppm/°C, which is only 70% of Epoxy-E. For rework evaluation, R4 and R5 showed good results, no adjacent defects which are suspected due to lower adhesion, underfill is easier to remove. R5 was selected for reliability test due to its similarity in viscosity and process condition compared to Epoxy-E with minimal change in dispensing process setup. R5 test vehicle survived 1000 thermal cycling (-40°C to 85°C) meeting mechanical shock and vibration tests qualification. Lastly, it was observed that R5 achieved both rework-ability and package reliability expectations with a new defined thermo-mechanical property.
{"title":"Thermo-Mechanical Reworkable Epoxy Underfill in Board-Level Package: Material Characteristics and Reliability Criteria","authors":"Saw Lip Teng, M. Devarajan","doi":"10.1109/ectc51906.2022.00275","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00275","url":null,"abstract":"This work explores underfill with improved properties for rework-ability and package reliability. Reworkable underfills (Epoxy-R1 – R5) were customized by a material supplier and benchmarked with an existing non-reworkable underfill (Epoxy-E). R1 shows similar glass transition temperature (Tg), coefficient of thermal expansion 1&2 (CTE) with Epoxy-E, lower storage modulus (30% of Epoxy-E), yet still poor for rework due to major damage on printed circuit board (PCB) detected. R2 was refined with much lower modulus, 10% of Epoxy-E, but failed to meet target Tg and CTE. R3 used smaller filler size (10um) in formulation, reliability related properties were significantly improved, however, same overheat issue on adjacent component and insufficient coverage was found. For R4 and R5, both Tg reached above 130°C and low CTE-2 around 100ppm/°C, which is only 70% of Epoxy-E. For rework evaluation, R4 and R5 showed good results, no adjacent defects which are suspected due to lower adhesion, underfill is easier to remove. R5 was selected for reliability test due to its similarity in viscosity and process condition compared to Epoxy-E with minimal change in dispensing process setup. R5 test vehicle survived 1000 thermal cycling (-40°C to 85°C) meeting mechanical shock and vibration tests qualification. Lastly, it was observed that R5 achieved both rework-ability and package reliability expectations with a new defined thermo-mechanical property.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116876072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00345
Jotham Kasule, Shokat Ganjeheizadeh Rohani, M. Pothier, Yuri Piro, A. Akyurtlu, C. Armiento
This paper describes the development of a printed, planar microwave connector operating from 1-7 GHz. The connector, which is based on a Grounded Coplanar Waveguide (GCPW) transmission line structure, is fabricated using 3D-printed thermoplastic material (PEEK) and conductive nanoparticle silver ink. Electromagnetic models were established to provide guidance on design tradeoffs and their impact on microwave performance. New mechanical designs were also developed to provide accurate alignment and robust connection of the two halves of the planar connector structure. Initial connector prototypes were fabricated to validate the new planar design using conventional double-sided copper laminates (Isola MT40). The designs were then implemented in an all-printed version of the connector. Electromagnetic models of the printed connectors were developed using the measured dielectric properties of printed PEEK. The insertion loss of the printed connectors was measured to be less than 1.7dB across the band.
{"title":"Printed Microwave Connector","authors":"Jotham Kasule, Shokat Ganjeheizadeh Rohani, M. Pothier, Yuri Piro, A. Akyurtlu, C. Armiento","doi":"10.1109/ectc51906.2022.00345","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00345","url":null,"abstract":"This paper describes the development of a printed, planar microwave connector operating from 1-7 GHz. The connector, which is based on a Grounded Coplanar Waveguide (GCPW) transmission line structure, is fabricated using 3D-printed thermoplastic material (PEEK) and conductive nanoparticle silver ink. Electromagnetic models were established to provide guidance on design tradeoffs and their impact on microwave performance. New mechanical designs were also developed to provide accurate alignment and robust connection of the two halves of the planar connector structure. Initial connector prototypes were fabricated to validate the new planar design using conventional double-sided copper laminates (Isola MT40). The designs were then implemented in an all-printed version of the connector. Electromagnetic models of the printed connectors were developed using the measured dielectric properties of printed PEEK. The insertion loss of the printed connectors was measured to be less than 1.7dB across the band.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116291546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00066
I-Hung Lin, Cheng-Chen Lin, Ying-Chieh Pan, B. Lwo, Tom Ni
This paper first presents the architecture of a self-designed, slot-coupled patch antenna unit in a glass-embedded fan-out antenna in package. Due to the embedded glass, design flexible and the radiation properties of the antenna structure was improved by single or double-sided patch made by redistribution layers (RDLs) on the embedded glass surfaces. The FOAiP is an extended application of fan-out technology in the advanced electronics package. It provides an ideal approach for millimeter-wave (mmWave) chip with low transmission loss of chip-to-antenna interconnect and greater design flexibilities. However, mmWave signals from a single antenna cannot be concentrated over a long distance because of its limited transmission power. Therefore, an antenna array was explored to enhance the antenna gain and the transmission distance in this study, and the full wave 3D electromagnetic (EM) simulation software (ANSYS HFSS) was employed to simulate the antenna characteristics of the FOAiP with varying structural designs and the characteristics of the array antenna with various array forms. In the slot-coupled antenna structure, the microstrip and the grounding coplanar waveguide (CPW) layer are located at RDL-1 (the feeding interconnection) and RDL-2 (beneath the glass), respectively, and the reflector layer is located on the PCB surface. As a result, a single antenna model was optimized with center frequency of 60 GHz with 5.5db gain and the bandwidth was 3.89 GHz. With the optimized antenna unit, the simulation results on antenna arrays revealed that the radiation field patterns were efficiently concentrated and the gains were increased with the array size, but the antenna bandwidths were slightly different. Furthermore, the four-by-four array antenna exhibited gain increased by 3.2 times than a single antenna. That is, the optimal characteristics of the antenna array had 59.83 GHz center frequency, 17.6 dB gain, and its bandwidth was 4.1 GHz.
{"title":"Characteristics of Glass-Embedded FOAiP with Antenna Arrays for 60GHz mmWave Applications","authors":"I-Hung Lin, Cheng-Chen Lin, Ying-Chieh Pan, B. Lwo, Tom Ni","doi":"10.1109/ectc51906.2022.00066","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00066","url":null,"abstract":"This paper first presents the architecture of a self-designed, slot-coupled patch antenna unit in a glass-embedded fan-out antenna in package. Due to the embedded glass, design flexible and the radiation properties of the antenna structure was improved by single or double-sided patch made by redistribution layers (RDLs) on the embedded glass surfaces. The FOAiP is an extended application of fan-out technology in the advanced electronics package. It provides an ideal approach for millimeter-wave (mmWave) chip with low transmission loss of chip-to-antenna interconnect and greater design flexibilities. However, mmWave signals from a single antenna cannot be concentrated over a long distance because of its limited transmission power. Therefore, an antenna array was explored to enhance the antenna gain and the transmission distance in this study, and the full wave 3D electromagnetic (EM) simulation software (ANSYS HFSS) was employed to simulate the antenna characteristics of the FOAiP with varying structural designs and the characteristics of the array antenna with various array forms. In the slot-coupled antenna structure, the microstrip and the grounding coplanar waveguide (CPW) layer are located at RDL-1 (the feeding interconnection) and RDL-2 (beneath the glass), respectively, and the reflector layer is located on the PCB surface. As a result, a single antenna model was optimized with center frequency of 60 GHz with 5.5db gain and the bandwidth was 3.89 GHz. With the optimized antenna unit, the simulation results on antenna arrays revealed that the radiation field patterns were efficiently concentrated and the gains were increased with the array size, but the antenna bandwidths were slightly different. Furthermore, the four-by-four array antenna exhibited gain increased by 3.2 times than a single antenna. That is, the optimal characteristics of the antenna array had 59.83 GHz center frequency, 17.6 dB gain, and its bandwidth was 4.1 GHz.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115194742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00009
X. Sun, J. Slabbekoorn, S. Sinha, P. Bex, N. Pinho, T. Webers, D. Velenis, A. Miller, N. Collaert, G. van der Plas, E. Beyne
We present a highly-scaled packaging and system-integration RF interposer platform on low-resistivity Si (15-25 Ωcm). The heterogenous platform has been processed and characterized by measurements in the frequency range from 10 MHz to 110 GHz, revealing an interconnect insertion loss less than 0.3 dB/mm at 100 GHz and Qmax above 40 for integrated inductors. The excellent performance of the RF Si interposer enables high frequency interconnects between the ICs and the partial matching network in the package. The narrow pitch of the μbumps further enables flip-chip performance up to 500 GHz, allowing for heterogenous integration of multiple mm-wave ICs in different technologies, together with integrated high-Q passives, as well as antennas-in-package for RF to beyond-5G applications.
{"title":"Cost-effective RF interposer platform on low-resistivity Si enabling heterogeneous integration opportunities for beyond 5G","authors":"X. Sun, J. Slabbekoorn, S. Sinha, P. Bex, N. Pinho, T. Webers, D. Velenis, A. Miller, N. Collaert, G. van der Plas, E. Beyne","doi":"10.1109/ectc51906.2022.00009","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00009","url":null,"abstract":"We present a highly-scaled packaging and system-integration RF interposer platform on low-resistivity Si (15-25 Ωcm). The heterogenous platform has been processed and characterized by measurements in the frequency range from 10 MHz to 110 GHz, revealing an interconnect insertion loss less than 0.3 dB/mm at 100 GHz and Qmax above 40 for integrated inductors. The excellent performance of the RF Si interposer enables high frequency interconnects between the ICs and the partial matching network in the package. The narrow pitch of the μbumps further enables flip-chip performance up to 500 GHz, allowing for heterogenous integration of multiple mm-wave ICs in different technologies, together with integrated high-Q passives, as well as antennas-in-package for RF to beyond-5G applications.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00232
L. Yip, Rosa Lin, C.W. Lai, C. Peng
As the cost of advanced silicon nodes continue to rise, high-performance devices are shifting towards advanced packaging to reduce the overall cost, increase functionality, and improve performance. Fan-out packaging technology is an advanced packaging approach that has increasingly been adopted for networking, artificial intelligence, and high-performance computing (HPC) applications. Fan-out technology enables multi-chip integration using fine pitch and small line width copper redistribution layer (RDL) technology to interconnect different dies resulting in a flexible and cost-effective package solution. However, as the fan-out package size increases to accommodate higher I/O counts and higher bandwidth, package warpage and reliability become more challenging. The main challenges in building large size packages (ı65x65mm2) with fan-out technology are warpage, RDL integrity, and package reliability. In this paper, we discuss the reliability assessment of a 1.6X reticle size integrated fan-out multi-chip assembly on large organic substrates for networking applications. The package integrates a 7 nm ASIC die and 8 I/O chiplets with 3 layers of fine-pitch RDL interconnection. The coefficient of thermal expansion (CTE) mismatch between different materials in the package structure can cause the device to warp and induce mechanical stresses that can cause RDL cracking and other failures in the package. We will discuss package design and processing methods for improving RDL integrity to enhance overall package reliability. By using finite element stress analysis to optimize the RDL design, robust large format multi-chip fan-out packages were developed and validated through reliability testing.
{"title":"Reliability Challenges of High-Density Fan-out Packaging for High-Performance Computing Applications","authors":"L. Yip, Rosa Lin, C.W. Lai, C. Peng","doi":"10.1109/ectc51906.2022.00232","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00232","url":null,"abstract":"As the cost of advanced silicon nodes continue to rise, high-performance devices are shifting towards advanced packaging to reduce the overall cost, increase functionality, and improve performance. Fan-out packaging technology is an advanced packaging approach that has increasingly been adopted for networking, artificial intelligence, and high-performance computing (HPC) applications. Fan-out technology enables multi-chip integration using fine pitch and small line width copper redistribution layer (RDL) technology to interconnect different dies resulting in a flexible and cost-effective package solution. However, as the fan-out package size increases to accommodate higher I/O counts and higher bandwidth, package warpage and reliability become more challenging. The main challenges in building large size packages (ı65x65mm2) with fan-out technology are warpage, RDL integrity, and package reliability. In this paper, we discuss the reliability assessment of a 1.6X reticle size integrated fan-out multi-chip assembly on large organic substrates for networking applications. The package integrates a 7 nm ASIC die and 8 I/O chiplets with 3 layers of fine-pitch RDL interconnection. The coefficient of thermal expansion (CTE) mismatch between different materials in the package structure can cause the device to warp and induce mechanical stresses that can cause RDL cracking and other failures in the package. We will discuss package design and processing methods for improving RDL integrity to enhance overall package reliability. By using finite element stress analysis to optimize the RDL design, robust large format multi-chip fan-out packages were developed and validated through reliability testing.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00289
Jinfeng Li
A new 0-360° continuously-variable true-time-delay phase shifter (delay line) based on liquid crystal (LC) is prototyped targeting 60 GHz inter-satellite cross-links. The device is developed on a stray-modes-free conductor-backed fully-enclosed coplanar waveguide (CB-ECPW). The novelty is underpinned by an electric field homogenisation concept, as well as insertion losses balancing at various phase-delay states by smart impedance-matching to remove beam-steering distortions without using amplitude compensation networks. The manufacturing features nickel-free gold-plating and vias plated shut. Measured worst-case insertion loss being -7.04 dB (0-360° phase-shifting) and phase-tuning rise time being 0.6 seconds at 60 GHz, the device demonstrates an improvement of up to 1 dB for the forward transmission coefficient, as well as a reduction of 3.4 seconds for the response time compared against our previously optimised LC-based ECPW phase shifter. These enable the new device to compete with existing waveguide-based LC analog delay lines in terms of various figure-of-merits and agility.
{"title":"60 GHz 0-360˚ Passive Analog Delay Line in Liquid Crystal Technology based on a Novel Conductor-backed Fully-enclosed Coplanar Waveguide","authors":"Jinfeng Li","doi":"10.1109/ectc51906.2022.00289","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00289","url":null,"abstract":"A new 0-360° continuously-variable true-time-delay phase shifter (delay line) based on liquid crystal (LC) is prototyped targeting 60 GHz inter-satellite cross-links. The device is developed on a stray-modes-free conductor-backed fully-enclosed coplanar waveguide (CB-ECPW). The novelty is underpinned by an electric field homogenisation concept, as well as insertion losses balancing at various phase-delay states by smart impedance-matching to remove beam-steering distortions without using amplitude compensation networks. The manufacturing features nickel-free gold-plating and vias plated shut. Measured worst-case insertion loss being -7.04 dB (0-360° phase-shifting) and phase-tuning rise time being 0.6 seconds at 60 GHz, the device demonstrates an improvement of up to 1 dB for the forward transmission coefficient, as well as a reduction of 3.4 seconds for the response time compared against our previously optimised LC-based ECPW phase shifter. These enable the new device to compete with existing waveguide-based LC analog delay lines in terms of various figure-of-merits and agility.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125480930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00280
Valeriy Khaldarov, Andy Zhang, Dongji Xie, J. Lee, Xue Shi, R. Roucou, S. Doranga, A. Shalumov
In this paper, a simplified methodology is presented for the evaluation of test-to-failure board-level random vibrations using a combination of experimental and finite element modeling techniques in calculating equivalent stresses for SAC305 solder joints experiencing high- and ultra-high-cycle fatigue usually found in the emerging automotive robo-taxi industry. Some partial results that were obtained during this study allow for an investigation of the effects of a printed circuit board geometry on possible failure modes of Pb-free solder joints. These results seem to confirm the findings that have been reported previously by some researchers on the migration of a failure mode from the ductile fracture in the bulk solder to the brittle fracture of the intermetallic compound (IMC) layer due to the positive correlation between the tensile strength of the solder joint and the strain rate which may have occurred from high level of vibration and shock during the test. The generated data points were then compared to the existing S-N (stress-life) fatigue curves for the SAC305 solder joints in order to assess whether these curves can provide adequate results for the test vehicles fatigue life calculations. These preliminary results show that more work is needed in both verifying the effect of a failure mode migration in the solder joints as well as developing additional data points for S-N curve generation. This research is a continuation of the study initiated by the JEDEC JESD22 working group.
{"title":"Solder Joint Fatigue Studies Subjected to Board-level Random Vibration for Automotive Applications","authors":"Valeriy Khaldarov, Andy Zhang, Dongji Xie, J. Lee, Xue Shi, R. Roucou, S. Doranga, A. Shalumov","doi":"10.1109/ectc51906.2022.00280","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00280","url":null,"abstract":"In this paper, a simplified methodology is presented for the evaluation of test-to-failure board-level random vibrations using a combination of experimental and finite element modeling techniques in calculating equivalent stresses for SAC305 solder joints experiencing high- and ultra-high-cycle fatigue usually found in the emerging automotive robo-taxi industry. Some partial results that were obtained during this study allow for an investigation of the effects of a printed circuit board geometry on possible failure modes of Pb-free solder joints. These results seem to confirm the findings that have been reported previously by some researchers on the migration of a failure mode from the ductile fracture in the bulk solder to the brittle fracture of the intermetallic compound (IMC) layer due to the positive correlation between the tensile strength of the solder joint and the strain rate which may have occurred from high level of vibration and shock during the test. The generated data points were then compared to the existing S-N (stress-life) fatigue curves for the SAC305 solder joints in order to assess whether these curves can provide adequate results for the test vehicles fatigue life calculations. These preliminary results show that more work is needed in both verifying the effect of a failure mode migration in the solder joints as well as developing additional data points for S-N curve generation. This research is a continuation of the study initiated by the JEDEC JESD22 working group.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130330408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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