Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00207
Luke Prenger, Xavier Martinez, Andrea M. Chacko, Vikram Turkani, Lauren Reimnitz, V. Akhavan, K. Schroder
Advanced packaging technology has continuously evolved over the past 10-20 years to become a major driving force in improving integrated circuit (IC) performance. This improvement in IC performance is assisted by the ability to place specialized components near each other for shorter interconnects in the IC packages. Temporary bond and debond (TB/DB) is an enabling technique for this work. TB/DB facilitates many advanced packaging methods such as 2.5D, 3D-IC, fan-out wafer-level packaging (FOWLP), and system-in-package (SiP). All these architectures require a carrier support system to allow for backside processing of device wafers, including wafer thinning. A variety of TB/DB methods exist, such as thermal slide debond, mechanical debond, chemical release, and laser debond. Each of these methods has its own advantages and disadvantages and require proper material selection particular for each method.This paper describes a recently developed debond method called photonic debond. We compare this method with existing TB/DB methods and demonstrate the feasibility of this technique to process a wide range of devices. Additionally, the photonic debond method has a fundamentally different thermal load profile on the devices, enabling novel material selection. This is modeled in this paper.Photonic debond has transitioned from a manually operated debond method to an automated debond system. The new automated debond system enables higher wafer throughput as compared to the four existing debond methods. Advancements made with new debond system enables TB/DB from variety of device wafer sizes and types. Evaluation of debonding for wafers with device topography will be presented.
{"title":"Photonic Debond: Scalability and Advancements","authors":"Luke Prenger, Xavier Martinez, Andrea M. Chacko, Vikram Turkani, Lauren Reimnitz, V. Akhavan, K. Schroder","doi":"10.1109/ectc51906.2022.00207","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00207","url":null,"abstract":"Advanced packaging technology has continuously evolved over the past 10-20 years to become a major driving force in improving integrated circuit (IC) performance. This improvement in IC performance is assisted by the ability to place specialized components near each other for shorter interconnects in the IC packages. Temporary bond and debond (TB/DB) is an enabling technique for this work. TB/DB facilitates many advanced packaging methods such as 2.5D, 3D-IC, fan-out wafer-level packaging (FOWLP), and system-in-package (SiP). All these architectures require a carrier support system to allow for backside processing of device wafers, including wafer thinning. A variety of TB/DB methods exist, such as thermal slide debond, mechanical debond, chemical release, and laser debond. Each of these methods has its own advantages and disadvantages and require proper material selection particular for each method.This paper describes a recently developed debond method called photonic debond. We compare this method with existing TB/DB methods and demonstrate the feasibility of this technique to process a wide range of devices. Additionally, the photonic debond method has a fundamentally different thermal load profile on the devices, enabling novel material selection. This is modeled in this paper.Photonic debond has transitioned from a manually operated debond method to an automated debond system. The new automated debond system enables higher wafer throughput as compared to the four existing debond methods. Advancements made with new debond system enables TB/DB from variety of device wafer sizes and types. Evaluation of debonding for wafers with device topography will be presented.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115857704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00201
Vigneshwarram Kumaresan, M. Devarajan
Liquid thermal gap fillers play a vital role in dissipating heat from electronic components to enclosure surfaces. However, oil bleed from silicone-based liquid thermal gap filler causes contamination on enclosure substrates. It is essential to develop a non-oil bleed, thermally reliable thermal gap filler for solid state drive (SSD). In this work, a novel two-part thermal gap filler was synthesized. The long-term stability and reliability of thermal gap filler were evaluated using a highly accelerated temperature and humidity stress test (HAST). Thermal conductivity of cured thermal gap fillers were investigated before and after HAST. It was found that newly formulated thermal gap filler was stable even at high temperature and high humidity environments. Thus, the newly formulated thermal gap filler can effectively dissipate heat and enhance the performance and reliability of SSD.
{"title":"Non-oil bleed thermal gap fillers for long-term reliability of Solid State Drive","authors":"Vigneshwarram Kumaresan, M. Devarajan","doi":"10.1109/ectc51906.2022.00201","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00201","url":null,"abstract":"Liquid thermal gap fillers play a vital role in dissipating heat from electronic components to enclosure surfaces. However, oil bleed from silicone-based liquid thermal gap filler causes contamination on enclosure substrates. It is essential to develop a non-oil bleed, thermally reliable thermal gap filler for solid state drive (SSD). In this work, a novel two-part thermal gap filler was synthesized. The long-term stability and reliability of thermal gap filler were evaluated using a highly accelerated temperature and humidity stress test (HAST). Thermal conductivity of cured thermal gap fillers were investigated before and after HAST. It was found that newly formulated thermal gap filler was stable even at high temperature and high humidity environments. Thus, the newly formulated thermal gap filler can effectively dissipate heat and enhance the performance and reliability of SSD.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116073911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00206
Zhijian Sun, Michael Yu, Jiaxiong Li, Macleary Moran, M. Kathaperumal, K. Moon, Madhavan Swaminathan, C. Wong
Recent advances in two-dimensional (2D) nanomaterials have generated great interest in the investigations of these materials for wide ranging applications in the micro-to nano-scale electronics, healthcare, and energy storage areas. In particular, 2D materialas such as boron nitride nanosheets (BNNS) have been studied extensively due to their unique material properties that include a large specific surface area, high thermal conductivity (~750 W/mK), and wide bandgap (~5.5 eV), along with the associated electrical insulation. In this paper, we prepared BNNS by liquid exfoliation of hexagonal boron nitride (h-BN). Liquid exfoliation is an enhanced method to achieve large-scale and low-cost production, which is more suitable for large volume applications. In this paper, we have combined low-energy ball milling and sonication methods to produce BNNS on a large scale.BNNS have a high in-plane thermal conductivity due to their 2D morphology but a lower through-plane thermal conductivity. Also, the thermal interface resistance between BNNS is also an important factor that impedes the through-plane thermal conductivity. Thus, we employed a vacuum filtration method to obtain thick BNNS cakes. These cakes have a high x-y/in-plane thermal conductivity and a low z/through plane thermal conductivity. After slicing the cake vertically, it is rolled over to covert the strong x-y plane thermal conductivity to the z-plane. The now high thermal conductivity z-plane allows for effective 3D electronic packaging. Following this, BNNS are infiltrated into epoxy resins to fabricate epoxy nanocomposites with a low filler loading. This paper presents detailed studies on the coefficient of thermal expansion (CTE), electrical resistivity, thermal stability, and thermomechanical properties of the synthesized BNNS-epoxy nanocomposites. This study reveals the promising applications of high performance, thermally conductive epoxy nanocomposites in advanced packaging technologies such as 2.5D/ 3D packaging.
{"title":"Large-scale production of boron nitride nanosheets-based epoxy nanocomposites with ultrahigh through-plane thermal conductivity for electronic encapsulation","authors":"Zhijian Sun, Michael Yu, Jiaxiong Li, Macleary Moran, M. Kathaperumal, K. Moon, Madhavan Swaminathan, C. Wong","doi":"10.1109/ectc51906.2022.00206","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00206","url":null,"abstract":"Recent advances in two-dimensional (2D) nanomaterials have generated great interest in the investigations of these materials for wide ranging applications in the micro-to nano-scale electronics, healthcare, and energy storage areas. In particular, 2D materialas such as boron nitride nanosheets (BNNS) have been studied extensively due to their unique material properties that include a large specific surface area, high thermal conductivity (~750 W/mK), and wide bandgap (~5.5 eV), along with the associated electrical insulation. In this paper, we prepared BNNS by liquid exfoliation of hexagonal boron nitride (h-BN). Liquid exfoliation is an enhanced method to achieve large-scale and low-cost production, which is more suitable for large volume applications. In this paper, we have combined low-energy ball milling and sonication methods to produce BNNS on a large scale.BNNS have a high in-plane thermal conductivity due to their 2D morphology but a lower through-plane thermal conductivity. Also, the thermal interface resistance between BNNS is also an important factor that impedes the through-plane thermal conductivity. Thus, we employed a vacuum filtration method to obtain thick BNNS cakes. These cakes have a high x-y/in-plane thermal conductivity and a low z/through plane thermal conductivity. After slicing the cake vertically, it is rolled over to covert the strong x-y plane thermal conductivity to the z-plane. The now high thermal conductivity z-plane allows for effective 3D electronic packaging. Following this, BNNS are infiltrated into epoxy resins to fabricate epoxy nanocomposites with a low filler loading. This paper presents detailed studies on the coefficient of thermal expansion (CTE), electrical resistivity, thermal stability, and thermomechanical properties of the synthesized BNNS-epoxy nanocomposites. This study reveals the promising applications of high performance, thermally conductive epoxy nanocomposites in advanced packaging technologies such as 2.5D/ 3D packaging.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115391570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00069
Xiaofan Jia, Xingchen Li, K. Moon, Joon Woo Kim, Kai-Qi Huang, M. Jordan, Madhavan Swaminathan
This work presents the implementation and characterization of a die-embedded, antenna-integrated glass package for RF modules in D-Band. The proposed package uses glass as the core material which can match the coefficient-of-thermal-expansion (CTE) well for RF chips and printed circuit board (PCB). The redistribution layer (RDL) for electrical connections is built on low-loss polymeric build-up dielectric films (ABF-GL102). Dummy dies are embedded in the glass cavities for characterization. The interconnects between die pads and the package are implemented using micro-vias. An 8-elements series-fed microstrip patch antenna is also integrated on the low-loss RDL. The proposed glass panel embedded package addresses the electrical loss and parasitic from the interconnects. With micro-vias and transmission lines built on low-loss RDL, the glass embedded package provides low-loss and low-parasitic chip-to-chip and chip-to-antenna interconnects. Using temporary thermal release tapes, this package also shows great potential to address the high heat dissipation from D-band power amplifiers.
{"title":"Antenna-Integrated, Die-Embedded Glass Package for 6G Wireless Applications","authors":"Xiaofan Jia, Xingchen Li, K. Moon, Joon Woo Kim, Kai-Qi Huang, M. Jordan, Madhavan Swaminathan","doi":"10.1109/ectc51906.2022.00069","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00069","url":null,"abstract":"This work presents the implementation and characterization of a die-embedded, antenna-integrated glass package for RF modules in D-Band. The proposed package uses glass as the core material which can match the coefficient-of-thermal-expansion (CTE) well for RF chips and printed circuit board (PCB). The redistribution layer (RDL) for electrical connections is built on low-loss polymeric build-up dielectric films (ABF-GL102). Dummy dies are embedded in the glass cavities for characterization. The interconnects between die pads and the package are implemented using micro-vias. An 8-elements series-fed microstrip patch antenna is also integrated on the low-loss RDL. The proposed glass panel embedded package addresses the electrical loss and parasitic from the interconnects. With micro-vias and transmission lines built on low-loss RDL, the glass embedded package provides low-loss and low-parasitic chip-to-chip and chip-to-antenna interconnects. Using temporary thermal release tapes, this package also shows great potential to address the high heat dissipation from D-band power amplifiers.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123173463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00044
Rishav Roy, Shidhartha Das, Benoît Labbé, R. Mathur, Supreet Jeloka
The stacking of multiple dies to create 3D ICs has offered an attractive avenue to counter the slowing of Moore’s law. Stacking dies, however, leads to increased power densities that require effective heat extraction mechanisms. In this work, we perform thermal simulations to study the impact of stacking dies. The package is subject to air-based and liquid-based cooling solutions, under significantly different heat transfer coefficients. A case study is performed on a many-core 3D system to investigate the thermal impact of introducing dedicated low dropout regulators (LDOs) in 3D ICs. These LDOs enable percore dynamic voltage and frequency scaling (DVFS) for efficient power management but potentially add thermal hot spots. We also study the transient thermal behavior of a package subject to different cooling solutions, providing guidelines for thermal throttling. This study demonstrates that system architecture design guided by thermal considerations can effectively utilize the power management efficiencies of 3D ICs without exceeding thermal limits.
{"title":"Co-design of Thermal Management with System Architecture and Power Management for 3D ICs","authors":"Rishav Roy, Shidhartha Das, Benoît Labbé, R. Mathur, Supreet Jeloka","doi":"10.1109/ectc51906.2022.00044","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00044","url":null,"abstract":"The stacking of multiple dies to create 3D ICs has offered an attractive avenue to counter the slowing of Moore’s law. Stacking dies, however, leads to increased power densities that require effective heat extraction mechanisms. In this work, we perform thermal simulations to study the impact of stacking dies. The package is subject to air-based and liquid-based cooling solutions, under significantly different heat transfer coefficients. A case study is performed on a many-core 3D system to investigate the thermal impact of introducing dedicated low dropout regulators (LDOs) in 3D ICs. These LDOs enable percore dynamic voltage and frequency scaling (DVFS) for efficient power management but potentially add thermal hot spots. We also study the transient thermal behavior of a package subject to different cooling solutions, providing guidelines for thermal throttling. This study demonstrates that system architecture design guided by thermal considerations can effectively utilize the power management efficiencies of 3D ICs without exceeding thermal limits.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124850473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00232
L. Yip, Rosa Lin, C.W. Lai, C. Peng
As the cost of advanced silicon nodes continue to rise, high-performance devices are shifting towards advanced packaging to reduce the overall cost, increase functionality, and improve performance. Fan-out packaging technology is an advanced packaging approach that has increasingly been adopted for networking, artificial intelligence, and high-performance computing (HPC) applications. Fan-out technology enables multi-chip integration using fine pitch and small line width copper redistribution layer (RDL) technology to interconnect different dies resulting in a flexible and cost-effective package solution. However, as the fan-out package size increases to accommodate higher I/O counts and higher bandwidth, package warpage and reliability become more challenging. The main challenges in building large size packages (ı65x65mm2) with fan-out technology are warpage, RDL integrity, and package reliability. In this paper, we discuss the reliability assessment of a 1.6X reticle size integrated fan-out multi-chip assembly on large organic substrates for networking applications. The package integrates a 7 nm ASIC die and 8 I/O chiplets with 3 layers of fine-pitch RDL interconnection. The coefficient of thermal expansion (CTE) mismatch between different materials in the package structure can cause the device to warp and induce mechanical stresses that can cause RDL cracking and other failures in the package. We will discuss package design and processing methods for improving RDL integrity to enhance overall package reliability. By using finite element stress analysis to optimize the RDL design, robust large format multi-chip fan-out packages were developed and validated through reliability testing.
{"title":"Reliability Challenges of High-Density Fan-out Packaging for High-Performance Computing Applications","authors":"L. Yip, Rosa Lin, C.W. Lai, C. Peng","doi":"10.1109/ectc51906.2022.00232","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00232","url":null,"abstract":"As the cost of advanced silicon nodes continue to rise, high-performance devices are shifting towards advanced packaging to reduce the overall cost, increase functionality, and improve performance. Fan-out packaging technology is an advanced packaging approach that has increasingly been adopted for networking, artificial intelligence, and high-performance computing (HPC) applications. Fan-out technology enables multi-chip integration using fine pitch and small line width copper redistribution layer (RDL) technology to interconnect different dies resulting in a flexible and cost-effective package solution. However, as the fan-out package size increases to accommodate higher I/O counts and higher bandwidth, package warpage and reliability become more challenging. The main challenges in building large size packages (ı65x65mm2) with fan-out technology are warpage, RDL integrity, and package reliability. In this paper, we discuss the reliability assessment of a 1.6X reticle size integrated fan-out multi-chip assembly on large organic substrates for networking applications. The package integrates a 7 nm ASIC die and 8 I/O chiplets with 3 layers of fine-pitch RDL interconnection. The coefficient of thermal expansion (CTE) mismatch between different materials in the package structure can cause the device to warp and induce mechanical stresses that can cause RDL cracking and other failures in the package. We will discuss package design and processing methods for improving RDL integrity to enhance overall package reliability. By using finite element stress analysis to optimize the RDL design, robust large format multi-chip fan-out packages were developed and validated through reliability testing.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00338
F. Libsch, H. Mori, X. Gu
The focus of this work encompasses signal integrity (SI) design and analysis in hybrid integration of the latest generation of High Bandwidth Memory (HBM2E) onto the latest generation high density Organic Package now capable of 1.5um line and space interconnects. In this paper, for the first time, we design and analyze the whole system HBM2E link budget components on latest generation high density Organic Package where the methodology details all the interconnect signal uncertainties.
{"title":"Signal Integrity Design and Analysis with Link Budget Results of HBM2E Module on Latest High Density Organic Laminate","authors":"F. Libsch, H. Mori, X. Gu","doi":"10.1109/ectc51906.2022.00338","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00338","url":null,"abstract":"The focus of this work encompasses signal integrity (SI) design and analysis in hybrid integration of the latest generation of High Bandwidth Memory (HBM2E) onto the latest generation high density Organic Package now capable of 1.5um line and space interconnects. In this paper, for the first time, we design and analyze the whole system HBM2E link budget components on latest generation high density Organic Package where the methodology details all the interconnect signal uncertainties.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126541615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00067
N. P. Gaunkar, G. Dogiamis, T. Kamgaing, A. Elsherbini, J. Swan
A multi-layer, organic, low-loss flip-chip chip-scale package (FCCSP) for sub-THz applications has been developed and validated with on-package passive structures operating in the frequency band of 100 GHz to 140 GHz. The designed package co-integrates an electromagnetic wave launcher, a dual band multiplexer and a wideband through package transition. The wave launcher includes two rectangular patches separated by dielectric layers and supports a radiation bandwidth of 40 GHz. It has a return loss better than 10 dB in the designed bandwidth and an insertion loss between 1 to 1.5 dB. The on-package multiplexer (diplexer) combines two bandpass hairpin resonator filters. The two filters are designed to have a minimum bandwidth of 12 GHz each. The designed diplexer also has a return loss better than 10 dB and an insertion loss between 4 to 5 dB. Our work is a leading demonstrator for FCCSP packaging in the 100 to 140 GHz frequency range. We show that with the current fabrication processes, organic packaging is a valuable low-loss solution for sub-THz millimeter wave applications.
{"title":"Multi-layer FCCSP organic packaging for D-band millimeter wave applications","authors":"N. P. Gaunkar, G. Dogiamis, T. Kamgaing, A. Elsherbini, J. Swan","doi":"10.1109/ectc51906.2022.00067","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00067","url":null,"abstract":"A multi-layer, organic, low-loss flip-chip chip-scale package (FCCSP) for sub-THz applications has been developed and validated with on-package passive structures operating in the frequency band of 100 GHz to 140 GHz. The designed package co-integrates an electromagnetic wave launcher, a dual band multiplexer and a wideband through package transition. The wave launcher includes two rectangular patches separated by dielectric layers and supports a radiation bandwidth of 40 GHz. It has a return loss better than 10 dB in the designed bandwidth and an insertion loss between 1 to 1.5 dB. The on-package multiplexer (diplexer) combines two bandpass hairpin resonator filters. The two filters are designed to have a minimum bandwidth of 12 GHz each. The designed diplexer also has a return loss better than 10 dB and an insertion loss between 4 to 5 dB. Our work is a leading demonstrator for FCCSP packaging in the 100 to 140 GHz frequency range. We show that with the current fabrication processes, organic packaging is a valuable low-loss solution for sub-THz millimeter wave applications.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129861446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00349
L. Wai, Kazunori Yamamoto, G. Tang, Jacob Jordon Soh
The process development of a novel pressure-assist pates for high performance silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) was carried out. In this study, high shear strength on silver sintered die attach layer can be achieved. Interconnect process developed for gate pad (pad size = 0.8mm x 0.5mm) and source pad (pad size= 1.04mmx3.97mm) with copper clips and tin antimony (SnSb) solder passed the criteria of power cycling test. Highly densify silver sintered layer can be achieved by pressure-laser sintering process for pressure-assist type silver sintering paste.
{"title":"Pressure-assist Silver Sintering Paste for SiC Power Device Attachment on Lead Frame Based Package","authors":"L. Wai, Kazunori Yamamoto, G. Tang, Jacob Jordon Soh","doi":"10.1109/ectc51906.2022.00349","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00349","url":null,"abstract":"The process development of a novel pressure-assist pates for high performance silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) was carried out. In this study, high shear strength on silver sintered die attach layer can be achieved. Interconnect process developed for gate pad (pad size = 0.8mm x 0.5mm) and source pad (pad size= 1.04mmx3.97mm) with copper clips and tin antimony (SnSb) solder passed the criteria of power cycling test. Highly densify silver sintered layer can be achieved by pressure-laser sintering process for pressure-assist type silver sintering paste.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00150
Yihang Chu, Yamini Kotriwar, Ethan Kepros, Brian Wright, P. Chahal
This paper investigates the use of additive manufacturing (AM) for the fabrication of hollow or air substrate integrated waveguides (SIW or reduced height waveguides). The method relies on additive manufacturing (3-D fabrication) using a simple resin printer. A bandpass filter and a slot antenna working in the X-band are demonstrated. The simulation and measured results match closely and show that low-cost table top resin printers can fabricate microwave passive components with good performance.
{"title":"X-band Passive Circuits Using 3-D Printed Hollow Substrate Integrated Waveguides","authors":"Yihang Chu, Yamini Kotriwar, Ethan Kepros, Brian Wright, P. Chahal","doi":"10.1109/ectc51906.2022.00150","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00150","url":null,"abstract":"This paper investigates the use of additive manufacturing (AM) for the fabrication of hollow or air substrate integrated waveguides (SIW or reduced height waveguides). The method relies on additive manufacturing (3-D fabrication) using a simple resin printer. A bandpass filter and a slot antenna working in the X-band are demonstrated. The simulation and measured results match closely and show that low-cost table top resin printers can fabricate microwave passive components with good performance.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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