Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508290
Vladimir Kopta, D. Barras, C. Enz
A low-power FM-UWB receiver intended for short range communications in wireless sensor networks is presented in this paper. It utilizes an “approximate zero IF” architecture which combines a free-running ring oscillator as the RF LO with a modified delay-line demodulator. The main benefit comes from implementing the gain stages and the demodulator at the IF instead of RF, allowing significant power savings. Integrated in a 65nm CMOS technology, the whole receiver chain consumes 420μW from a 1V supply while achieving -68dBm sensitivity at the data rate of 100 kb/s.
{"title":"A 420µW, 4 GHz approximate zero IF FM-UWB receiver for short-range communications","authors":"Vladimir Kopta, D. Barras, C. Enz","doi":"10.1109/RFIC.2016.7508290","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508290","url":null,"abstract":"A low-power FM-UWB receiver intended for short range communications in wireless sensor networks is presented in this paper. It utilizes an “approximate zero IF” architecture which combines a free-running ring oscillator as the RF LO with a modified delay-line demodulator. The main benefit comes from implementing the gain stages and the demodulator at the IF instead of RF, allowing significant power savings. Integrated in a 65nm CMOS technology, the whole receiver chain consumes 420μW from a 1V supply while achieving -68dBm sensitivity at the data rate of 100 kb/s.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123819416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508304
Paria Sepidband, K. Entesari
Real time spectrum sensing can be useful for cognitive radio (CR) devices to detect primary signals without the need for a receiver, reducing complexity and false detection. In this paper, an integrated CMOS real time CR spectrum sensor in 57-354 MHz frequency band with a new integrable phaser is presented, which is the first real time spectrum sensor applicable to radio frequency integrated circuit (RFIC) area. The integrated chip has been fabricated in a standard 0.18 μm CMOS IBM technology and draws 11 mA from a 1.8 V supply voltage.
{"title":"A phaser-based real-time CMOS spectrum sensor for cognitive radios","authors":"Paria Sepidband, K. Entesari","doi":"10.1109/RFIC.2016.7508304","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508304","url":null,"abstract":"Real time spectrum sensing can be useful for cognitive radio (CR) devices to detect primary signals without the need for a receiver, reducing complexity and false detection. In this paper, an integrated CMOS real time CR spectrum sensor in 57-354 MHz frequency band with a new integrable phaser is presented, which is the first real time spectrum sensor applicable to radio frequency integrated circuit (RFIC) area. The integrated chip has been fabricated in a standard 0.18 μm CMOS IBM technology and draws 11 mA from a 1.8 V supply voltage.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116671904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508236
Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, T. Iizuka, T. Nakura, K. Asada
This paper presents a pulse generator (PG), aiming at low power applications with low duty cycle. The PG is capable to provide an efficient pulse generation at a frequency near and beyond CMOS's Fmax. It also features quick starting time and zero stand-by power. The PG is designed by CMOS flipped to a transmission line resonator on a quartz substrate. Efficiency, oscillation frequency and pulse duration can be tuned by adjusting the transmission line parameters. Two prototypes with coupling gap of 1μm and 2μm at 11.5GHz oscillation frequency are fabricated. Measurement shows energy conversion efficiency of 2.37% and 2.05%, respectively, with energy consumption of 5.4pJ/pulse.
{"title":"Analysis and implementation of quick-start pulse generator by CMOS flipped on quartz substrate","authors":"Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, T. Iizuka, T. Nakura, K. Asada","doi":"10.1109/RFIC.2016.7508236","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508236","url":null,"abstract":"This paper presents a pulse generator (PG), aiming at low power applications with low duty cycle. The PG is capable to provide an efficient pulse generation at a frequency near and beyond CMOS's Fmax. It also features quick starting time and zero stand-by power. The PG is designed by CMOS flipped to a transmission line resonator on a quartz substrate. Efficiency, oscillation frequency and pulse duration can be tuned by adjusting the transmission line parameters. Two prototypes with coupling gap of 1μm and 2μm at 11.5GHz oscillation frequency are fabricated. Measurement shows energy conversion efficiency of 2.37% and 2.05%, respectively, with energy consumption of 5.4pJ/pulse.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129724339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A mode-configurable filtering ΔΣ ADC is utilized as the analog baseband in a Wi-Fi 11ac direct-conversion receiver (RX). The filtering ΔΣ ADC providing both 2nd-order out-of-band filtering and 3rd-order in-band noise shaping is realized with only two opamps. A SAR-quantizer with built-in discrete-time (DT) excess-loop delay (ELD) compensation technique is also adopted. The filtering ΔΣ ADC is clocked at 480 MHz or 960 MHz and achieves 77-to-58 dB dynamic range (DR) in 10 MHz - 80 MHz bandwidth. With the aid of the filtering ability, the interferer DR at 4× bandwidth is at least 71.3 dB over modes. This work is fabricated in 28-nm low-power (LP) technology with 0.06 mm2 of active area. It consumes 3.97 mW or 6.39 mW over different clock rates, resulting a highest Schreier's FoM of 171 dB (BW20) and a best 4×-bandwidth Walden's FoM [2] of 13.3 fJ/c (BW160) among all modes.
{"title":"A mode-configurable analog baseband for Wi-Fi 11ac direct-conversion receiver utilizing a single filtering ΔΣ ADC","authors":"Chi-Yun Wang, Shu-Wei Chu, Tzu-Hsuin Peng, Jen-Che Tsai, Chih-Hong Lou","doi":"10.1109/RFIC.2016.7508278","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508278","url":null,"abstract":"A mode-configurable filtering ΔΣ ADC is utilized as the analog baseband in a Wi-Fi 11ac direct-conversion receiver (RX). The filtering ΔΣ ADC providing both 2nd-order out-of-band filtering and 3rd-order in-band noise shaping is realized with only two opamps. A SAR-quantizer with built-in discrete-time (DT) excess-loop delay (ELD) compensation technique is also adopted. The filtering ΔΣ ADC is clocked at 480 MHz or 960 MHz and achieves 77-to-58 dB dynamic range (DR) in 10 MHz - 80 MHz bandwidth. With the aid of the filtering ability, the interferer DR at 4× bandwidth is at least 71.3 dB over modes. This work is fabricated in 28-nm low-power (LP) technology with 0.06 mm2 of active area. It consumes 3.97 mW or 6.39 mW over different clock rates, resulting a highest Schreier's FoM of 171 dB (BW20) and a best 4×-bandwidth Walden's FoM [2] of 13.3 fJ/c (BW160) among all modes.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128944179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508325
Yi-Shin Yeh, B. Walker, E. Balboni, B. Floyd
This paper presents a 28-GHz four-channel phased-array receiver in 120-nm SiGe BiCMOS technology for 5G cellular application. The phased-array receiver employs scalar-only weighting functions within each front-end and then global quadrature power combining to realize beamforming. Differential LNAs and dual-vector variable-gain amplifiers are used to realize each front-end with compact area. Each front-end achieves 5.1 to 7 dB noise figure, -16.8 to -13.8 dBm input compression point, -10.5 to -8.9 dBm input third-order intercept point across 4-bit phase settings and a 3-dB bandwidth of 26.5 to 33.9GHz, while consuming 136 mW per element. RMS gain and phase errors are <; 0.6 dB and <; 5.4° at 28-32 GHz respectively, and all four elements reveal well-matched responses.
{"title":"A 28-GHz 4-channel dual-vector receiver phased array in SiGe BiCMOS technology","authors":"Yi-Shin Yeh, B. Walker, E. Balboni, B. Floyd","doi":"10.1109/RFIC.2016.7508325","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508325","url":null,"abstract":"This paper presents a 28-GHz four-channel phased-array receiver in 120-nm SiGe BiCMOS technology for 5G cellular application. The phased-array receiver employs scalar-only weighting functions within each front-end and then global quadrature power combining to realize beamforming. Differential LNAs and dual-vector variable-gain amplifiers are used to realize each front-end with compact area. Each front-end achieves 5.1 to 7 dB noise figure, -16.8 to -13.8 dBm input compression point, -10.5 to -8.9 dBm input third-order intercept point across 4-bit phase settings and a 3-dB bandwidth of 26.5 to 33.9GHz, while consuming 136 mW per element. RMS gain and phase errors are <; 0.6 dB and <; 5.4° at 28-32 GHz respectively, and all four elements reveal well-matched responses.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134213535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508323
Charley Wilson, B. Floyd
A 20-30 GHz mixer-first receiver implemented in 45-nm SOI CMOS is presented. The receiver employs four-phase passive mixing with input inductor to realize tunable impedance matching up to 30 GHz. The receiver achieves an 8-dB noise figure with reconfigurable 8.9 to 20.6-dB conversion gain and 2:1 impedance tuning range. Input 1-dB compression point ranges from -13 to -9.3 dBm and power consumption is 41 mW.
提出了一种采用45nm SOI CMOS实现的20- 30ghz混频器优先接收器。接收机采用四相无源混频和输入电感，实现阻抗匹配可调，最高可达30ghz。该接收机达到8 db噪声系数，可重构8.9至20.6 db转换增益和2:1阻抗调谐范围。输入1db压缩点范围为-13 ~ -9.3 dBm，功耗为41mw。
{"title":"20–30 GHz mixer-first receiver in 45-nm SOI CMOS","authors":"Charley Wilson, B. Floyd","doi":"10.1109/RFIC.2016.7508323","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508323","url":null,"abstract":"A 20-30 GHz mixer-first receiver implemented in 45-nm SOI CMOS is presented. The receiver employs four-phase passive mixing with input inductor to realize tunable impedance matching up to 30 GHz. The receiver achieves an 8-dB noise figure with reconfigurable 8.9 to 20.6-dB conversion gain and 2:1 impedance tuning range. Input 1-dB compression point ranges from -13 to -9.3 dBm and power consumption is 41 mW.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133665256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508320
Dong Yang, H. Yuksel, Christopher Newman, Changhyuk Lee, Zachariah Boynton, N. Paya, Miles Pedrone, A. Apsel, A. Molnar
An ideal Software Defined Radio (SDR) requires a reconfigurable, intergrated, widely-frequency-tunable transceiver able to support different RX/TX duplex schemes. Here we present an integrated transceiver capable of supporting both TDD and FDD operation with >25dB integrated RX-TX isolation from 0.3-1.6GHz without any off-chip switches or filters. The transceiver uses an artificial transmission line (TL) and distributed PA to separate TX and RX. TX noise in the RX band is further suppressed by >13dB an RX-tracking PA degeneration circuit.
{"title":"A fully integrated Software-Defined FDD transceiver tunable from 0.3-to-1.6 GHz","authors":"Dong Yang, H. Yuksel, Christopher Newman, Changhyuk Lee, Zachariah Boynton, N. Paya, Miles Pedrone, A. Apsel, A. Molnar","doi":"10.1109/RFIC.2016.7508320","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508320","url":null,"abstract":"An ideal Software Defined Radio (SDR) requires a reconfigurable, intergrated, widely-frequency-tunable transceiver able to support different RX/TX duplex schemes. Here we present an integrated transceiver capable of supporting both TDD and FDD operation with >25dB integrated RX-TX isolation from 0.3-1.6GHz without any off-chip switches or filters. The transceiver uses an artificial transmission line (TL) and distributed PA to separate TX and RX. TX noise in the RX band is further suppressed by >13dB an RX-tracking PA degeneration circuit.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134174111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508272
S. Ayati, Debashis Mandal, B. Bakkaloglu, S. Kiaei
An adaptive circulator fabricated on a 130 nm CMOS is presented. Circulator has two adaptive blocks for gain and phase mismatch correction and leakage cancelation. The impedance matching circuit corrects mismatches for antenna, divider, and LNTA. The cancelation block cancels the Tx leakage. Measured isolation between transmitter and receiver for single tone at 2.4 GHz is 90 dB, and for a 40 MHz wide-band signal is 50dB. The circulator Rx gain is 10 dB, with NF = 4.7 dB and 5 dB insertion loss.
{"title":"Adaptive integrated CMOS circulator","authors":"S. Ayati, Debashis Mandal, B. Bakkaloglu, S. Kiaei","doi":"10.1109/RFIC.2016.7508272","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508272","url":null,"abstract":"An adaptive circulator fabricated on a 130 nm CMOS is presented. Circulator has two adaptive blocks for gain and phase mismatch correction and leakage cancelation. The impedance matching circuit corrects mismatches for antenna, divider, and LNTA. The cancelation block cancels the Tx leakage. Measured isolation between transmitter and receiver for single tone at 2.4 GHz is 90 dB, and for a 40 MHz wide-band signal is 50dB. The circulator Rx gain is 10 dB, with NF = 4.7 dB and 5 dB insertion loss.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131297778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508245
V. Vanukuru
This paper describes an efficient implementation of a lumped millimeter(mm)-wave narrow bandpass filter at 60 GHz. The mm-wave filter uses layout optimized conical spiral inductors which are shown to have higher quality factor (Q) and self resonant frequency values than standard spiral inductors. The filter also uses interdigital metal-oxide-metal capacitors which are shown to have Q values than nitride metal-insulator-metal (MIM) capacitors at these high frequencies. The filter is fabricated in 0.18 μm high resistivity RF silicon-on-insulator CMOS technology. The filter has a center frequency of 60 GHz and 3 dB bandwidth of 8 GHz, with a fractional bandwidth of 13.3% and a loaded Q of 7.5 occupying an area of (150×215)μm2. Monte-carlo simulations of the filter demonstrate excellent robustness against process variations due to usage of only two top thick metals and exclusion of MIM capacitors.
{"title":"Millimeter-wave bandpass filter using high-Q conical inductors and MOM capacitors","authors":"V. Vanukuru","doi":"10.1109/RFIC.2016.7508245","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508245","url":null,"abstract":"This paper describes an efficient implementation of a lumped millimeter(mm)-wave narrow bandpass filter at 60 GHz. The mm-wave filter uses layout optimized conical spiral inductors which are shown to have higher quality factor (Q) and self resonant frequency values than standard spiral inductors. The filter also uses interdigital metal-oxide-metal capacitors which are shown to have Q values than nitride metal-insulator-metal (MIM) capacitors at these high frequencies. The filter is fabricated in 0.18 μm high resistivity RF silicon-on-insulator CMOS technology. The filter has a center frequency of 60 GHz and 3 dB bandwidth of 8 GHz, with a fractional bandwidth of 13.3% and a loaded Q of 7.5 occupying an area of (150×215)μm2. Monte-carlo simulations of the filter demonstrate excellent robustness against process variations due to usage of only two top thick metals and exclusion of MIM capacitors.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114596452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508316
F. Balteanu
This paper presents a 2.3GHz - 2.7GHz broadband CMOS FDD/TDD LTE Band 7. 38, 40 and 41 power amplifier (PA) fully integrated with a fast envelope tracker (ET) on a single 0.18μm CMOS die. The PA and the tracker achieve a 37% overall efficiency for 26.5dBm and -39dBc ACLR1. The entire design including the input/output match uses an active silicon area around 2.7mm2.
本文提出了一种2.3GHz - 2.7GHz宽带CMOS FDD/TDD LTE Band 7。38、40和41功率放大器(PA)与快速包络跟踪器(ET)完全集成在单个0.18μm CMOS芯片上。PA和跟踪器在26.5dBm和-39dBc ACLR1下实现37%的总效率。整个设计包括输入/输出匹配使用约2.7mm2的有源硅面积。
{"title":"Single die broadband CMOS power amplifier and tracker with 37% overall efficiency for TDD/FDD LTE applications","authors":"F. Balteanu","doi":"10.1109/RFIC.2016.7508316","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508316","url":null,"abstract":"This paper presents a 2.3GHz - 2.7GHz broadband CMOS FDD/TDD LTE Band 7. 38, 40 and 41 power amplifier (PA) fully integrated with a fast envelope tracker (ET) on a single 0.18μm CMOS die. The PA and the tracker achieve a 37% overall efficiency for 26.5dBm and -39dBc ACLR1. The entire design including the input/output match uses an active silicon area around 2.7mm2.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121418325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：