M. Akata, Y. Nagataki, K. Koyabu, K. Mukai, S. Yoshida, I. Ueki
A subscriber line interface circuit (SLIC) two-chip set is presented. It eliminates off-chip function trimming and contains integrated coin telephone set facilities and BORSCHT functions. The set consists of: (a) the subscriber interface LSI, a 320-V dielectrically isolated bipolar LSI with on-chip thin-film resistors and double-layer metal; and (b) the subscriber processor LSI, a 1.6 μm CMOS LSI with oversampling A-D/D-A converters and a microprogrammable digital signal processor. The chip sizes are 5.5 mm×6.06 mm and 6.0 mm×5.7 mm, respectively. With the two-chip set, a SLIC for coin telephone set interface can be established without high-precision filter components or hybrid ICs with their function trimming
{"title":"A no-trimming SLIC two-chip set with coin telephone signaling facilities","authors":"M. Akata, Y. Nagataki, K. Koyabu, K. Mukai, S. Yoshida, I. Ueki","doi":"10.1109/CICC.1989.56771","DOIUrl":"https://doi.org/10.1109/CICC.1989.56771","url":null,"abstract":"A subscriber line interface circuit (SLIC) two-chip set is presented. It eliminates off-chip function trimming and contains integrated coin telephone set facilities and BORSCHT functions. The set consists of: (a) the subscriber interface LSI, a 320-V dielectrically isolated bipolar LSI with on-chip thin-film resistors and double-layer metal; and (b) the subscriber processor LSI, a 1.6 μm CMOS LSI with oversampling A-D/D-A converters and a microprogrammable digital signal processor. The chip sizes are 5.5 mm×6.06 mm and 6.0 mm×5.7 mm, respectively. With the two-chip set, a SLIC for coin telephone set interface can be established without high-precision filter components or hybrid ICs with their function trimming","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"61 27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121457787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of CHARM, a chip-architecture planning tool for digital VLSI. From a behavioral description on the algorithmic level, a structural strip-architecture plan is synthesized. It uses a knowledge-based approach that incorporates heuristics and experience from industrial designers into the system. This is done by modeling the various chip-architecture principles using generic objects called schemes, which are instantiated during the design process. Evaluation is done by heuristic quality functions to determine the best-suited architecture. A blackboard architecture is an adequate structure for the prototype expert system. The quality of this expert system heavily depends on the success of the knowledge acquisition from experienced VLSI designers. A simplified design example is given
{"title":"CHARM: a synthesis tool for high-level chip-architecture planning","authors":"Karl-Heinz Temme","doi":"10.1109/CICC.1989.56684","DOIUrl":"https://doi.org/10.1109/CICC.1989.56684","url":null,"abstract":"A description is given of CHARM, a chip-architecture planning tool for digital VLSI. From a behavioral description on the algorithmic level, a structural strip-architecture plan is synthesized. It uses a knowledge-based approach that incorporates heuristics and experience from industrial designers into the system. This is done by modeling the various chip-architecture principles using generic objects called schemes, which are instantiated during the design process. Evaluation is done by heuristic quality functions to determine the best-suited architecture. A blackboard architecture is an adequate structure for the prototype expert system. The quality of this expert system heavily depends on the success of the knowledge acquisition from experienced VLSI designers. A simplified design example is given","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116015939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Robert Skruhak, M. McDermott, C. Wiseman, M. Taborn, J. J. Vaglica, E. Carter
A 32-bit microcontroller the MC68332 has been fabricated using a macro-module design approach. This permitted early fabrication and evaluation of the modules as the designs were completed. Interface to the modules was achieved by a common bus interface, which was accessible externally for testing
{"title":"Modular design of a high performance 32-bit microcontroller","authors":"Robert Skruhak, M. McDermott, C. Wiseman, M. Taborn, J. J. Vaglica, E. Carter","doi":"10.1109/CICC.1989.56821","DOIUrl":"https://doi.org/10.1109/CICC.1989.56821","url":null,"abstract":"A 32-bit microcontroller the MC68332 has been fabricated using a macro-module design approach. This permitted early fabrication and evaluation of the modules as the designs were completed. Interface to the modules was achieved by a common bus interface, which was accessible externally for testing","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116225813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The significance, requirements, and potential of an integrated tool for the evaluation of simulation results in VLSI design are discussed. Results and solutions developed for a simulation evaluation tool called SIMUEVA are stated and exemplified. Particular aspects considered are proper modeling of simulation result data, a UPN set calculator for extraction of goal-directed excerpts, validation by automatic comparison, inclusion of hardware structure descriptions into the evaluation process, examples of automatic fault location, and interaction of evaluation and other VLSI design tools are stated and exemplified
{"title":"An approach to understanding evaluation of simulation results as an integrated task","authors":"R. Buschke, K. Lagemann","doi":"10.1109/CICC.1989.56750","DOIUrl":"https://doi.org/10.1109/CICC.1989.56750","url":null,"abstract":"The significance, requirements, and potential of an integrated tool for the evaluation of simulation results in VLSI design are discussed. Results and solutions developed for a simulation evaluation tool called SIMUEVA are stated and exemplified. Particular aspects considered are proper modeling of simulation result data, a UPN set calculator for extraction of goal-directed excerpts, validation by automatic comparison, inclusion of hardware structure descriptions into the evaluation process, examples of automatic fault location, and interaction of evaluation and other VLSI design tools are stated and exemplified","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"3 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116389710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Several CMOS amplifier types are compared and optimized for high-frequency applications. Scaling laws are derived for the power consumption as a function of the gain bandwidth, the load capacitance and the second pole. It is shown that minor modifications on existing circuits can save over a factor of two of power consumption. A 3-μm wideband amplifier is presented with 150-MHz gain-bandwidth and 60° phase margin and with 30 mW of power consumption for a load capacitance of 2 pF
{"title":"Design and optimisation of CMOS wideband amplifiers","authors":"F. Op't Eynde, W. Sansen","doi":"10.1109/CICC.1989.56834","DOIUrl":"https://doi.org/10.1109/CICC.1989.56834","url":null,"abstract":"Several CMOS amplifier types are compared and optimized for high-frequency applications. Scaling laws are derived for the power consumption as a function of the gain bandwidth, the load capacitance and the second pole. It is shown that minor modifications on existing circuits can save over a factor of two of power consumption. A 3-μm wideband amplifier is presented with 150-MHz gain-bandwidth and 60° phase margin and with 30 mW of power consumption for a load capacitance of 2 pF","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116938708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An approach is described for knowledge-based acquisition and checking of system-specification data using frames and rules. Beside the functional description, electrical, timing, environmental, and test-oriented specification data is captured. The representation of a complete specification in a frame knowledge base provides support and control of essential design and verification steps
{"title":"An approach to knowledge-based ASIC specification","authors":"K. Mueller-Glaser, J. Bortolazzi","doi":"10.1109/CICC.1989.56788","DOIUrl":"https://doi.org/10.1109/CICC.1989.56788","url":null,"abstract":"An approach is described for knowledge-based acquisition and checking of system-specification data using frames and rules. Beside the functional description, electrical, timing, environmental, and test-oriented specification data is captured. The representation of a complete specification in a frame knowledge base provides support and control of essential design and verification steps","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115535514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Murabayashi, Y. Nishio, H. Maejima, A. Watanabe, S. Shukuri, T. Nishida, K. Shimohigashi
A BiCMOS channelless gate array using 0.5-μm BiCMOS technology is described. To improve the speed and density of the gate array, a novel feedback-type BiCMOS circuit and the channelless architecture were adopted. The plane-type gate array has 54 K cells and can construct a three-input NAND or NOR gate using one of them. The array realizes the high utilization ratio of basic cells using a four-metal-layer wiring technique. If macrocells are used, the density of the chip becomes more than twice that of a plane-type gate array. The gate delay time of 220 ps was simulated using a feedback-type BiCMOS two-input NAND circuit and 0.5-μm BiCMOS devices with a 4-V power supply. This high-performance BiCMOS channelless gate array can be applied to high-speed computers
{"title":"A 0.5 μm BiCMOS channelless gate array","authors":"F. Murabayashi, Y. Nishio, H. Maejima, A. Watanabe, S. Shukuri, T. Nishida, K. Shimohigashi","doi":"10.1109/CICC.1989.56718","DOIUrl":"https://doi.org/10.1109/CICC.1989.56718","url":null,"abstract":"A BiCMOS channelless gate array using 0.5-μm BiCMOS technology is described. To improve the speed and density of the gate array, a novel feedback-type BiCMOS circuit and the channelless architecture were adopted. The plane-type gate array has 54 K cells and can construct a three-input NAND or NOR gate using one of them. The array realizes the high utilization ratio of basic cells using a four-metal-layer wiring technique. If macrocells are used, the density of the chip becomes more than twice that of a plane-type gate array. The gate delay time of 220 ps was simulated using a feedback-type BiCMOS two-input NAND circuit and 0.5-μm BiCMOS devices with a 4-V power supply. This high-performance BiCMOS channelless gate array can be applied to high-speed computers","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115189382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 10-bit 50 M-sample/s digital-to-analog converter has been fabricated in a 3-μm, double-metal, single-polysilicon CMOS process. The architecture of the converter was chosen to minimize the effects of chip gradients, mismatches and transistor parameters, voltage drops in supply tracks, and other nonideal effects. Close attention was paid to the dynamic behavior of the converter to reduce output glitches and code-dependent distortion
{"title":"A 10-bit high speed CMOS CAS macrocell","authors":"A. W. Vogt, I. Dedic","doi":"10.1109/CICC.1989.56703","DOIUrl":"https://doi.org/10.1109/CICC.1989.56703","url":null,"abstract":"A 10-bit 50 M-sample/s digital-to-analog converter has been fabricated in a 3-μm, double-metal, single-polysilicon CMOS process. The architecture of the converter was chosen to minimize the effects of chip gradients, mismatches and transistor parameters, voltage drops in supply tracks, and other nonideal effects. Close attention was paid to the dynamic behavior of the converter to reduce output glitches and code-dependent distortion","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114690560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Friedman, J. Khoury, L. J. Loporcaro, M. Theobald, E. Fields, M. Tompsett, V. Gopal, G. L. Lustro, M. Figueroa
A 1.5-μm CMOS codec, using Σ-Δ conversion techniques, which incorporates the hybrid echo cancellation on chip, is described. The echo cancellation is done in two states, using an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter. The limiting effects of the variation of the analog components on the echo cancellation performance of the device are minimized, so that only one set of coefficients per national standard is necessary
{"title":"A codec with on-chip digital echo canceller","authors":"V. Friedman, J. Khoury, L. J. Loporcaro, M. Theobald, E. Fields, M. Tompsett, V. Gopal, G. L. Lustro, M. Figueroa","doi":"10.1109/CICC.1989.56770","DOIUrl":"https://doi.org/10.1109/CICC.1989.56770","url":null,"abstract":"A 1.5-μm CMOS codec, using Σ-Δ conversion techniques, which incorporates the hybrid echo cancellation on chip, is described. The echo cancellation is done in two states, using an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter. The limiting effects of the variation of the analog components on the echo cancellation performance of the device are minimized, so that only one set of coefficients per national standard is necessary","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127203409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Simulations of CMOS combinational circuits have been conducted to determine the relationship between stuck-at and stuck-open fault coverage. The results suggest that node activity is more important to stuck-open fault coverage than test length by itself. Reordering test sets so that node activity is increased resulted in increased stuck-open fault coverage. It is important to note that the reordering of the test sets requires an analysis of fault-free simulations; no fault simulations need to be done. It has been shown that all but some minimum-length test sets can easily achieve the 75% stuck-open fault coverage required by the DoD (US Department of Defense), and pseudorandom tests, which have high measures of node activity, can be expected to have over 90% stuck-open fault coverage
{"title":"Detecting stuck-open faults with stuck-at test sets","authors":"S. Millman, E. McCluskey","doi":"10.1109/CICC.1989.56809","DOIUrl":"https://doi.org/10.1109/CICC.1989.56809","url":null,"abstract":"Simulations of CMOS combinational circuits have been conducted to determine the relationship between stuck-at and stuck-open fault coverage. The results suggest that node activity is more important to stuck-open fault coverage than test length by itself. Reordering test sets so that node activity is increased resulted in increased stuck-open fault coverage. It is important to note that the reordering of the test sets requires an analysis of fault-free simulations; no fault simulations need to be done. It has been shown that all but some minimum-length test sets can easily achieve the 75% stuck-open fault coverage required by the DoD (US Department of Defense), and pseudorandom tests, which have high measures of node activity, can be expected to have over 90% stuck-open fault coverage","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127060635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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