Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551704
E. Bazizi, E. Banghart, B. Zhu, J. H. B. Tng, F. Benistant, Y. Hu, X. He, D. Zhou, H. Lo, D. Choi, J. G. Lee
3D TCAD (Technology Computer Aided Design) process and device simulation is used to show that taller and thinner fins at the 14nm device node enable significant DC and RO performance gains for both nFET and pFET short channel devices through improvement in charge inversion andleakage current control. In particular, simulations identify a maximum in the DC and RO performance as a function of the Fin Ratio, defined as the top fin width (TCD) over the bottom fin width (BCD). At long channel, TCAD simulation demonstrates that mobility degradation observed in nFET hardware devices (but not in pFET devices) is due to the effect of quantum confinement in the fin.
3D TCAD(技术计算机辅助设计)过程和器件仿真表明，在14nm器件节点上更高和更薄的鳍通过改进电荷反转和泄漏电流控制，使nFET和pFET短通道器件的直流和反渗透性能得到显著提高。特别地，模拟确定了直流和反渗透性能的最大值是鳍比的函数，定义为上鳍宽度(TCD)除以下鳍宽度(BCD)。在长信道下，TCAD模拟表明，在fet硬件器件中观察到的迁移率下降(而不是在fet器件中)是由于鳍中的量子限制的影响。
{"title":"14nm FinFET Device Boost via 2nd Generation Fins Optimized for High Performance CMOS Applications","authors":"E. Bazizi, E. Banghart, B. Zhu, J. H. B. Tng, F. Benistant, Y. Hu, X. He, D. Zhou, H. Lo, D. Choi, J. G. Lee","doi":"10.1109/SISPAD.2018.8551704","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551704","url":null,"abstract":"3D TCAD (Technology Computer Aided Design) process and device simulation is used to show that taller and thinner fins at the 14nm device node enable significant DC and RO performance gains for both nFET and pFET short channel devices through improvement in charge inversion andleakage current control. In particular, simulations identify a maximum in the DC and RO performance as a function of the Fin Ratio, defined as the top fin width (TCD) over the bottom fin width (BCD). At long channel, TCAD simulation demonstrates that mobility degradation observed in nFET hardware devices (but not in pFET devices) is due to the effect of quantum confinement in the fin.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123225170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551740
N. Parihar, R. Tiwari, S. Mahapatra
Negative Bias Temperature Instability (NBTI) stress and recovery time kinetics fromReplacement Metal Gate (RMG) High-K Metal Gate (HKMG) p-channel FinFETs are measured and modeled. The impact of channel length (L) scaling on shift in threshold voltage ($mathrm{V}_{T})$,its power-law time exponent (n), Voltage Acceleration Factor (VAF) and Temperature (T) activation $( mathrm{E}_{A})$ is analyzed. TCAD and band structure calculations are utilized to explain the L dependence of experimental data.
{"title":"Modeling Channel Length Scaling Impact on NBTI in RMG Si p-FinFETs","authors":"N. Parihar, R. Tiwari, S. Mahapatra","doi":"10.1109/SISPAD.2018.8551740","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551740","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) stress and recovery time kinetics fromReplacement Metal Gate (RMG) High-K Metal Gate (HKMG) p-channel FinFETs are measured and modeled. The impact of channel length (L) scaling on shift in threshold voltage ($mathrm{V}_{T})$,its power-law time exponent (n), Voltage Acceleration Factor (VAF) and Temperature (T) activation $( mathrm{E}_{A})$ is analyzed. TCAD and band structure calculations are utilized to explain the L dependence of experimental data.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"40 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551654
C. Pigot, F. Gilibert, M. Reyboz, M. Bocquet, J. Portal
To achieve high yield on product embedding PCM memory, it is mandatory to provide to designers accurately calibrated PCM compact model. To achieve this goal, it is mandatory to develop standardized model card extraction methodology. In this paper, we present a PCM model card extraction flow based on a minimal set of static and dynamic measurements. Based on this measurement, characteristics are first obtained and model card parameters extracted without any loop back, i.e. each parameter is extracted only once on a given characteristic. After this extraction procedure, model card values are validated through a comparison with an extra characteristics SET-Low characteristic not used for the extraction.
{"title":"PCM compact model: Optimized methodology for model card extraction","authors":"C. Pigot, F. Gilibert, M. Reyboz, M. Bocquet, J. Portal","doi":"10.1109/SISPAD.2018.8551654","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551654","url":null,"abstract":"To achieve high yield on product embedding PCM memory, it is mandatory to provide to designers accurately calibrated PCM compact model. To achieve this goal, it is mandatory to develop standardized model card extraction methodology. In this paper, we present a PCM model card extraction flow based on a minimal set of static and dynamic measurements. Based on this measurement, characteristics are first obtained and model card parameters extracted without any loop back, i.e. each parameter is extracted only once on a given characteristic. After this extraction procedure, model card values are validated through a comparison with an extra characteristics SET-Low characteristic not used for the extraction.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116225103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551652
B. Bakeroot, B. D. Jaeger, N. Ronchi, S. Stoffels, M. Zhao, S. Decoutere
Technology Computer Aided Design simulations are used to assess the influence of carbon in the back-barrier layers of GaN-on-Si wafers on the voltage distribution in GaN Schottky diodes. It is shown that carbon cannot be present as an acceptor only – as it is commonly assumed. The carbon needs to be compensated by donors or partly electrically inactive in order to explain the observed high hard breakdown voltage in GaN-onSi Schottky diodes. Furthermore, it is shown that the level of donor compensation of the carbon will have a significant influence on the two-dimensional voltage distribution in the devices, and, hence, on the surface electric field peaks. This conclusion is important to consider in the design of field plate extensions of the Schottky diode.
{"title":"The influence of carbon in the back-barrier layers on the surface electric field peaks in GaN Schottky diodes","authors":"B. Bakeroot, B. D. Jaeger, N. Ronchi, S. Stoffels, M. Zhao, S. Decoutere","doi":"10.1109/SISPAD.2018.8551652","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551652","url":null,"abstract":"Technology Computer Aided Design simulations are used to assess the influence of carbon in the back-barrier layers of GaN-on-Si wafers on the voltage distribution in GaN Schottky diodes. It is shown that carbon cannot be present as an acceptor only – as it is commonly assumed. The carbon needs to be compensated by donors or partly electrically inactive in order to explain the observed high hard breakdown voltage in GaN-onSi Schottky diodes. Furthermore, it is shown that the level of donor compensation of the carbon will have a significant influence on the two-dimensional voltage distribution in the devices, and, hence, on the surface electric field peaks. This conclusion is important to consider in the design of field plate extensions of the Schottky diode.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124005478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551750
O. D. Restrepo, Qun Gao, S. Pandey, E. Cruz‐Silva, E. Bazizi
We present ab initio-based electronic transport calculations on the effect of uniaxial and bi-axial stress on the CoSi2/n Si interface resistivity for the three main silicon crystallographic directions. For the [001] case, we identify two distinctive low and high bias conduction regimes for both compressive and tensile stress. In these regimes, the current is dominated by electronic transmission pathways near the Γ point for bias up to ~0.1V, while for higher bias it is dominated by transmission at the (±1/2, ±1/2) conduction band valleys of the Brillouin zone, which results in a contact resistivity decrease of up to 30% at 0.2V bias. This effect is less pronounced for the [110] direction, and negligible for the [111] case due to the symmetry of the Si conduction band valleys along these directions. This study provides insight into stress-based optimization pathways for contact resistivity reduction of silicide interfaces in next generation semiconductor devices.
{"title":"First Principles Calculations of the Effect of Stress in the I-V Characteristics of the CoSi2/Si Interface","authors":"O. D. Restrepo, Qun Gao, S. Pandey, E. Cruz‐Silva, E. Bazizi","doi":"10.1109/SISPAD.2018.8551750","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551750","url":null,"abstract":"We present ab initio-based electronic transport calculations on the effect of uniaxial and bi-axial stress on the CoSi2/n Si interface resistivity for the three main silicon crystallographic directions. For the [001] case, we identify two distinctive low and high bias conduction regimes for both compressive and tensile stress. In these regimes, the current is dominated by electronic transmission pathways near the Γ point for bias up to ~0.1V, while for higher bias it is dominated by transmission at the (±1/2, ±1/2) conduction band valleys of the Brillouin zone, which results in a contact resistivity decrease of up to 30% at 0.2V bias. This effect is less pronounced for the [110] direction, and negligible for the [111] case due to the symmetry of the Si conduction band valleys along these directions. This study provides insight into stress-based optimization pathways for contact resistivity reduction of silicide interfaces in next generation semiconductor devices.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"452 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132996050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551631
I. Martín-Bragado, Yumi Park, C. Zechner, Y. Oh
First principle calculations are a convenient and cost effective procedure to obtain the properties of the new and optimized materials required to solve the challenges of the next generation of semiconductor devices. But, even with reliable tools, the computation of the vacancy intermediated impurity diffusion can be challenging, especially in alloys. This work shows an algorithm to automate the process of such calculation by implementing a methodology tocompute ring mechanisms in generic materials. Results for semiconductor (namely, Ge diffusion in Si and As diffusion in a Si0.5 Ge0.5 random alloy) and non-semiconductor materials (Al diffusion in TiN) are shown. The results stress botha) the importance of the ring mechanism in understanding the diffusivity of impurities in crystalline materials, and b) the need for automatic algorithms that deal with the complexity of sampling and generating consistent configurations for such calculations.
{"title":"High Throughput Simulation On The Impurity-Vacancy Diffusion Mechanism Using First-Principles","authors":"I. Martín-Bragado, Yumi Park, C. Zechner, Y. Oh","doi":"10.1109/SISPAD.2018.8551631","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551631","url":null,"abstract":"First principle calculations are a convenient and cost effective procedure to obtain the properties of the new and optimized materials required to solve the challenges of the next generation of semiconductor devices. But, even with reliable tools, the computation of the vacancy intermediated impurity diffusion can be challenging, especially in alloys. This work shows an algorithm to automate the process of such calculation by implementing a methodology tocompute ring mechanisms in generic materials. Results for semiconductor (namely, Ge diffusion in Si and As diffusion in a Si0.5 Ge0.5 random alloy) and non-semiconductor materials (Al diffusion in TiN) are shown. The results stress botha) the importance of the ring mechanism in understanding the diffusivity of impurities in crystalline materials, and b) the need for automatic algorithms that deal with the complexity of sampling and generating consistent configurations for such calculations.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131828276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/sispad.2018.8551738
{"title":"SISPAD 2018 Cover Page","authors":"","doi":"10.1109/sispad.2018.8551738","DOIUrl":"https://doi.org/10.1109/sispad.2018.8551738","url":null,"abstract":"","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132498429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/sispad.2018.8551754
{"title":"SISPAD 2018 Program","authors":"","doi":"10.1109/sispad.2018.8551754","DOIUrl":"https://doi.org/10.1109/sispad.2018.8551754","url":null,"abstract":"","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133571329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551706
D. Rideau, G. Mugny, M. Pala, D. Esseni
This paper presents a systematic analysis of the use of the linear combination of bulk bands based on the empirical pseudopotential method to obtain the bandstructure of confined nanostructures. The relevance of interband coupling between conduction and valence bands in III-V materials is highlighted.
{"title":"Inter-band coupling in Empirical Pseudopotential Method based bandstructure calculations of group IV and III-V nanostructures","authors":"D. Rideau, G. Mugny, M. Pala, D. Esseni","doi":"10.1109/SISPAD.2018.8551706","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551706","url":null,"abstract":"This paper presents a systematic analysis of the use of the linear combination of bulk bands based on the empirical pseudopotential method to obtain the bandstructure of confined nanostructures. The relevance of interband coupling between conduction and valence bands in III-V materials is highlighted.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115146218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551630
C. Medina-Bailón, T. Sadi, M. Nedjalkov, Jaehyun Lee, S. Berrada, H. Carrillo-Nuñez, V. Georgiev, S. Selberherr, A. Asenov
In the simulation based research of aggressively scaled CMOS transistors, it is mandatoryto combine advanced transport simulators and quantum confinement effects with atomistic simulations which accurately reproduce the electronic structure at the nanometer scale. This work investigates the impact of cross-section dependent effective masses, obtained from atomistic simulations, on the mobility in Si nanowire transistors (NWTs). For the transport simulations, weuse the Kubo-Greenwood formalism with a set of multisubband phonon, surface roughness, and impurity scattering mechanisms.
{"title":"Impact of the Effective Mass on the Mobility in Si Nanowire Transistors","authors":"C. Medina-Bailón, T. Sadi, M. Nedjalkov, Jaehyun Lee, S. Berrada, H. Carrillo-Nuñez, V. Georgiev, S. Selberherr, A. Asenov","doi":"10.1109/SISPAD.2018.8551630","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551630","url":null,"abstract":"In the simulation based research of aggressively scaled CMOS transistors, it is mandatoryto combine advanced transport simulators and quantum confinement effects with atomistic simulations which accurately reproduce the electronic structure at the nanometer scale. This work investigates the impact of cross-section dependent effective masses, obtained from atomistic simulations, on the mobility in Si nanowire transistors (NWTs). For the transport simulations, weuse the Kubo-Greenwood formalism with a set of multisubband phonon, surface roughness, and impurity scattering mechanisms.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121453292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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