Optimizing the locations and sizes of droplets is the key to reducing defects and increasing throughput of ultraviolet nanoimprint lithography. In practice the templates are composed of regions with different structures. The interface between structures will generate complicated fluid flow behavior that will slow the filling time. Here, we explore several strategies through simulations to distribute resist material according to a nonuniform pattern to reduce filling time and ultimately increase throughput. In order to mimic the complexity of a template, the interface between different pairs of template structures is considered and the spreading and merging of droplets are simulated. From these simulations, it is found that the volume and arrangement of droplets underneath strongly affect the imprint time. By distributing the correct amount of resist underneath the template, one can remove the unnecessary fluid transferring step in droplet spreading and reduce the total filling time. Furthermore, by optimally placing the resist droplets, one can delay merging events and accelerate the spreading speed. Finally, the advantage of hexagonal arrangements is explored.
{"title":"Minimizing filling time for ultraviolet nanoimprint lithography with templates with multiple structures","authors":"Yang H. Ban, R. Bonnecaze","doi":"10.1116/6.0000648","DOIUrl":"https://doi.org/10.1116/6.0000648","url":null,"abstract":"Optimizing the locations and sizes of droplets is the key to reducing defects and increasing throughput of ultraviolet nanoimprint lithography. In practice the templates are composed of regions with different structures. The interface between structures will generate complicated fluid flow behavior that will slow the filling time. Here, we explore several strategies through simulations to distribute resist material according to a nonuniform pattern to reduce filling time and ultimately increase throughput. In order to mimic the complexity of a template, the interface between different pairs of template structures is considered and the spreading and merging of droplets are simulated. From these simulations, it is found that the volume and arrangement of droplets underneath strongly affect the imprint time. By distributing the correct amount of resist underneath the template, one can remove the unnecessary fluid transferring step in droplet spreading and reduce the total filling time. Furthermore, by optimally placing the resist droplets, one can delay merging events and accelerate the spreading speed. Finally, the advantage of hexagonal arrangements is explored.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78351931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, self-heating effects (SHE) in nanometer-scale metal-oxide-semiconductor field-effect transistor structures—namely, FinFETs (FFs), nanosheet gate-all-around FETs (NSFs), and nanowire gate-all-around FETs (GAAFs)—are investigated via three-dimensional device electrothermal simulations using technology computer-aided design software tools. Initially, transistor design parameter values are set so that their on-state currents are similar for the same operating voltage (VDD). It is found that NSFs and GAAFs are more susceptible to SHE and that p-channel transistors have higher peak internal temperatures than do their n-channel counterparts due to the poor thermal conductivity of the silicon-germanium used as the p-type source/drain material. Subsequently, the on-state currents of FFs, NSFs, and GAAFs are compared under the constraint of identical peak internal temperature, which is required to ensure long-term reliability, revealing that NSFs and GAAFs offer no performance advantage over FFs under this constraint. Design optimization of p-channel NSFs for minimal SHE is subsequently investigated. It is found that with such optimization, NSFs operating at lower VDD (for similar SHE) can achieve similar on-state current as FFs.
{"title":"Design optimization of sub-5 nm node nanosheet field effect transistors to minimize self-heating effects","authors":"F. Ding, H. Wong, T. Liu","doi":"10.1116/6.0000675","DOIUrl":"https://doi.org/10.1116/6.0000675","url":null,"abstract":"In this work, self-heating effects (SHE) in nanometer-scale metal-oxide-semiconductor field-effect transistor structures—namely, FinFETs (FFs), nanosheet gate-all-around FETs (NSFs), and nanowire gate-all-around FETs (GAAFs)—are investigated via three-dimensional device electrothermal simulations using technology computer-aided design software tools. Initially, transistor design parameter values are set so that their on-state currents are similar for the same operating voltage (VDD). It is found that NSFs and GAAFs are more susceptible to SHE and that p-channel transistors have higher peak internal temperatures than do their n-channel counterparts due to the poor thermal conductivity of the silicon-germanium used as the p-type source/drain material. Subsequently, the on-state currents of FFs, NSFs, and GAAFs are compared under the constraint of identical peak internal temperature, which is required to ensure long-term reliability, revealing that NSFs and GAAFs offer no performance advantage over FFs under this constraint. Design optimization of p-channel NSFs for minimal SHE is subsequently investigated. It is found that with such optimization, NSFs operating at lower VDD (for similar SHE) can achieve similar on-state current as FFs.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78114939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A variety of nonvolatile memory (NVM) devices including the resistive Random Access Memory (RRAM) are currently being investigated for implementing energy-efficient hardware for deep learning and artificial intelligence at the edge. RRAM devices are employed in the form of dense crosspoint or crossbar arrays. In order to exploit the high-density and low-power operation of these devices, circuit designers need to accommodate their nonideal behavior and consider their impact on circuit design and algorithm performance. Hybrid integration of RRAMs with standard CMOS technology is spurring the development of large-scale neuromorphic system-on-a-chip. This review article provides an overview of neuromorphic integrated circuits (ICs) using hybrid CMOS-RRAM integration with an emphasis on spiking neural networks (SNNs), device nonidealities, their associated circuit design challenges, and potential strategies for their mitigation. An overview of various SNN learning algorithms and their codevelopment with devices and circuits is discussed. Finally, a comparison of NVM-based fully integrated neuromorphic ICs is presented along with a discussion on their future evolution.
{"title":"Neuromorphic computing: From devices to integrated circuits","authors":"V. Saxena","doi":"10.1116/6.0000591","DOIUrl":"https://doi.org/10.1116/6.0000591","url":null,"abstract":"A variety of nonvolatile memory (NVM) devices including the resistive Random Access Memory (RRAM) are currently being investigated for implementing energy-efficient hardware for deep learning and artificial intelligence at the edge. RRAM devices are employed in the form of dense crosspoint or crossbar arrays. In order to exploit the high-density and low-power operation of these devices, circuit designers need to accommodate their nonideal behavior and consider their impact on circuit design and algorithm performance. Hybrid integration of RRAMs with standard CMOS technology is spurring the development of large-scale neuromorphic system-on-a-chip. This review article provides an overview of neuromorphic integrated circuits (ICs) using hybrid CMOS-RRAM integration with an emphasis on spiking neural networks (SNNs), device nonidealities, their associated circuit design challenges, and potential strategies for their mitigation. An overview of various SNN learning algorithms and their codevelopment with devices and circuits is discussed. Finally, a comparison of NVM-based fully integrated neuromorphic ICs is presented along with a discussion on their future evolution.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72890939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sofya Torosyan, A. Kteyan, V. Sukharev, J. Choy, F. Najm
A recently developed novel methodology for electromigration (EM) failure assessment in power/ground grids of integrated circuits is employed in the electronic design automation tool prototype. The tool performs the analysis of stress evolution in interconnect trees for detecting EM-induced voiding locations and tracks resistance increase in the voided wires based on a physics-based model of voiding kinetics. Increased resistances of the branches of power/ground networks lead to a voltage drop increase in grid nodes. The instance in time when a designer-specified voltage-drop threshold is reached defines the EM-induced time-to-failure. Monte-Carlo simulation, performed around the core engine that simulates the stress over time using randomly generated atomic diffusivities and critical stress values, leads to the mean-time-to-failure of the grid, along with voiding probabilities of the interconnect branches.
{"title":"Novel physics-based tool-prototype for electromigration assessment in commercial-grade power delivery networks","authors":"Sofya Torosyan, A. Kteyan, V. Sukharev, J. Choy, F. Najm","doi":"10.1116/6.0000617","DOIUrl":"https://doi.org/10.1116/6.0000617","url":null,"abstract":"A recently developed novel methodology for electromigration (EM) failure assessment in power/ground grids of integrated circuits is employed in the electronic design automation tool prototype. The tool performs the analysis of stress evolution in interconnect trees for detecting EM-induced voiding locations and tracks resistance increase in the voided wires based on a physics-based model of voiding kinetics. Increased resistances of the branches of power/ground networks lead to a voltage drop increase in grid nodes. The instance in time when a designer-specified voltage-drop threshold is reached defines the EM-induced time-to-failure. Monte-Carlo simulation, performed around the core engine that simulates the stress over time using randomly generated atomic diffusivities and critical stress values, leads to the mean-time-to-failure of the grid, along with voiding probabilities of the interconnect branches.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83359212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ionic liquid/ionogel gate dielectrics can provide significant advantages for transistor architectures that utilize high surface area semiconductors and/or nonplanar substrates because of their cleanroom-free, liquid-based processability and their inherently large electrostatic double layer capacitance. These attributes of ionogels have already enabled the facile fabrication of several up-and-coming transistor devices geometries for which a highly conformal interface between the electrolyte gate dielectric and the semiconductor is readily achievable, and remote gating with a nonaligned gate electrode is possible. Further, ionogel gating can improve device performance to maximize current densities at low operating voltages. This Perspective highlights three classes of emerging transistor architectures, namely, vertical transistors, surround gate transistors, and thread/fiber-based transistors, and provides several key examples of instances where ionogel gating has either already enabled or still stands to improve device fabrication and performance.
{"title":"Opportunities for ionic liquid/ionogel gating of emerging transistor architectures","authors":"Rachel Owyeung, S. Sonkusale, M. Panzer","doi":"10.1116/6.0000678","DOIUrl":"https://doi.org/10.1116/6.0000678","url":null,"abstract":"Ionic liquid/ionogel gate dielectrics can provide significant advantages for transistor architectures that utilize high surface area semiconductors and/or nonplanar substrates because of their cleanroom-free, liquid-based processability and their inherently large electrostatic double layer capacitance. These attributes of ionogels have already enabled the facile fabrication of several up-and-coming transistor devices geometries for which a highly conformal interface between the electrolyte gate dielectric and the semiconductor is readily achievable, and remote gating with a nonaligned gate electrode is possible. Further, ionogel gating can improve device performance to maximize current densities at low operating voltages. This Perspective highlights three classes of emerging transistor architectures, namely, vertical transistors, surround gate transistors, and thread/fiber-based transistors, and provides several key examples of instances where ionogel gating has either already enabled or still stands to improve device fabrication and performance.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78393533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abhishek Raj, Manish Kumar, H. Bherwani, Ankit Gupta, A. Anshul
Simulation has been performed on fully lead-free inorganic cesium germanium tri-iodide (CsGeI3) perovskite solar cell heterostructure and achieved a champion power conversion efficiency (PCE) of ∼18.30% with significantly improved device parameters. The influence of thickness of an electron transport layer, a hole transport layer, an absorber, defect density, doping concentration, electron affinity, temperature, and series resistance issued for the optimization of the lead-free device is studied. It is confirmed via the scaps simulation results that this device is perfectly optimized with the experimental results and demonstrates the maximum possible improved power conversion efficiency in a fully inorganic lead-free CsGeI3 perovskite solar cell device. The final optimized device performance parameters are as follows: %PCE = 18.30%, %FF = 75.46%, Jsc = 23.31 mA/cm2, and Voc = 1.04 V. In the future, this efficiency may offer prominent potential as a substitute in a highly efficient green solar absorber material for photovoltaic applications after confirmation in the laboratory.
{"title":"Evidence of improved power conversion efficiency in lead-free CsGeI3 based perovskite solar cell heterostructure via scaps simulation","authors":"Abhishek Raj, Manish Kumar, H. Bherwani, Ankit Gupta, A. Anshul","doi":"10.1116/6.0000718","DOIUrl":"https://doi.org/10.1116/6.0000718","url":null,"abstract":"Simulation has been performed on fully lead-free inorganic cesium germanium tri-iodide (CsGeI3) perovskite solar cell heterostructure and achieved a champion power conversion efficiency (PCE) of ∼18.30% with significantly improved device parameters. The influence of thickness of an electron transport layer, a hole transport layer, an absorber, defect density, doping concentration, electron affinity, temperature, and series resistance issued for the optimization of the lead-free device is studied. It is confirmed via the scaps simulation results that this device is perfectly optimized with the experimental results and demonstrates the maximum possible improved power conversion efficiency in a fully inorganic lead-free CsGeI3 perovskite solar cell device. The final optimized device performance parameters are as follows: %PCE = 18.30%, %FF = 75.46%, Jsc = 23.31 mA/cm2, and Voc = 1.04 V. In the future, this efficiency may offer prominent potential as a substitute in a highly efficient green solar absorber material for photovoltaic applications after confirmation in the laboratory.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90259396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reported is the manufacture and optimization of inverted micropyramid cavity structures into thermoplastic sheets using roll-to-roll (R2R) embossing. To manufacture the master, an ultraprecision diamond machining method was applied to create seamless surface structures into a copper-coated hot embossing roller. Using the hot embossing process, the roller features were successfully transferred to 2 mm thick polymethyl methacrylate (PMMA) sheets. Optimization of the R2R control process variables was conducted using Taguchi's numerical methods, which showed the importance of the roller temperature for a successful pattern transfer. The work presents a novel fabrication technique that allows microstructures to be manufactured into thick PMMA sheets in a continuous process.
{"title":"Optimization of a continuous hot embossing process for fabrication of micropyramid structures in thermoplastic sheets","authors":"L. Haponow, J. Kettle, J. Allsop","doi":"10.1116/6.0000551","DOIUrl":"https://doi.org/10.1116/6.0000551","url":null,"abstract":"Reported is the manufacture and optimization of inverted micropyramid cavity structures into thermoplastic sheets using roll-to-roll (R2R) embossing. To manufacture the master, an ultraprecision diamond machining method was applied to create seamless surface structures into a copper-coated hot embossing roller. Using the hot embossing process, the roller features were successfully transferred to 2 mm thick polymethyl methacrylate (PMMA) sheets. Optimization of the R2R control process variables was conducted using Taguchi's numerical methods, which showed the importance of the roller temperature for a successful pattern transfer. The work presents a novel fabrication technique that allows microstructures to be manufactured into thick PMMA sheets in a continuous process.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85478350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A cerium hexaboride (CeB6) single crystal grown by the floating-zone method has a low work function of about 2.6 eV, and along with lanthanum hexaboride (LaB6), it is one of the most popular cathode materials. It has been widely used as the thermionic emitter of electron microscopes, such as SEMs and TEMs. However, cold-field emitters (CFEs) based on CeB6 and LaB6 have not been put to practical use due to their insufficient emission stability compared to that of conventional tungsten (W)-CFEs. In consideration of that background, in the present study, the stability of the emission current from a CeB6 single-crystal CFE was improved by using the (100) plane at the faceted tip of the single crystal. The CeB6⟨100⟩ single crystal was processed by electrochemical etching and successive high-temperature field evaporation and faceting under an appropriate electric field to make a (100) plane at the apex of the crystal. The improved CeB6(100)-CFE emitted a monochromatic electron beam, which has about three-quarters of the energy width of that of W(310)-CFEs. Emission current from the (100) plane maintained low emission noise, and emission decay in the electron-gun chamber of the SEM was suppressed. The resulting current noise is low enough to produce SEM images without image deterioration, and the relatively small decay makes it possible to use the CeB6(100) emitter for one flashing process per day.
{"title":"Stabilization of cold-field-emission current from a CeB6 single-crystal emitter by using a faceted (100) plane","authors":"T. Kusunoki, T. Hashizume, K. Kasuya, N. Arai","doi":"10.1116/6.0000739","DOIUrl":"https://doi.org/10.1116/6.0000739","url":null,"abstract":"A cerium hexaboride (CeB6) single crystal grown by the floating-zone method has a low work function of about 2.6 eV, and along with lanthanum hexaboride (LaB6), it is one of the most popular cathode materials. It has been widely used as the thermionic emitter of electron microscopes, such as SEMs and TEMs. However, cold-field emitters (CFEs) based on CeB6 and LaB6 have not been put to practical use due to their insufficient emission stability compared to that of conventional tungsten (W)-CFEs. In consideration of that background, in the present study, the stability of the emission current from a CeB6 single-crystal CFE was improved by using the (100) plane at the faceted tip of the single crystal. The CeB6⟨100⟩ single crystal was processed by electrochemical etching and successive high-temperature field evaporation and faceting under an appropriate electric field to make a (100) plane at the apex of the crystal. The improved CeB6(100)-CFE emitted a monochromatic electron beam, which has about three-quarters of the energy width of that of W(310)-CFEs. Emission current from the (100) plane maintained low emission noise, and emission decay in the electron-gun chamber of the SEM was suppressed. The resulting current noise is low enough to produce SEM images without image deterioration, and the relatively small decay makes it possible to use the CeB6(100) emitter for one flashing process per day.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77488908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Focused ion beam (FIB) sample preparation for electron microscopy often requires large volumes of materials to be removed. Prior efforts to increase the rate of bulk material removal were mainly focused on increasing the primary ion beam current. Enhanced yield of etching at glancing ion beam incidence is known but has not found widespread use in practical applications. In this study, etching at glancing ion beam incidence was explored for its advantages in increasing the rate of bulk material removal. Anomalous enhancement of material removal at glancing angles of ion beam incidence was observed with single-raster etching in along-the-slope direction with toward-FIB direction of raster propagation. Material removal was inhibited in an away-from-FIB direction of raster propagation. The effects of glancing angles and ion doses on depth of cut and volume of removed materials were also recorded. We demonstrated that the combination of single-raster FIB etching at glancing incidence in along-the-slope direction with toward-FIB raster propagation and a “staircase” type of etching strategy holds promise for reducing the processing time for bulk material removal in FIB sample preparation applications.
{"title":"Anomalous enhancement of focused ion beam etching by single raster propagating toward ion beam at glancing incidence","authors":"J. Favata, V. Ray, S. Shahbazmohamadi","doi":"10.1116/6.0000555","DOIUrl":"https://doi.org/10.1116/6.0000555","url":null,"abstract":"Focused ion beam (FIB) sample preparation for electron microscopy often requires large volumes of materials to be removed. Prior efforts to increase the rate of bulk material removal were mainly focused on increasing the primary ion beam current. Enhanced yield of etching at glancing ion beam incidence is known but has not found widespread use in practical applications. In this study, etching at glancing ion beam incidence was explored for its advantages in increasing the rate of bulk material removal. Anomalous enhancement of material removal at glancing angles of ion beam incidence was observed with single-raster etching in along-the-slope direction with toward-FIB direction of raster propagation. Material removal was inhibited in an away-from-FIB direction of raster propagation. The effects of glancing angles and ion doses on depth of cut and volume of removed materials were also recorded. We demonstrated that the combination of single-raster FIB etching at glancing incidence in along-the-slope direction with toward-FIB raster propagation and a “staircase” type of etching strategy holds promise for reducing the processing time for bulk material removal in FIB sample preparation applications.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90425062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cha-Hee Kim, Jae-Min Kim, Seung-Ho Seo, Jae-hak Lee, J. Song, Won-Jun Lee
We modeled flexible microelectronic systems, in which a thinned silicon die is flip-chip bonded to a flexible substrate, and analyzed the stress and strain distribution generated during twisting deformation. Because of the presence of the rigid silicon die, the strain distribution of the system model was significantly different from that of the substrate model. Unlike the substrate model, there is no significant difference in the von Mises strain according to the position in both the molding layer and the substrate in the system model. Therefore, the results of modeling or testing only flexible substrate cannot be directly applied to predict the behavior of flexible microelectronic systems. The copper bumps revealed stress above the ultimate strength as well as the yield strength. Therefore, the copper bump would be the most mechanically weak component in the operation of the face-down flexible microelectronic system during twisting. By replacing copper bumps with polymer bumps, the maximum stress in the bumps can be significantly reduced from 282 to 47 MPa, and the maximum mechanically safe twisting angle was also improved from approximately 40° to 80°. Therefore, in flexible electronic systems where twisting deformation is applied, polymer bumps are a better bonding method than the conventional copper bumps.
{"title":"Mechanical analysis of a flexible microelectronic system under twisting stress","authors":"Cha-Hee Kim, Jae-Min Kim, Seung-Ho Seo, Jae-hak Lee, J. Song, Won-Jun Lee","doi":"10.1116/6.0000665","DOIUrl":"https://doi.org/10.1116/6.0000665","url":null,"abstract":"We modeled flexible microelectronic systems, in which a thinned silicon die is flip-chip bonded to a flexible substrate, and analyzed the stress and strain distribution generated during twisting deformation. Because of the presence of the rigid silicon die, the strain distribution of the system model was significantly different from that of the substrate model. Unlike the substrate model, there is no significant difference in the von Mises strain according to the position in both the molding layer and the substrate in the system model. Therefore, the results of modeling or testing only flexible substrate cannot be directly applied to predict the behavior of flexible microelectronic systems. The copper bumps revealed stress above the ultimate strength as well as the yield strength. Therefore, the copper bump would be the most mechanically weak component in the operation of the face-down flexible microelectronic system during twisting. By replacing copper bumps with polymer bumps, the maximum stress in the bumps can be significantly reduced from 282 to 47 MPa, and the maximum mechanically safe twisting angle was also improved from approximately 40° to 80°. Therefore, in flexible electronic systems where twisting deformation is applied, polymer bumps are a better bonding method than the conventional copper bumps.","PeriodicalId":17652,"journal":{"name":"Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77776128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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