Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493875
C. Tsai, B. Scharf, P. Garone, P. Humphries, K. O
Emitter widths of 0.3 /spl mu/m on double-polysilicon bipolar transistors are achieved using 0.8-/spl mu/m photolithography and a double-spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f/sub T/ and f/sub max/.
{"title":"A double-spacer technology for the formation of very narrow emitter (0.3 /spl mu/m) double-polysilicon bipolar transistors using 0.8-/spl mu/m photolithography","authors":"C. Tsai, B. Scharf, P. Garone, P. Humphries, K. O","doi":"10.1109/BIPOL.1995.493875","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493875","url":null,"abstract":"Emitter widths of 0.3 /spl mu/m on double-polysilicon bipolar transistors are achieved using 0.8-/spl mu/m photolithography and a double-spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f/sub T/ and f/sub max/.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"87 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131177135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493857
S. Sen, B. Leung
A low-power, high-speed BiCMOS op amp is described. It uses a wideband, composite PMOS-vertical-NPN structure as a substitute for vertical-PNP transistors to realize a Class-AB input stage with very high small and large signal transconductances and op amp slew-rate.
{"title":"A Class-AB high-speed low-power op amp in BiCMOS technology","authors":"S. Sen, B. Leung","doi":"10.1109/BIPOL.1995.493857","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493857","url":null,"abstract":"A low-power, high-speed BiCMOS op amp is described. It uses a wideband, composite PMOS-vertical-NPN structure as a substitute for vertical-PNP transistors to realize a Class-AB input stage with very high small and large signal transconductances and op amp slew-rate.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131613865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493894
Jeffrey S. Glenn, Mary E. Case, David L. Harame, B. Meyerson, R. Poisson
We present Gilbert mixer circuits, fabricated with an epitaxial-base Si/SiGe bipolar technology, having bandwidths of up to 12 GHz and gain-bandwidth products in excess of 22 GHz.
{"title":"12-GHz Gilbert mixers using a manufacturable Si/SiGe epitaxial-base bipolar technology","authors":"Jeffrey S. Glenn, Mary E. Case, David L. Harame, B. Meyerson, R. Poisson","doi":"10.1109/BIPOL.1995.493894","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493894","url":null,"abstract":"We present Gilbert mixer circuits, fabricated with an epitaxial-base Si/SiGe bipolar technology, having bandwidths of up to 12 GHz and gain-bandwidth products in excess of 22 GHz.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125387943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493863
K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.
{"title":"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry","authors":"K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta","doi":"10.1109/BIPOL.1995.493863","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493863","url":null,"abstract":"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493899
S. Tu, G. Tam, P. Tam, A. Taomoto
A high-speed IGBT fabricated using silicon direct wafer bonding is demonstrated. By controlling the heavily-doped n/sup +/ buffer layer in the device, an on-state voltage drop of 1.4 V at current density of 100 A/cm/sup 2/ and a turn-off fall time less than 100 nanoseconds are achieved.
{"title":"High-speed insulated-gate bipolar transistors fabricated using silicon wafer bonding","authors":"S. Tu, G. Tam, P. Tam, A. Taomoto","doi":"10.1109/BIPOL.1995.493899","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493899","url":null,"abstract":"A high-speed IGBT fabricated using silicon direct wafer bonding is demonstrated. By controlling the heavily-doped n/sup +/ buffer layer in the device, an on-state voltage drop of 1.4 V at current density of 100 A/cm/sup 2/ and a turn-off fall time less than 100 nanoseconds are achieved.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130744862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493856
D. Frey
The design concept of log filters is reviewed. A new second order filter topology which is particularly useful for RF signal processing is introduced with a discussion of its features which meet the needs of RF design.
{"title":"On log domain filtering for RF applications","authors":"D. Frey","doi":"10.1109/BIPOL.1995.493856","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493856","url":null,"abstract":"The design concept of log filters is reviewed. A new second order filter topology which is particularly useful for RF signal processing is introduced with a discussion of its features which meet the needs of RF design.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129365047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493877
P. Popescu, A. Solheim, M. Wight
A monolithic high speed low power transceiver for Manchester encoded data has been designed and integrated using Northern Telecom's advanced 0.8 micron BiCMOS process. The circuit was evaluated for use in high speed low power BiCMOS VLSI for large synchronous digital communication systems with point to point connections running at a rate of 622 Mb/s and operating from +3.3 V.
{"title":"Experimental monolithic high speed transceiver for Manchester encoded data","authors":"P. Popescu, A. Solheim, M. Wight","doi":"10.1109/BIPOL.1995.493877","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493877","url":null,"abstract":"A monolithic high speed low power transceiver for Manchester encoded data has been designed and integrated using Northern Telecom's advanced 0.8 micron BiCMOS process. The circuit was evaluated for use in high speed low power BiCMOS VLSI for large synchronous digital communication systems with point to point connections running at a rate of 622 Mb/s and operating from +3.3 V.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123669696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493890
Weinan Gao, W. Snelgrove, S. Kovacic
A monolithic comparator implemented in a SiGe HBT technology is presented. The circuit employs a resettable slave stage, which was carefully designed to produce return-to-zero output data. Operation with sampling rates up to 5-GHz has been demonstrated. The comparator chip has an input range of 1.5 V, dissipates 89 mW from a 3-volt supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/.
{"title":"A 5-GHz SiGe HBT return-to-zero comparator","authors":"Weinan Gao, W. Snelgrove, S. Kovacic","doi":"10.1109/BIPOL.1995.493890","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493890","url":null,"abstract":"A monolithic comparator implemented in a SiGe HBT technology is presented. The circuit employs a resettable slave stage, which was carefully designed to produce return-to-zero output data. Operation with sampling rates up to 5-GHz has been demonstrated. The comparator chip has an input range of 1.5 V, dissipates 89 mW from a 3-volt supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129182224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493878
M. Elrabaa, M. Elmasry, D. Malhi
A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Operating at 3.3 V, it can drive/receive low-voltage-swing signals with termination voltages ranging from 5 V down to 2 V without using any external reference voltages.
{"title":"A universal 3.3 V 1 GHz BiCMOS transceiver (driver/receiver)","authors":"M. Elrabaa, M. Elmasry, D. Malhi","doi":"10.1109/BIPOL.1995.493878","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493878","url":null,"abstract":"A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Operating at 3.3 V, it can drive/receive low-voltage-swing signals with termination voltages ranging from 5 V down to 2 V without using any external reference voltages.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116568064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493886
M. Corsi, E. Suder, J. Tran, L. Hutter, J.P. Smith, L. Springer
The design aspects of a 9-channel ultra-SCSI transceiver chip are discussed including improvements to speed, power consumption and die size over a previous generation chip, Discussion of the enabling linear BiCMOS technology and an ESD strategy, critical to the function of this class of chip, are presented. Finally, the results of prototype silicon are reviewed.
{"title":"The design and technology requirements of a 9-channel RS485 transceiver for ultra-SCSI applications","authors":"M. Corsi, E. Suder, J. Tran, L. Hutter, J.P. Smith, L. Springer","doi":"10.1109/BIPOL.1995.493886","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493886","url":null,"abstract":"The design aspects of a 9-channel ultra-SCSI transceiver chip are discussed including improvements to speed, power consumption and die size over a previous generation chip, Discussion of the enabling linear BiCMOS technology and an ESD strategy, critical to the function of this class of chip, are presented. Finally, the results of prototype silicon are reviewed.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121810235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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