Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493883
E. Bayer, W. Bucksch, K. Scoones, K. Wagensohner, J. Erdeljac, L. Hutter
A 1.0 micron BiCMOS process, with lateral DMOS as an available process extension, is presented for mixed-signal and power applications, providing a broad range of active and passive components. The DMOS transistor offers 45-60 V capability with Rsp=1.25 m/spl Omega/.cm/sup 2/. The process has been used to build a 5A H-Bridge for automotive applications, the design of which is described in detail.
{"title":"A 1.0 /spl mu/m linear BiCMOS technology with power DMOS capability","authors":"E. Bayer, W. Bucksch, K. Scoones, K. Wagensohner, J. Erdeljac, L. Hutter","doi":"10.1109/BIPOL.1995.493883","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493883","url":null,"abstract":"A 1.0 micron BiCMOS process, with lateral DMOS as an available process extension, is presented for mixed-signal and power applications, providing a broad range of active and passive components. The DMOS transistor offers 45-60 V capability with Rsp=1.25 m/spl Omega/.cm/sup 2/. The process has been used to build a 5A H-Bridge for automotive applications, the design of which is described in detail.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129925107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493877
P. Popescu, A. Solheim, M. Wight
A monolithic high speed low power transceiver for Manchester encoded data has been designed and integrated using Northern Telecom's advanced 0.8 micron BiCMOS process. The circuit was evaluated for use in high speed low power BiCMOS VLSI for large synchronous digital communication systems with point to point connections running at a rate of 622 Mb/s and operating from +3.3 V.
{"title":"Experimental monolithic high speed transceiver for Manchester encoded data","authors":"P. Popescu, A. Solheim, M. Wight","doi":"10.1109/BIPOL.1995.493877","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493877","url":null,"abstract":"A monolithic high speed low power transceiver for Manchester encoded data has been designed and integrated using Northern Telecom's advanced 0.8 micron BiCMOS process. The circuit was evaluated for use in high speed low power BiCMOS VLSI for large synchronous digital communication systems with point to point connections running at a rate of 622 Mb/s and operating from +3.3 V.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123669696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493858
F. Moraveji, M. Musbah
A high-speed, voltage-feedback operational amplifier capable of operating from +/- 1.8 V to +/- 20 V supplies and driving infinite capacitive load is described. Silicon evaluations show 188 MHz bandwidth and 1500 V//spl mu/s slew rate. Die size is 38/spl times/46 square mils in a tiny SOT package. The part has been fabricated on a 40 V poly-emitter complementary bipolar process.
{"title":"A tiny, high-speed, voltage-feedback amplifier stable with all capacitive loads","authors":"F. Moraveji, M. Musbah","doi":"10.1109/BIPOL.1995.493858","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493858","url":null,"abstract":"A high-speed, voltage-feedback operational amplifier capable of operating from +/- 1.8 V to +/- 20 V supplies and driving infinite capacitive load is described. Silicon evaluations show 188 MHz bandwidth and 1500 V//spl mu/s slew rate. Die size is 38/spl times/46 square mils in a tiny SOT package. The part has been fabricated on a 40 V poly-emitter complementary bipolar process.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131977484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493890
Weinan Gao, W. Snelgrove, S. Kovacic
A monolithic comparator implemented in a SiGe HBT technology is presented. The circuit employs a resettable slave stage, which was carefully designed to produce return-to-zero output data. Operation with sampling rates up to 5-GHz has been demonstrated. The comparator chip has an input range of 1.5 V, dissipates 89 mW from a 3-volt supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/.
{"title":"A 5-GHz SiGe HBT return-to-zero comparator","authors":"Weinan Gao, W. Snelgrove, S. Kovacic","doi":"10.1109/BIPOL.1995.493890","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493890","url":null,"abstract":"A monolithic comparator implemented in a SiGe HBT technology is presented. The circuit employs a resettable slave stage, which was carefully designed to produce return-to-zero output data. Operation with sampling rates up to 5-GHz has been demonstrated. The comparator chip has an input range of 1.5 V, dissipates 89 mW from a 3-volt supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129182224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493887
T. Shu, K. Bacrania, R. Gokhale
A BiCMOS fully-differential, 10-bit, 40 MHz pipelined ADC has been developed. The ADC can digitize not only a fully-differential but also a single-ended signal over a wide input range with little variation in performance. At f/sub s/=40 MHz, the ADC exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW from a single 5-V supply.
{"title":"A BiCMOS fully-differential 10-bit 40 MHz pipelined ADC","authors":"T. Shu, K. Bacrania, R. Gokhale","doi":"10.1109/BIPOL.1995.493887","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493887","url":null,"abstract":"A BiCMOS fully-differential, 10-bit, 40 MHz pipelined ADC has been developed. The ADC can digitize not only a fully-differential but also a single-ended signal over a wide input range with little variation in performance. At f/sub s/=40 MHz, the ADC exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW from a single 5-V supply.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114375009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493859
S. Laux, M. Fischetti
An overview of three methods currently employed in advanced semiconductor device simulation is given, together with results for a model n/sup +/-n-n/sup +/ structure. The Monte Carlo, energy transport and spherical harmonic expansion methods are discussed from the perspective of a Monte Carlo enthusiast.
{"title":"Transport models for advanced device simulation-truth or consequences?","authors":"S. Laux, M. Fischetti","doi":"10.1109/BIPOL.1995.493859","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493859","url":null,"abstract":"An overview of three methods currently employed in advanced semiconductor device simulation is given, together with results for a model n/sup +/-n-n/sup +/ structure. The Monte Carlo, energy transport and spherical harmonic expansion methods are discussed from the perspective of a Monte Carlo enthusiast.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126549279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493862
J. Schutz, M. Bohr
A 0.35 /spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5 V version offers lower power and higher performance. A 3.3 V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6 /spl mu/m 3.3 V BiCMOS process. The design process for converting an existing production worthy 0.6 /spl mu/m 3.3 V BiCMOS design is described. The silicon results are described.
采用高性能晶体管和四层平面化金属互连技术，开发了一种0.35 /spl mu/m的逻辑技术。2.5 V版本提供更低的功耗和更高的性能。3.3 V BiCMOS版本已经过优化，可与以前在0.6 /spl mu/m 3.3 V BiCMOS工艺中实现的设计兼容。介绍了现有生产价值0.6 /spl mu/m 3.3 V BiCMOS设计的改造设计过程。描述了硅的结果。
{"title":"A high performance 0.35 /spl mu/m 3.3 V BiCMOS technology optimized for product porting from a 0.6 /spl mu/m 3.3 V BiCMOS technology","authors":"J. Schutz, M. Bohr","doi":"10.1109/BIPOL.1995.493862","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493862","url":null,"abstract":"A 0.35 /spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5 V version offers lower power and higher performance. A 3.3 V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6 /spl mu/m 3.3 V BiCMOS process. The design process for converting an existing production worthy 0.6 /spl mu/m 3.3 V BiCMOS design is described. The silicon results are described.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126635592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493874
K. Inou, Y. Katsumata, S. Matsuda, H. Naruse, H. Sugaya, H. Iwai
An in-situ highly doped arsenic polysilicon emitter technology has been developed as a way to improve the degradation of electrical characteristics suffered by narrow emitter bipolar transistors due to the plug effect. We have experimentally confirmed that transistors fabricated with the new technique have good electrical characteristics.
{"title":"Improvement of narrow emitter bipolar transistor performance by in-situ highly doped arsenic polysilicon technique","authors":"K. Inou, Y. Katsumata, S. Matsuda, H. Naruse, H. Sugaya, H. Iwai","doi":"10.1109/BIPOL.1995.493874","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493874","url":null,"abstract":"An in-situ highly doped arsenic polysilicon emitter technology has been developed as a way to improve the degradation of electrical characteristics suffered by narrow emitter bipolar transistors due to the plug effect. We have experimentally confirmed that transistors fabricated with the new technique have good electrical characteristics.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121455073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493893
M. Pfost, H. Rein, T. Holzwarth
The contribution of the p/sup -/ substrate and channel stopper on the equivalent circuits of Si-bipolar transistors and bond pads are theoretically and experimentally investigated up to very high frequencies. Equivalent substrate circuits are derived and verified by numerical simulation using a new computer program. The validity of both the numerical simulation results and the equivalent circuits are checked by on-wafer measurements up to 20 GHz.
{"title":"Modeling of the substrate effect in high-speed Si-bipolar ICs","authors":"M. Pfost, H. Rein, T. Holzwarth","doi":"10.1109/BIPOL.1995.493893","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493893","url":null,"abstract":"The contribution of the p/sup -/ substrate and channel stopper on the equivalent circuits of Si-bipolar transistors and bond pads are theoretically and experimentally investigated up to very high frequencies. Equivalent substrate circuits are derived and verified by numerical simulation using a new computer program. The validity of both the numerical simulation results and the equivalent circuits are checked by on-wafer measurements up to 20 GHz.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121462845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/BIPOL.1995.493882
K. Joardar
A new methodology for measuring p/n junction capacitance is demonstrated. The method is dc based making it suitable for use in automated high volume measurements. The validity of the technique is supported by both simulated and experimentally measured data.
{"title":"A new technique for measuring junction capacitance in bipolar transistors","authors":"K. Joardar","doi":"10.1109/BIPOL.1995.493882","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493882","url":null,"abstract":"A new methodology for measuring p/n junction capacitance is demonstrated. The method is dc based making it suitable for use in automated high volume measurements. The validity of the technique is supported by both simulated and experimentally measured data.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131772940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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