Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328679
G. Davydov, D. Boychenko, Daria V. Pechenkina, A. Tararaksin, T. Kritskaya, A. Polokhov
The SEB test results of 3 kinds and 17 types of power MOSFET were systemized in this work. Several common features of radiation behavior were found for tested devices. The approach to increase SEB sustainability area of MOSFET-based electronic devices was discussed.
{"title":"Safe Operation Area Of Trench-Gate And Low-Charge Power MOSFET","authors":"G. Davydov, D. Boychenko, Daria V. Pechenkina, A. Tararaksin, T. Kritskaya, A. Polokhov","doi":"10.1109/RADECS45761.2018.9328679","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328679","url":null,"abstract":"The SEB test results of 3 kinds and 17 types of power MOSFET were systemized in this work. Several common features of radiation behavior were found for tested devices. The approach to increase SEB sustainability area of MOSFET-based electronic devices was discussed.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115441698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The soft breakdown (SBD) characteristic and self-heating effect (SHE) suppression of 400V SOI NLDMOSFETs after irradiation under different bias conditions is discovered through experiments. The mechanisms for these phenomena are analysed and confirmed by TCAD simulations.
通过实验发现400V SOI nldmosfet在不同偏置条件下辐照后的软击穿(SBD)特性和自热效应抑制(SHE)。对这些现象的机理进行了分析，并通过TCAD模拟加以证实。
{"title":"TID Effects on Soft-breakdown and Self-heating Characteristics of 400V SOI NLDMOSFETs","authors":"Lei Shu, Liang Wang, Xin Zhou, Yuan Li, Tongde Li, Zhangyi’an Yuan, Cheng-Long Sui, Yuanfu Zhao","doi":"10.1109/RADECS45761.2018.9328663","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328663","url":null,"abstract":"The soft breakdown (SBD) characteristic and self-heating effect (SHE) suppression of 400V SOI NLDMOSFETs after irradiation under different bias conditions is discovered through experiments. The mechanisms for these phenomena are analysed and confirmed by TCAD simulations.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114374133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328704
S. Hoeffgen, Mirko Liebender, M. Baum, Christopher Carl, O. Felden, Tobias Kündgen, W. Lennartz, S. Metzger, Samuel Plettner, Friedrich Schün
The NXP P4080 processor is tested for SEE using a proton beam of up to 500 MeV. Single and multiple bit upsets of the L2 and L3 cache were measured as well as core crashes with different signatures.
{"title":"Proton Testing of the NXP P4080 Processor at the COSY Accelerator","authors":"S. Hoeffgen, Mirko Liebender, M. Baum, Christopher Carl, O. Felden, Tobias Kündgen, W. Lennartz, S. Metzger, Samuel Plettner, Friedrich Schün","doi":"10.1109/RADECS45761.2018.9328704","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328704","url":null,"abstract":"The NXP P4080 processor is tested for SEE using a proton beam of up to 500 MeV. Single and multiple bit upsets of the L2 and L3 cache were measured as well as core crashes with different signatures.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A radiation-hardened-by-design (RHBD) phase-locked loop (PLL) designed in 0.13-µm CMOS is demonstrated to effectively mitigate the single-event transient (SET) effect. In this paper, a novel Current Limiter circuit Controlled by Comparators (CLCBC) is proposed to improve SET tolerance of the Charge-Pump (CP). Further a SET tolerant Voltage-Controlled Oscillator (VCO) based on an interleaved architecture is also presented. The CLCBC features in being able to detect the abnormal current surged at the CP output node as a result of a SET strike and then to keep this abnormal current from flowing into the low pass filter (LPF) by a high resolution and fast compensation scheme. The VCO consists of a 4-stage interleaved delay buffer implemented to perform the Majority Decision Voting functions without incurring additional signal delay. Such a VCO can generate symmetric multi-phase outputs. Simulation results show that, with deposited charges of 2650fC, the output variation of the CP/ LPF hardened by the proposed CLCBC is reduced by 84.5%, in comparison to the previous work. For the RHBD PLL designed, the perturbation of the VCO control voltage is reduced by 95.6%, while the PLL recovery time is reduced by 68.9%, and the period variation range of the output is reduced by 97%, all with reference to the baseline PLL unhardened. Moreover, the jitter performance of the proposed RHBD PLL remains unaffected and is nearly the same as that of the baseline PLL unhardened.
{"title":"A SET Harden Phase-Locked Loop with Perturbation Compensated Charge Pump & Interleaved VCO","authors":"Yuan-feng Wei, Haigang Yang, Tianwen Li, Zhujia Chen","doi":"10.1109/RADECS45761.2018.9328650","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328650","url":null,"abstract":"A radiation-hardened-by-design (RHBD) phase-locked loop (PLL) designed in 0.13-µm CMOS is demonstrated to effectively mitigate the single-event transient (SET) effect. In this paper, a novel Current Limiter circuit Controlled by Comparators (CLCBC) is proposed to improve SET tolerance of the Charge-Pump (CP). Further a SET tolerant Voltage-Controlled Oscillator (VCO) based on an interleaved architecture is also presented. The CLCBC features in being able to detect the abnormal current surged at the CP output node as a result of a SET strike and then to keep this abnormal current from flowing into the low pass filter (LPF) by a high resolution and fast compensation scheme. The VCO consists of a 4-stage interleaved delay buffer implemented to perform the Majority Decision Voting functions without incurring additional signal delay. Such a VCO can generate symmetric multi-phase outputs. Simulation results show that, with deposited charges of 2650fC, the output variation of the CP/ LPF hardened by the proposed CLCBC is reduced by 84.5%, in comparison to the previous work. For the RHBD PLL designed, the perturbation of the VCO control voltage is reduced by 95.6%, while the PLL recovery time is reduced by 68.9%, and the period variation range of the output is reduced by 97%, all with reference to the baseline PLL unhardened. Moreover, the jitter performance of the proposed RHBD PLL remains unaffected and is nearly the same as that of the baseline PLL unhardened.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328700
M. Hofbauer, B. Steindl, K. Schneider-Hornstein, B. Goll, K. Voss, H. Zimmermann
Single-event transients (SETs) in a PIN photodiode and a single-photon avalanche diode (SPAD), both fabricated in the same 0.35μm CMOS process, are compared under heavy ion irradiation. The experimental results suggest that mainly the low-doped epitaxial layer defines the amount of collected charge. High current peaks at the output of the photodetectors, necessitate precautions in the quencher and read-out circuit design.
{"title":"Single-Event Transients in a PIN Photodiode and a Single-Photon Avalanche Diode Integrated in 0.35μm CMOS","authors":"M. Hofbauer, B. Steindl, K. Schneider-Hornstein, B. Goll, K. Voss, H. Zimmermann","doi":"10.1109/RADECS45761.2018.9328700","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328700","url":null,"abstract":"Single-event transients (SETs) in a PIN photodiode and a single-photon avalanche diode (SPAD), both fabricated in the same 0.35μm CMOS process, are compared under heavy ion irradiation. The experimental results suggest that mainly the low-doped epitaxial layer defines the amount of collected charge. High current peaks at the output of the photodetectors, necessitate precautions in the quencher and read-out circuit design.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126238389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328665
S. Azimi, B. Du, L. Sterpone
Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. The decreasing of device feature size leads to an increasing of the device sensitivity against Single Event Effects (SEEs), especially Single Event Transients (SETs), induced particle strikes within the device silicon structure. Flash-based FPGA is a golden core for aerospace safety critical applications; however, traditional SET mitigation solutions, such as filter insertion, can lead to performance degradation of the implemented design. In this paper, we provide a new implementation flow that is able to evaluate the SET phenomena considering its specific convergence case and effectively mitigate the SETs without introducing any performance penalization to the original netlist. Experimental results on different sets of benchmark circuits demonstrated the mitigation of SET events without affecting the timing performances of the circuits.
{"title":"A Zero-Timing Overhead SET Mitigation Approach for Flash-based FPGAs","authors":"S. Azimi, B. Du, L. Sterpone","doi":"10.1109/RADECS45761.2018.9328665","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328665","url":null,"abstract":"Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. The decreasing of device feature size leads to an increasing of the device sensitivity against Single Event Effects (SEEs), especially Single Event Transients (SETs), induced particle strikes within the device silicon structure. Flash-based FPGA is a golden core for aerospace safety critical applications; however, traditional SET mitigation solutions, such as filter insertion, can lead to performance degradation of the implemented design. In this paper, we provide a new implementation flow that is able to evaluate the SET phenomena considering its specific convergence case and effectively mitigate the SETs without introducing any performance penalization to the original netlist. Experimental results on different sets of benchmark circuits demonstrated the mitigation of SET events without affecting the timing performances of the circuits.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134192664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328720
A. Barnard, F. Smit, R. Neveling, W.H. Steyn
The development and verification of the Single-Event-Effect (SEE) Proton Testing of electronic systems facility at iThemba LABS using a novel Beam Loss Monitor (BLM) based dosimetry system is presented. This is the first high-energy proton SEE testing facility in Africa and the Southern hemisphere.
{"title":"SEE Proton Testing Facility at iThemba LABS","authors":"A. Barnard, F. Smit, R. Neveling, W.H. Steyn","doi":"10.1109/RADECS45761.2018.9328720","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328720","url":null,"abstract":"The development and verification of the Single-Event-Effect (SEE) Proton Testing of electronic systems facility at iThemba LABS using a novel Beam Loss Monitor (BLM) based dosimetry system is presented. This is the first high-energy proton SEE testing facility in Africa and the Southern hemisphere.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"56 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124316363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328716
D. Bamber, K. Ryden, D. Tye, C. Underwood
This paper describes the development and testing of a new radiation monitor for MEO and GEO orbits utilizing novel design techniques including dual-footprinting of COTS and radiation hardened components. Its sensor suite consists of proton and heavy ion particle telescopes, ionizing dose sensors and current sensing plates for deep dielectric charge monitoring.
{"title":"Development and Calibration of a New, Low Cost Radiation Monitor for High Radiation Orbits","authors":"D. Bamber, K. Ryden, D. Tye, C. Underwood","doi":"10.1109/RADECS45761.2018.9328716","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328716","url":null,"abstract":"This paper describes the development and testing of a new radiation monitor for MEO and GEO orbits utilizing novel design techniques including dual-footprinting of COTS and radiation hardened components. Its sensor suite consists of proton and heavy ion particle telescopes, ionizing dose sensors and current sensing plates for deep dielectric charge monitoring.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134125769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328725
L. Tambara, J. Andersson, F. Sturesson, J. Jalle, R. Sharp
The Cobham Gaisler LEON4FT is a fault-tolerant synthesizable VHDL model of a 32-bit processor core, compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for System-on-Chip (SoC) designs. The processor is the basis of the Cobham Gaisler GR740, a radiation-tolerant SoC that features a quad-core LEON4FT processor, as well as several other peripherals. The Microsemi RTG4 Field Programmable Gate Array (FPGA) is fabricated using a low-power, 65 nm CMOS Flash technology, which is known to provide higher immunity to radiation-induced errors than SRAM-based FPGAs. This work performs a dynamic test of RTG4 FPGA embedding a LEON4FT-based SoC under heavy ion-induced single event effects. The results obtained demonstrate the effectiveness of the fault-tolerant techniques adopted at both device and design levels in a real application.
{"title":"Dynamic Heavy Ion SEE Testing of Microsemi RTG4 Flash-based FPGA Embedding a LEON4FT-based SoC","authors":"L. Tambara, J. Andersson, F. Sturesson, J. Jalle, R. Sharp","doi":"10.1109/RADECS45761.2018.9328725","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328725","url":null,"abstract":"The Cobham Gaisler LEON4FT is a fault-tolerant synthesizable VHDL model of a 32-bit processor core, compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for System-on-Chip (SoC) designs. The processor is the basis of the Cobham Gaisler GR740, a radiation-tolerant SoC that features a quad-core LEON4FT processor, as well as several other peripherals. The Microsemi RTG4 Field Programmable Gate Array (FPGA) is fabricated using a low-power, 65 nm CMOS Flash technology, which is known to provide higher immunity to radiation-induced errors than SRAM-based FPGAs. This work performs a dynamic test of RTG4 FPGA embedding a LEON4FT-based SoC under heavy ion-induced single event effects. The results obtained demonstrate the effectiveness of the fault-tolerant techniques adopted at both device and design levels in a real application.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"329 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133196297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/RADECS45761.2018.9328697
V. Bezhenova, A. Michalowska-Forsyth
Enclosed layout is an effective way to mitigate radiation induced leakage current in NMOS transistors. The unconventional shape of such device makes modeling a challenging task. Evaluation of equivalent aspect ratio estimation is complicated by additional stress effects, such as STI stress. We incorporate the STI stress effect into simulation for enclosed layout transistor in order to evaluate accuracy of two equivalent aspect ratio evaluation models: the well-known mid-line approximation and the recently introduced isosceles trapezoid approximation.
{"title":"Modeling of Annular Gate MOS Transistors","authors":"V. Bezhenova, A. Michalowska-Forsyth","doi":"10.1109/RADECS45761.2018.9328697","DOIUrl":"https://doi.org/10.1109/RADECS45761.2018.9328697","url":null,"abstract":"Enclosed layout is an effective way to mitigate radiation induced leakage current in NMOS transistors. The unconventional shape of such device makes modeling a challenging task. Evaluation of equivalent aspect ratio estimation is complicated by additional stress effects, such as STI stress. We incorporate the STI stress effect into simulation for enclosed layout transistor in order to evaluate accuracy of two equivalent aspect ratio evaluation models: the well-known mid-line approximation and the recently introduced isosceles trapezoid approximation.","PeriodicalId":248855,"journal":{"name":"2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115567653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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