Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362910
W. H. Becker
Time-dependent dielectric breakdown is an important failure mode for silicon integrated circuits. This paper presents a study of such failures in a MNOS capacitor used on a bipolar operational amplifier IC. It is shown that the cause of these failures is point defects in the Si3N4 film. The number of defective capacitors in a given population can be estimated by a silicon "pinhole etch" decoration technique. The failure of these defects is very dependent on voltage and each has a definite threshold for failure. This threshold varies from defect to defect. Aging at a fixed voltage stress causes rapid failure of all those defects with thresholds below the stress. The defects with higher thresholds do not fail. Voltage step-stress data is. presented to show that the defects have a definite distribution of failure thresholds. This distribution is approximately normal with a median of 40 volts. Thus most defects fail well below the 120 volt dielectric breakdown of the MNOS structure. For defects aged above their failure threshold, the time-to-failure distribution is a strong function of the overvoltage (VOV); i.e., the amount the aging voltage exceeds the defect threshold. For VOV of a few volts, the time-to-failure distribution is log-normal with a median of about 10 hours and sigma of about 2. For higher overvoltages, the median life decreases rapidly - approximately as 1/VOV4. Examples of long-term failure rate. calculations are given and compared with experimental data.
{"title":"Time and Voltage Dependence of Failure in MNOS Capacitors Containing Point Defects","authors":"W. H. Becker","doi":"10.1109/IRPS.1980.362910","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362910","url":null,"abstract":"Time-dependent dielectric breakdown is an important failure mode for silicon integrated circuits. This paper presents a study of such failures in a MNOS capacitor used on a bipolar operational amplifier IC. It is shown that the cause of these failures is point defects in the Si3N4 film. The number of defective capacitors in a given population can be estimated by a silicon \"pinhole etch\" decoration technique. The failure of these defects is very dependent on voltage and each has a definite threshold for failure. This threshold varies from defect to defect. Aging at a fixed voltage stress causes rapid failure of all those defects with thresholds below the stress. The defects with higher thresholds do not fail. Voltage step-stress data is. presented to show that the defects have a definite distribution of failure thresholds. This distribution is approximately normal with a median of 40 volts. Thus most defects fail well below the 120 volt dielectric breakdown of the MNOS structure. For defects aged above their failure threshold, the time-to-failure distribution is a strong function of the overvoltage (VOV); i.e., the amount the aging voltage exceeds the defect threshold. For VOV of a few volts, the time-to-failure distribution is log-normal with a median of about 10 hours and sigma of about 2. For higher overvoltages, the median life decreases rapidly - approximately as 1/VOV4. Examples of long-term failure rate. calculations are given and compared with experimental data.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125031596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362921
C. Sie
Charles H. Sie Xerox Corp. 701 S. Aviation Blvd. El Segundo, Ca. 90245 With the development of radio, television, computers and microelectronics, electronic technology has rapidly evolved into a catalytic force in *sustaining industrial growth. As the electronic industry matures, product manufacturing cost and product quality are becoming determining factors for the product's competitiveness. The relationship between manufacturing cost and quality can either be a direct one (increased cost for higher quality) or an inverse one (decreased cost for. *higher quality) very much dependent upon the strategy chosen-to improve the product's quality. By increasing the stringency of the screening process,and therefore the cost, in the manufacturing flow, the product quality can be enhanced. However, the same result can be achieved in a.cost-. effective manner. if corrective action i's developed .based on the analysis of components failing in the screening process, shown schematically in Figure 1. The inverse cost-quality relationship comes about when i.mplementing corrective action, the screening rejection in the manufacturing flow and failure i-n the fie.ld will be reduced; therefore, correspondingly the manufacturing cost will be lowered and the quality improved. Usuallythe burden of component failure analysis and cor-rective action'development can be leveraged by the product volume or generically amortized across product lines. Component failure can truly be caused by an intermittent or. degraded component, or it can' be the symptom of a problem-which relates to circuit compatibility, to test coverage, or to manufacturing process. It is absolutely essential to uncover the real cause of the failure as evidenced by the responsiveness of the implemented corrective action; therefore, failure analysis should always be 'a closed loop activity. The effectiveness of the-failure analysis group can be greatly enhanced when its staff is multi-disciplinary including device physics, circuit des-ign and testing. Lastly, a highly focused component failure analysis activity will serve as a focal point for accountability, specially in a large organization. FIGURE 1. ROIL OF FAI URE ANALYSIS IN CLOSED LOOP ENGINFERING
{"title":"Perspectives in Component Failure Analysis","authors":"C. Sie","doi":"10.1109/IRPS.1980.362921","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362921","url":null,"abstract":"Charles H. Sie Xerox Corp. 701 S. Aviation Blvd. El Segundo, Ca. 90245 With the development of radio, television, computers and microelectronics, electronic technology has rapidly evolved into a catalytic force in *sustaining industrial growth. As the electronic industry matures, product manufacturing cost and product quality are becoming determining factors for the product's competitiveness. The relationship between manufacturing cost and quality can either be a direct one (increased cost for higher quality) or an inverse one (decreased cost for. *higher quality) very much dependent upon the strategy chosen-to improve the product's quality. By increasing the stringency of the screening process,and therefore the cost, in the manufacturing flow, the product quality can be enhanced. However, the same result can be achieved in a.cost-. effective manner. if corrective action i's developed .based on the analysis of components failing in the screening process, shown schematically in Figure 1. The inverse cost-quality relationship comes about when i.mplementing corrective action, the screening rejection in the manufacturing flow and failure i-n the fie.ld will be reduced; therefore, correspondingly the manufacturing cost will be lowered and the quality improved. Usuallythe burden of component failure analysis and cor-rective action'development can be leveraged by the product volume or generically amortized across product lines. Component failure can truly be caused by an intermittent or. degraded component, or it can' be the symptom of a problem-which relates to circuit compatibility, to test coverage, or to manufacturing process. It is absolutely essential to uncover the real cause of the failure as evidenced by the responsiveness of the implemented corrective action; therefore, failure analysis should always be 'a closed loop activity. The effectiveness of the-failure analysis group can be greatly enhanced when its staff is multi-disciplinary including device physics, circuit des-ign and testing. Lastly, a highly focused component failure analysis activity will serve as a focal point for accountability, specially in a large organization. FIGURE 1. ROIL OF FAI URE ANALYSIS IN CLOSED LOOP ENGINFERING","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133569743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362939
A. Marques
Field programmable ROMs provide the electronics industry with a more versatile memory function by postponing final processing until after the seal operation. This report will focus on (1) a failure mechanism, unreported until now, which concerns the self-programming of an unprogrammed nichrome link during operation of the PROM under normal "read" conditions, and (2) an electrical screen for culling out links with a high probability for self-programming. The occurrence of these failures after many days of burn-in will be discussed along with the link programming set-up, failure analysis data, and documented history of high reliability screening procedures. It is important to note that these PROMs were programmed to the vendor's specifications, except that a single pulse fusing criterion was used. Additionally, an elaborate verification scheme followed each fusing attempt as a check for errors. Based on the results of the failure analysis study, the failures which are considered to be escapes from the die visual inspection screen will be shown to be due to a wafer process-related fault. A new electrical test procedure will be proposed which can be used to augment or partially supplant the visual screen now in practice. A general test scheme will be presented so that the prerequisite conditions of applicability to other manufacturers' PROMs can be defined. The general scheme will be then applied to the specific circuit implementation used by the manufacturer of the aforementioned failures.
{"title":"Electrical Inspection of PROM Memory Links","authors":"A. Marques","doi":"10.1109/IRPS.1980.362939","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362939","url":null,"abstract":"Field programmable ROMs provide the electronics industry with a more versatile memory function by postponing final processing until after the seal operation. This report will focus on (1) a failure mechanism, unreported until now, which concerns the self-programming of an unprogrammed nichrome link during operation of the PROM under normal \"read\" conditions, and (2) an electrical screen for culling out links with a high probability for self-programming. The occurrence of these failures after many days of burn-in will be discussed along with the link programming set-up, failure analysis data, and documented history of high reliability screening procedures. It is important to note that these PROMs were programmed to the vendor's specifications, except that a single pulse fusing criterion was used. Additionally, an elaborate verification scheme followed each fusing attempt as a check for errors. Based on the results of the failure analysis study, the failures which are considered to be escapes from the die visual inspection screen will be shown to be due to a wafer process-related fault. A new electrical test procedure will be proposed which can be used to augment or partially supplant the visual screen now in practice. A general test scheme will be presented so that the prerequisite conditions of applicability to other manufacturers' PROMs can be defined. The general scheme will be then applied to the specific circuit implementation used by the manufacturer of the aforementioned failures.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131434683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362938
A. Hart, Tsuo-Tong Teng, A. McKenna
Reliability prediction of MOS LSI devices by testing at elevated temperature can be influenced by electrostatic discharge and electrical overstress conditions during the test period. MOS devices that used junction diodes in the input protection structure were found to be more susceptible to failure from electrostatic discharge in 125°C ambient temperature than at 25°C. Failure analysis and modeling indicate that this effect is more severe for MOS LSI devices than for bipolar devices due to the doping levels used in the MOS technology. These effects will impact accelerated life testing, simulation testing of electronic systems to be operated at elevated temperatures and failure analysis techniques performed at elevated temperatures.
MOS LSI器件在高温下的可靠性预测会受到静电放电和电气过应力条件的影响。在输入保护结构中使用结二极管的MOS器件在125°C环境温度下比在25°C环境温度下更容易受到静电放电的影响。失效分析和建模表明，由于MOS技术中使用的掺杂水平，这种影响对MOS LSI器件比双极器件更为严重。这些影响将影响在高温下运行的电子系统的加速寿命测试、模拟测试以及在高温下进行的失效分析技术。
{"title":"Reliability Influences from Electrical Overstress on LSI Devices","authors":"A. Hart, Tsuo-Tong Teng, A. McKenna","doi":"10.1109/IRPS.1980.362938","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362938","url":null,"abstract":"Reliability prediction of MOS LSI devices by testing at elevated temperature can be influenced by electrostatic discharge and electrical overstress conditions during the test period. MOS devices that used junction diodes in the input protection structure were found to be more susceptible to failure from electrostatic discharge in 125°C ambient temperature than at 25°C. Failure analysis and modeling indicate that this effect is more severe for MOS LSI devices than for bipolar devices due to the doping levels used in the MOS technology. These effects will impact accelerated life testing, simulation testing of electronic systems to be operated at elevated temperatures and failure analysis techniques performed at elevated temperatures.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116044120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362912
J. Bindell, J. McGinn
A voltage contrast technique which generates a video display of data movement within an active integrated circuit has been developed. The technique utilizes a microprocessor to exercise and control the flow of data within an integrated circuit so that SEM images of sequential logic states can be generated without the use of electron beam blanking.
{"title":"Voltage Contrast SEM Observations with Microprocessor Controlled Device Timing","authors":"J. Bindell, J. McGinn","doi":"10.1109/IRPS.1980.362912","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362912","url":null,"abstract":"A voltage contrast technique which generates a video display of data movement within an active integrated circuit has been developed. The technique utilizes a microprocessor to exercise and control the flow of data within an integrated circuit so that SEM images of sequential logic states can be generated without the use of electron beam blanking.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"458 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124549852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362946
T. Welsher, J. Mitchell, D. J. Lando
In papers presented at the 1979 IRPS it was reported that failure of printed-circuit boards due to conductive anodic filaments (CAF) posed a potential reliability problem for applications involving high circuit density, hostile environments and/or low power dissipation. In this paper, the results of a study to characterize the CAF phenomenon with respect to temperature, humidity, applied voltage, and other factors are reported. Further aspects of the mechanism of failure are explored. The results of extensive testing of a CAF-resistant material, triazine/glass, are presented.
{"title":"CAF in Composite Printed-Circuit Substrates: Characterization, Modeling and a Resistant Material","authors":"T. Welsher, J. Mitchell, D. J. Lando","doi":"10.1109/IRPS.1980.362946","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362946","url":null,"abstract":"In papers presented at the 1979 IRPS it was reported that failure of printed-circuit boards due to conductive anodic filaments (CAF) posed a potential reliability problem for applications involving high circuit density, hostile environments and/or low power dissipation. In this paper, the results of a study to characterize the CAF phenomenon with respect to temperature, humidity, applied voltage, and other factors are reported. Further aspects of the mechanism of failure are explored. The results of extensive testing of a CAF-resistant material, triazine/glass, are presented.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"9 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123670090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362913
A. Dermarderosian
This paper details a novel approach to the detection of cracks in ceramic semiconductor packages. The technique is extremely fast and has been designed to be a cost effective method of performing crack detection for high volume production applications as well as for traditional failure analysis. The test does not require any special lighting nor any optical magnification. It is capable of detecting cracks as fine as one-tenth of a micron in width. Although developed for a specific situation, the test may be useful for a wide variety of other applications.
{"title":"The Detection of Cracks in Ceramic Packages by Vapor Condensation","authors":"A. Dermarderosian","doi":"10.1109/IRPS.1980.362913","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362913","url":null,"abstract":"This paper details a novel approach to the detection of cracks in ceramic semiconductor packages. The technique is extremely fast and has been designed to be a cost effective method of performing crack detection for high volume production applications as well as for traditional failure analysis. The test does not require any special lighting nor any optical magnification. It is capable of detecting cracks as fine as one-tenth of a micron in width. Although developed for a specific situation, the test may be useful for a wide variety of other applications.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114255940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362919
J. Lloyd, G. Prokop, M.E. Molchen
The degree of correlation between time to failure by electromigration stressing and pulse ohmic - non-linearity was found to depend markedly on the stress conditions. Only the highest stress and highest joule heating resulted in good correlation. Also, a simple resistance measurement was found to correlate as well with time to failure as pulse non-linearity. It was concluded that pulse non-linearity techniques are of limited usefulness as a reliability tool for all but those applications where severe joule heating is present.
{"title":"Evaluation of the Pulse Ohmic Non-Linearity Technique as a Reliability Tool for Predicting Susceptibility to Electromigration Damage","authors":"J. Lloyd, G. Prokop, M.E. Molchen","doi":"10.1109/IRPS.1980.362919","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362919","url":null,"abstract":"The degree of correlation between time to failure by electromigration stressing and pulse ohmic - non-linearity was found to depend markedly on the stress conditions. Only the highest stress and highest joule heating resulted in good correlation. Also, a simple resistance measurement was found to correlate as well with time to failure as pulse non-linearity. It was concluded that pulse non-linearity techniques are of limited usefulness as a reliability tool for all but those applications where severe joule heating is present.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114772498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362929
M. Omori, J. Wholey, J. Gibbons
An initial study at Avantek has established that static accelerated life tests on GaAs FET devices predict about an order of magnitude longer life than active accelerated life tests (tests at elevated temperatures with normal operating bias applied). In order to obtain reliable data, it is necessary to ensure that the devices do not oscillate while under test. To avoid oscillations the drain and source of the FET must be terminated in impedances which are controlled from DC to Fmax. For many of the devices tested Fmas was as high as 80 GHz. A test fixture with 50-ohm ceramic microstrip lines connected to the source and drain proved successful. The packaged GaAs FET and one end of each ceramic microstrip line was attached to a temperature-controlled heated stage. The GaAs FETs used in these tests were fabricated with AuGe/Ni/Au ohmic contacts and TiW/Au overlay metal. An identical layer of TiW/Au was also used for the Schottky barrier gate. They were then her-metically sealed in metal ceramic packages. The failure criterion used to define end of life was a 1-dB degradation of S21 (insertion gain in 50-ohm system) measured at 6 GHz. Insertion gain, S21 was measured with bias conditions which were typically optimum for low noise so long as this current was below Idss. If after stress, Idss was below the current which was previously optimum for noise figure, then measurements would be made at Idss. The average activation energy of the Arrhenius curve of this failure mode was 1.
{"title":"Accelerated Active Life Test of GaAs FET and a New Failure Mode","authors":"M. Omori, J. Wholey, J. Gibbons","doi":"10.1109/IRPS.1980.362929","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362929","url":null,"abstract":"An initial study at Avantek has established that static accelerated life tests on GaAs FET devices predict about an order of magnitude longer life than active accelerated life tests (tests at elevated temperatures with normal operating bias applied). In order to obtain reliable data, it is necessary to ensure that the devices do not oscillate while under test. To avoid oscillations the drain and source of the FET must be terminated in impedances which are controlled from DC to Fmax. For many of the devices tested Fmas was as high as 80 GHz. A test fixture with 50-ohm ceramic microstrip lines connected to the source and drain proved successful. The packaged GaAs FET and one end of each ceramic microstrip line was attached to a temperature-controlled heated stage. The GaAs FETs used in these tests were fabricated with AuGe/Ni/Au ohmic contacts and TiW/Au overlay metal. An identical layer of TiW/Au was also used for the Schottky barrier gate. They were then her-metically sealed in metal ceramic packages. The failure criterion used to define end of life was a 1-dB degradation of S21 (insertion gain in 50-ohm system) measured at 6 GHz. Insertion gain, S21 was measured with bias conditions which were typically optimum for low noise so long as this current was below Idss. If after stress, Idss was below the current which was previously optimum for noise figure, then measurements would be made at Idss. The average activation energy of the Arrhenius curve of this failure mode was 1.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130599497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-04-01DOI: 10.1109/IRPS.1980.362908
J. Prince, J. Lathrop, R. A. Hartman
Results of a program to investigate the reliability characteristics of unencapsulated low-cost terrestrial solar cells using accelerated stress testing are presented. A total of seven types of cells were investigated. Results of extended (~ 1 year) bias-temperature stress testing of four cell types were obtained. An additional three cell types, including cells fabricated using the advanced technologies of ribbon-grown silicon and polycrystalline silicon, were subjected to various combinations of bias, temperature cycling stress tests. The spectrum of tests used was based on previous years' work, but differs from that used earlier. An electrical measurement procedure capable of distinguishing small changes in cell electrical parameters was used. Significant degradation was shown by some cell types in some stress tests. Other combinations of cell types and stress tests resulted in no detectable cell degradation. Analysis of the origins of the differences in degradation is continuing. Second quadrant characteristics of some cell types were also investigated in order to establish the electrical behavior of cells which may be exposed to this stress condition in modules deployed in the field.
{"title":"Reliability Degradation Indicators being Observed on Terrestrial Silicon Solar Cells","authors":"J. Prince, J. Lathrop, R. A. Hartman","doi":"10.1109/IRPS.1980.362908","DOIUrl":"https://doi.org/10.1109/IRPS.1980.362908","url":null,"abstract":"Results of a program to investigate the reliability characteristics of unencapsulated low-cost terrestrial solar cells using accelerated stress testing are presented. A total of seven types of cells were investigated. Results of extended (~ 1 year) bias-temperature stress testing of four cell types were obtained. An additional three cell types, including cells fabricated using the advanced technologies of ribbon-grown silicon and polycrystalline silicon, were subjected to various combinations of bias, temperature cycling stress tests. The spectrum of tests used was based on previous years' work, but differs from that used earlier. An electrical measurement procedure capable of distinguishing small changes in cell electrical parameters was used. Significant degradation was shown by some cell types in some stress tests. Other combinations of cell types and stress tests resulted in no detectable cell degradation. Analysis of the origins of the differences in degradation is continuing. Second quadrant characteristics of some cell types were also investigated in order to establish the electrical behavior of cells which may be exposed to this stress condition in modules deployed in the field.","PeriodicalId":270567,"journal":{"name":"18th International Reliability Physics Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134646756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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