Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409628
Daeseok Lee, Jaesung Park, Kibong Moon, Junwoo Jang, Sangsu Park, Myonglae Chu, Jongin Kim, J. Noh, M. Jeon, Byoung Hun Lee, Boreom Lee, Byung-geun Lee, H. Hwang
We report oxide based analog synpase for neuromorphic system. By optimizing redox reaction at the metal/oxide interface, we can obtain stable analog synapse characteristics and wafer scale switching uniformity. We have confirmed the feasibility of neuromorphic hardware system with oxide synapse array device which recognizes the electroencephalogram (EEG) signal and rat's neural signal.
{"title":"Oxide based nanoscale analog synapse device for neural signal recognition system","authors":"Daeseok Lee, Jaesung Park, Kibong Moon, Junwoo Jang, Sangsu Park, Myonglae Chu, Jongin Kim, J. Noh, M. Jeon, Byoung Hun Lee, Boreom Lee, Byung-geun Lee, H. Hwang","doi":"10.1109/IEDM.2015.7409628","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409628","url":null,"abstract":"We report oxide based analog synpase for neuromorphic system. By optimizing redox reaction at the metal/oxide interface, we can obtain stable analog synapse characteristics and wafer scale switching uniformity. We have confirmed the feasibility of neuromorphic hardware system with oxide synapse array device which recognizes the electroencephalogram (EEG) signal and rat's neural signal.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126452249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409789
Nuo Xu, Jing Wang, Yang Lu, Hong-hyun Park, Bo Fu, Renyu Chen, W. Choi, D. Apalkov, Sungchul Lee, S. Ahn, Yohan Kim, Yutaka Nishizawa, Keun-Ho Lee, Youngkwan Park, E. Jung
A comprehensive compact modeling framework coupling quantum transport with magnetic dynamics has been developed for state-of-the-art and emerging STT-MRAMs. After validation with numerical simulation and experimental results, various transistor-MRAM cell architectures have been studied for their performance and variability. SOT-assisted MRAMs are found to have significant improvement on Erase time over conventional STT-MRAMs.
{"title":"Physics-based compact modeling framework for state-of-the-art and emerging STT-MRAM technology","authors":"Nuo Xu, Jing Wang, Yang Lu, Hong-hyun Park, Bo Fu, Renyu Chen, W. Choi, D. Apalkov, Sungchul Lee, S. Ahn, Yohan Kim, Yutaka Nishizawa, Keun-Ho Lee, Youngkwan Park, E. Jung","doi":"10.1109/IEDM.2015.7409789","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409789","url":null,"abstract":"A comprehensive compact modeling framework coupling quantum transport with magnetic dynamics has been developed for state-of-the-art and emerging STT-MRAMs. After validation with numerical simulation and experimental results, various transistor-MRAM cell architectures have been studied for their performance and variability. SOT-assisted MRAMs are found to have significant improvement on Erase time over conventional STT-MRAMs.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114162263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409730
Daewon Kim, Byeong-Woon Hwang, Jin-woo Han, Myeong-Lok Seol, Yura Oh, Yang-Kyu Choi
A micro-porous polymer film is utilized as a triboelectric layer of triboelectric energy harvester. The relationship between porosity of the triboelectric layer and output characteristics is analyzed for the first time. There are two key parameters found to influence the output performance of the triboelectric energy harvester: the surface charge density and effective capacitance of the triboelectric layer. Experiment, modeling, and simulation based on electrodynamics are performed to investigate how the two parameters affect the output performance.
{"title":"Output enhancement of triboelectric energy harvester by micro-porous triboelectric layer","authors":"Daewon Kim, Byeong-Woon Hwang, Jin-woo Han, Myeong-Lok Seol, Yura Oh, Yang-Kyu Choi","doi":"10.1109/IEDM.2015.7409730","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409730","url":null,"abstract":"A micro-porous polymer film is utilized as a triboelectric layer of triboelectric energy harvester. The relationship between porosity of the triboelectric layer and output characteristics is analyzed for the first time. There are two key parameters found to influence the output performance of the triboelectric energy harvester: the surface charge density and effective capacitance of the triboelectric layer. Experiment, modeling, and simulation based on electrodynamics are performed to investigate how the two parameters affect the output performance.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121219800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409762
K. Ikegami, H. Noguchi, S. Takaya, C. Kamata, M. Amano, K. Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, D. Saida, A. Kawasumi, H. Hara, J. Ito, S. Fujita
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for high speed operation and considered not suited for lower level cache memory. In this work, we have developed L2 and L3 cache memory based on thermal stability factor engineered pMTJ with 2T-2MTJ and 1T-1MTJ memory cell and novel error handling scheme. These techniques reduce 75% energy with 2% performance overhead compared to SRAM-based l2 and L3 cache memory.
{"title":"MTJ-based \"normally-off processors\" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and last level cache based on 1T-1MTJ cell and novel error handling scheme","authors":"K. Ikegami, H. Noguchi, S. Takaya, C. Kamata, M. Amano, K. Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, D. Saida, A. Kawasumi, H. Hara, J. Ito, S. Fujita","doi":"10.1109/IEDM.2015.7409762","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409762","url":null,"abstract":"MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for high speed operation and considered not suited for lower level cache memory. In this work, we have developed L2 and L3 cache memory based on thermal stability factor engineered pMTJ with 2T-2MTJ and 1T-1MTJ memory cell and novel error handling scheme. These techniques reduce 75% energy with 2% performance overhead compared to SRAM-based l2 and L3 cache memory.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116585420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409654
J. C. Liu, K. C. Huang, Y. Chu, J. Hung, C. C. Change, Y. L. Wei, J. Lin, M. Kao, P. Chen, S. Y. Huang, H. C. Lin, W. D. Wang, P.S. Chou, C. F. Lu, Y. Tu, F. J. Shiu, C. Huang, C. H. Lin, T. Lu, D. Yaung
A high density 50K~100K/mm2 cross-tier connection featuring backside through-via (BTV) and wafer level 3D stacking technologies has been successfully demonstrated. Wafer stacking and thinning to <; 1/250 Si thickness process showed little to no impact to advanced device performance. BTV induced stress effect was also studied; quite different behaviors between wafers with SiGe and without SiGe process were found. SiGe local strain will be diminished by BTV induced strain when BTV getting too close to channel, and hence lower hole mobility. This impact could be minimized by proper Keep-Out Zone (KOZ) design. Furthermore, 3D stacked architecture provides the opportunity to individually optimize process and design for each function block on separated wafers, thus improve chip performance and power consumption, and also benefit chip footprint.
{"title":"Advanced device performance impact by wafer level 3D stacked architecture","authors":"J. C. Liu, K. C. Huang, Y. Chu, J. Hung, C. C. Change, Y. L. Wei, J. Lin, M. Kao, P. Chen, S. Y. Huang, H. C. Lin, W. D. Wang, P.S. Chou, C. F. Lu, Y. Tu, F. J. Shiu, C. Huang, C. H. Lin, T. Lu, D. Yaung","doi":"10.1109/IEDM.2015.7409654","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409654","url":null,"abstract":"A high density 50K~100K/mm2 cross-tier connection featuring backside through-via (BTV) and wafer level 3D stacking technologies has been successfully demonstrated. Wafer stacking and thinning to <; 1/250 Si thickness process showed little to no impact to advanced device performance. BTV induced stress effect was also studied; quite different behaviors between wafers with SiGe and without SiGe process were found. SiGe local strain will be diminished by BTV induced strain when BTV getting too close to channel, and hence lower hole mobility. This impact could be minimized by proper Keep-Out Zone (KOZ) design. Furthermore, 3D stacked architecture provides the opportunity to individually optimize process and design for each function block on separated wafers, thus improve chip performance and power consumption, and also benefit chip footprint.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121635764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409619
E. Hsieh, Z. H. Huang, S. Chung, J. Ke, C. Yang, C. Tsai, T. Yew
For the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<; 50μA), fast speed (~20μsec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era.
{"title":"The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown","authors":"E. Hsieh, Z. H. Huang, S. Chung, J. Ke, C. Yang, C. Tsai, T. Yew","doi":"10.1109/IEDM.2015.7409619","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409619","url":null,"abstract":"For the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<; 50μA), fast speed (~20μsec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125048735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409649
Z.-Q Wang, S. Ambrogio, S. Balatti, S. Sills, A. Calderoni, N. Ramaswamy, D. Ielmini
Resistive switching memory (RRAM) is raising interest for future storage-class memory (SCM) and embedded applications due to high speed operation, low power and non-volatile behavior. While cycling endurance is currently well understood, the impact of cycling on switching and reliability is still a matter of concern. To that purpose we study the cycling-induced degradation of HfOx RRAM in this work. We show that the resistance of the low-resistance state (LRS), the set voltage Vset and the reset voltage Vreset decrease with cycling, which we attribute to defect generation causing enhanced ion mobility. The degradation kinetics is modelled by an Arrhenius-driven distributed-energy model. Our study allows to predict set/reset voltages after any arbitrary number of cycles and for any set/reset cycling condition.
{"title":"Cycling-induced degradation of metal-oxide resistive switching memory (RRAM)","authors":"Z.-Q Wang, S. Ambrogio, S. Balatti, S. Sills, A. Calderoni, N. Ramaswamy, D. Ielmini","doi":"10.1109/IEDM.2015.7409649","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409649","url":null,"abstract":"Resistive switching memory (RRAM) is raising interest for future storage-class memory (SCM) and embedded applications due to high speed operation, low power and non-volatile behavior. While cycling endurance is currently well understood, the impact of cycling on switching and reliability is still a matter of concern. To that purpose we study the cycling-induced degradation of HfOx RRAM in this work. We show that the resistance of the low-resistance state (LRS), the set voltage Vset and the reset voltage Vreset decrease with cycling, which we attribute to defect generation causing enhanced ion mobility. The degradation kinetics is modelled by an Arrhenius-driven distributed-energy model. Our study allows to predict set/reset voltages after any arbitrary number of cycles and for any set/reset cycling condition.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122712290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409608
M. Simmons
Down-scaling has been the leading paradigm of the semiconductor industry since the invention of the first transistor in 1947. This paper discusses the development of a unique technology for creating atomic-scale devices in silicon. We will introduce single atom transistors and how we are systematically demonstrating the components of a quantum integrated circuit at the atomic-scale towards the development of a silicon based quantum computer. This new type of computer exploits the laws of quantum physics to provide a predicted exponential speed up in computational processing power.
{"title":"Quantum computing in silicon","authors":"M. Simmons","doi":"10.1109/IEDM.2015.7409608","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409608","url":null,"abstract":"Down-scaling has been the leading paradigm of the semiconductor industry since the invention of the first transistor in 1947. This paper discusses the development of a unique technology for creating atomic-scale devices in silicon. We will introduce single atom transistors and how we are systematically demonstrating the components of a quantum integrated circuit at the atomic-scale towards the development of a silicon based quantum computer. This new type of computer exploits the laws of quantum physics to provide a predicted exponential speed up in computational processing power.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131215724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409679
P. Ren, Xiaoqing Xu, P. Hao, Junyao Wang, Runsheng Wang, Ming Li, Jianping Wang, Weihai Bu, Jingang Wu, W. Wong, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, D. Pan, Ru Huang
In this paper, a new class of layout dependent effects (LDE)-the time-dependent layout dependency due to device aging, is reported for the first time. The BTI and HCI degradation in nanoscale HKMG devices are experimentally found to be sensitive to layout configurations, even biased at the same stress condition. This new effect of layout dependent aging (LDA) can significantly mess the circuit design, which conventionally only includes the static LDE modeled for time-zero performance. Further studies at circuit level indicate that, for resilient device-circuit-layout co-design, especially to ensure enough design margin near the end of life, LDA cannot be neglected. The results are helpful to guide the cross-layer technology/design co-optimization.
{"title":"Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization - New findings on the layout dependent aging effects","authors":"P. Ren, Xiaoqing Xu, P. Hao, Junyao Wang, Runsheng Wang, Ming Li, Jianping Wang, Weihai Bu, Jingang Wu, W. Wong, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, D. Pan, Ru Huang","doi":"10.1109/IEDM.2015.7409679","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409679","url":null,"abstract":"In this paper, a new class of layout dependent effects (LDE)-the time-dependent layout dependency due to device aging, is reported for the first time. The BTI and HCI degradation in nanoscale HKMG devices are experimentally found to be sensitive to layout configurations, even biased at the same stress condition. This new effect of layout dependent aging (LDA) can significantly mess the circuit design, which conventionally only includes the static LDE modeled for time-zero performance. Further studies at circuit level indicate that, for resilient device-circuit-layout co-design, especially to ensure enough design margin near the end of life, LDA cannot be neglected. The results are helpful to guide the cross-layer technology/design co-optimization.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131744475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409821
Rotem Vishinkin, H. Haick
Delayed diagnosis of many diseases is caused by technology limitations of currently available methods. Therefore, there is a need for novel technology that would allow efficient early detection, population stratification for personalized therapy, and for rapid assessment of treatment efficacy. Such an emerging approach is based on artificially intelligent sensing arrays of solid-state or flexible sensors that detect the so-called "volatolomics", viz. profiles of volatile organic compounds (VOCs) which are by-products of metabolic processes and emit from various body fluids.
{"title":"Artificially intelligent nanoarrays for disease detection via volatolomics","authors":"Rotem Vishinkin, H. Haick","doi":"10.1109/IEDM.2015.7409821","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409821","url":null,"abstract":"Delayed diagnosis of many diseases is caused by technology limitations of currently available methods. Therefore, there is a need for novel technology that would allow efficient early detection, population stratification for personalized therapy, and for rapid assessment of treatment efficacy. Such an emerging approach is based on artificially intelligent sensing arrays of solid-state or flexible sensors that detect the so-called \"volatolomics\", viz. profiles of volatile organic compounds (VOCs) which are by-products of metabolic processes and emit from various body fluids.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131856751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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