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2015 IEEE International Electron Devices Meeting (IEDM)最新文献

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The challenging promise of 2D materials for electronics 二维电子材料的挑战性前景
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409778
G. Fiori, G. Iannaccone
In this work, we discuss the prospects of two-dimensional materials (2DMs) for electronic applications, investigated through multi-scale simulations. Our aim is to assess the ultimate achievable performance of 2DMs in a wide range of applications, such as digital and analog in high-performance transistors, or as transparent electrode in opto-electronics devices.
在这项工作中,我们通过多尺度模拟研究了二维材料(2dm)在电子应用中的前景。我们的目标是评估2dm在广泛应用中的最终可实现性能,例如高性能晶体管中的数字和模拟,或光电器件中的透明电极。
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引用次数: 4
A novel two-varistors (a-Si/SiN/a-Si) selected complementary atom switch (2V-1CAS) for nonvolatile crossbar switch with multiple fan-outs 一种新型的双压敏电阻(A - si /SiN/ A - si)互补原子开关(2V-1CAS)用于多扇出非易失性交叉排开关
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409614
N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi
A nonvolatile and compact switch realizing multiple fan-outs of a crossbar switch for programmable logic devices (PLDs) has been newly developed by using two-varistors selected complementary atom switch (2V-1CAS). The two control lines connected to the varistors realize the accurate programming of each cross-point without select transistors. The novel nitrogen-modulated, TiN/a-Si/SiN/a-Si/TiN varistor shows superior nonlinear (NL) characteristic of ~105, which are successfully stacked on the top of CAS with dual-hard mask (DHM) process. The developed 2V-1CAS (18F2) gives a promising switch block (SB) used for energy-efficient, nonvolatile PLDs.
采用双压敏电阻选择互补原子开关(2V-1CAS),研制了一种非易失性紧凑开关,可实现可编程逻辑器件(pld)交叉排开关的多扇出。连接到压敏电阻的两条控制线实现了每个交叉点的精确编程,无需选择晶体管。新型氮调制TiN/a-Si/SiN/a-Si/TiN压敏电阻具有~105的优异非线性(NL)特性,并通过双硬掩膜(DHM)工艺成功地叠加在CAS的顶部。开发的2V-1CAS (18F2)提供了一种有前途的开关块(SB),用于节能,非易失性pld。
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引用次数: 12
Color image sensor with organic photoconductive films 彩色图像传感器与有机光导薄膜
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409800
T. Sakai, H. Seo, T. Takagi, M. Kubota, H. Ohtake, M. Furuta
A color image sensor with three stacked organic photoconductive films (OPFs) and transparent readout circuits for a high-resolution, high-sensitivity, compact color video camera is described. The sensor separates and simultaneously detects the three primary colors. We fabricated test image sensors and confirmed the feasibility of the color video camera with three stacked OPFs.
介绍了一种用于高分辨率、高灵敏度、紧凑型彩色摄像机的彩色图像传感器,该传感器具有三层堆叠的有机光导膜(opf)和透明读出电路。传感器分离并同时检测三种原色。我们制作了测试图像传感器,并证实了三个堆叠opf的彩色摄像机的可行性。
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引用次数: 9
A floating gate based 3D NAND technology with CMOS under array 基于浮动门的CMOS阵列三维NAND技术
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409618
K. Parat, C. Dennison
NAND Flash has followed Moore's law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.
NAND闪存遵循摩尔定律已经好几代了。随着最小半间距低于20nm,需要过渡到3D NAND单元以继续缩放。本文介绍了一种基于浮栅的3D NAND技术,该技术相对于2D NAND具有优越的单元特性,并在CMOS阵列下实现高Gb/mm2密度。
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引用次数: 83
2RW dual-port SRAM design challenges in advanced technology nodes 2RW双端口SRAM在先进技术节点中的设计挑战
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409673
K. Nii, M. Yabuuchi, Yoshisato Yokoyama, Y. Ishii, T. Okagaki, M. Morimoto, Y. Tsukamoto, Koji Tanaka, Miki Tanaka, S. Tanaka
We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.
我们研究了先进平面/FinFET技术中两个读/写(2RW) 8T双端口(DP) SRAM的适当位单元布局。采用16纳米FinFET技术设计并制作了具有高度对称8T DP位元的256 kbit 2RW SRAM宏。wordline超速驱动的读写辅助将Vmln降低了120mv,在低于0.5 V的电压下实现了成功的操作。
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引用次数: 7
Novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using ultra-high density nano-Cu filaments for exascale 2.5D/3D integration 采用超高密度纳米铜丝的新型晶圆间(W2W)混合键合技术,实现百亿亿级2.5D/3D集成
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409652
K. Lee, C. Nagai, J. Bea, T. Fukushima, R. Suresh, X. Wu, T. Tanaka, M. Koyanagi
In order to solve the critical issues of current standard chip-to-wafer (C2W)/wafer-to-wafer (W2W) hybrid bonding technologies, we propose novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using three types of scaled tiny electrodes with slightly extruded structure and unique adhesive layers for ultra-high density 2.5D/3D integration applications. Especially, we developed a high stacking yield hybrid bonding technology using unique anisotropic conductive film composed of ultra-high density nano-Cu filaments for exascale 2.5D/3D integration. Multi numbers of TEG die with 7mm × 23mm size are simultaneously aligned with high accuracy around 1um by chip self-assembly method and thermal-compression bonding in wafer-level. Totally 3,898,000 of 4,309,200 electrodes with 3um diameter/6um pitch in each TEG chip are well intact-bonded by new hybrid bonding technology using ultra-high density nano-Cu filaments which gives rise to the joining yield of 90%.
为了解决当前标准芯片到晶圆(C2W)/晶圆到晶圆(W2W)混合键合技术的关键问题,我们提出了一种新的重新配置的晶圆到晶圆(W2W)混合键合技术,该技术使用三种具有微挤压结构的缩放微小电极和独特的粘合层,用于超高密度2.5D/3D集成应用。特别是,我们开发了一种高堆叠良率的混合键合技术,该技术采用独特的由超高密度纳米铜丝组成的各向异性导电膜,用于百亿亿次2.5D/3D集成。采用芯片自组装和晶圆级热压缩键合的方法,实现了7mm × 23mm尺寸的多个TEG芯片同时对准,精度在1um左右。在TEG芯片中,4309,200个直径为3um /间距为6um的电极中,有3,898,000个电极采用超高密度纳米铜丝混合键合技术完整地连接在一起,连接率达到90%。
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引用次数: 6
Understanding the nature of metal-graphene contacts: A theoretical and experimental study 理解金属-石墨烯接触的本质:一项理论和实验研究
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409686
T. Cusati, G. Fiori, A. Gahoi, V. Passi, A. Fortunelli, M. Lemme, G. Iannaccone
In this paper we propose a theoretical and experimental study of the nature of metal-graphene contacts. We use ab-initio simulations and semi-analytical modeling to derive and validate a simple two-parameter model of metal-graphene contacts. Such findings are supported by experimental results for large samples of different types of metal-graphene contacts.
在本文中,我们提出了金属-石墨烯接触性质的理论和实验研究。我们使用ab-initio模拟和半解析建模来推导和验证金属-石墨烯接触的简单双参数模型。这些发现得到了不同类型金属-石墨烯接触大样本实验结果的支持。
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引用次数: 6
Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules 基于Si平台上垂直堆叠纳米线的栅极全能CMOS (InAs n-FET和GaSb p-FET),通过极薄缓冲层技术和通用栅极堆叠和触点模块实现
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409704
K. Goh, K. Tan, S. Yadav, Annie, S. Yoon, G. Liang, X. Gong, Y. Yeo
We report the first demonstration of a novel vertically stacked structure comprising InAs nanowires and GaSb nanowires, enabled by an extremely-thin (sub-150 nm) III-V buffer technology on a Si platform. This led to the realization of InAs n-FETs and GaSb p-FETs based on the stacked InAs or GaSb nanowires (NWs), respectively, employing multiple common modules such as gate stack and contact processes. Decent transfer characteristics with SS of 126 mV/decade and DIBL of 285 mV/V were obtained for the InAs n-FET with a channel length LCH of 20 nm. For the vertically stacked GaSb NW p-FET (LCH of 500 nm), the lowest reported SS of 188 mV/decade and highest ION/IOFF ratio of 3.5 orders were achieved for III-V p-FETs on Si substrate.
我们报告了一种由InAs纳米线和GaSb纳米线组成的新型垂直堆叠结构的首次演示,该结构由极薄(低于150 nm) III-V缓冲技术在Si平台上实现。这导致分别基于堆叠InAs或GaSb纳米线(NWs)实现InAs n- fet和GaSb p- fet,采用多个通用模块,如栅极堆叠和接触工艺。对于沟道长度LCH为20 nm的InAs n-FET,获得了良好的转移特性,SS为126 mV/decade, DIBL为285 mV/V。对于垂直堆叠的GaSb NW p-FET (LCH为500 nm),在Si衬底上的III-V p-FET获得了最低的SS为188 mV/decade和最高的离子/IOFF比3.5阶。
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引用次数: 10
High dose efficiency, ultra-high resolution amorphous selenium/CMOS hybrid digital X-ray imager 高剂量效率,超高分辨率非晶硒/CMOS混合数字x射线成像仪
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409803
C. Scott, A. Parsafar, A. El-Falou, P. Levine, K. Karim
We demonstrate measured X-ray dose efficiency results from a 5.6-μm × 6.25-μm pixel-pitch direct-conversion amorphous selenium/CMOS hybrid X-ray imager. Compared to existing scintillator-based imagers, our approach enables up to 100× gains in DQE at spatial frequencies of 20-60 cycles/mm, which could radically accelerate bioengineering research. The measured MTF is 50% at 32 cycles/mm, corresponding to a 16-μm effective object size. We also demonstrate a MTF model which confirms experimental results with an RMS error of 0.02.
我们展示了5.6 μm × 6.25 μm像素间距直接转换非晶硒/CMOS混合x射线成像仪测量的x射线剂量效率结果。与现有的基于闪烁体的成像仪相比,我们的方法可以在20-60周期/mm的空间频率下实现高达100倍的DQE增益,这可以从根本上加速生物工程研究。在32次循环/mm时,测量到的MTF为50%,对应于16 μm的有效物体尺寸。我们还验证了MTF模型,该模型与实验结果一致,均方根误差为0.02。
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引用次数: 12
Structural coordination of rigidity with flexibility in gate dielectric films for sub-nm EOT Ge gate stack reliability 亚纳米EOT Ge栅极堆叠可靠性栅介质膜刚性与柔性的结构配合
Pub Date : 2015-12-01 DOI: 10.1109/IEDM.2015.7409698
Cimang Lu, A. Toriumi
This paper reports a gate dielectric film design for reliability-aware as well as scalability conscious gate stacks on Ge. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome this big hurdle, we propose a novel concept of the rigidity control in the dielectric films with continuous random network. Ge gate stacks with initially prominent passivation and long term reliability are demonstrated experimentally. This is a new view for achieving the built-in design of gate dielectric film with reliability as well as scalability.
本文报道了一种用于可靠性感知和可扩展性感知栅极堆栈的栅极介电膜设计。初期良好的栅极堆叠特性并不一定能保证器件的长期可靠性。为了克服这一难题,我们提出了一种基于连续随机网络的介质膜刚度控制的新概念。实验证明了锗栅极堆具有初期显著的钝化和长期的可靠性。这为实现具有可靠性和可扩展性的栅介质薄膜内置设计提供了新的思路。
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引用次数: 7
期刊
2015 IEEE International Electron Devices Meeting (IEDM)
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