Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409698
Cimang Lu, A. Toriumi
This paper reports a gate dielectric film design for reliability-aware as well as scalability conscious gate stacks on Ge. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome this big hurdle, we propose a novel concept of the rigidity control in the dielectric films with continuous random network. Ge gate stacks with initially prominent passivation and long term reliability are demonstrated experimentally. This is a new view for achieving the built-in design of gate dielectric film with reliability as well as scalability.
{"title":"Structural coordination of rigidity with flexibility in gate dielectric films for sub-nm EOT Ge gate stack reliability","authors":"Cimang Lu, A. Toriumi","doi":"10.1109/IEDM.2015.7409698","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409698","url":null,"abstract":"This paper reports a gate dielectric film design for reliability-aware as well as scalability conscious gate stacks on Ge. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome this big hurdle, we propose a novel concept of the rigidity control in the dielectric films with continuous random network. Ge gate stacks with initially prominent passivation and long term reliability are demonstrated experimentally. This is a new view for achieving the built-in design of gate dielectric film with reliability as well as scalability.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121145935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409704
K. Goh, K. Tan, S. Yadav, Annie, S. Yoon, G. Liang, X. Gong, Y. Yeo
We report the first demonstration of a novel vertically stacked structure comprising InAs nanowires and GaSb nanowires, enabled by an extremely-thin (sub-150 nm) III-V buffer technology on a Si platform. This led to the realization of InAs n-FETs and GaSb p-FETs based on the stacked InAs or GaSb nanowires (NWs), respectively, employing multiple common modules such as gate stack and contact processes. Decent transfer characteristics with SS of 126 mV/decade and DIBL of 285 mV/V were obtained for the InAs n-FET with a channel length LCH of 20 nm. For the vertically stacked GaSb NW p-FET (LCH of 500 nm), the lowest reported SS of 188 mV/decade and highest ION/IOFF ratio of 3.5 orders were achieved for III-V p-FETs on Si substrate.
{"title":"Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules","authors":"K. Goh, K. Tan, S. Yadav, Annie, S. Yoon, G. Liang, X. Gong, Y. Yeo","doi":"10.1109/IEDM.2015.7409704","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409704","url":null,"abstract":"We report the first demonstration of a novel vertically stacked structure comprising InAs nanowires and GaSb nanowires, enabled by an extremely-thin (sub-150 nm) III-V buffer technology on a Si platform. This led to the realization of InAs n-FETs and GaSb p-FETs based on the stacked InAs or GaSb nanowires (NWs), respectively, employing multiple common modules such as gate stack and contact processes. Decent transfer characteristics with SS of 126 mV/decade and DIBL of 285 mV/V were obtained for the InAs n-FET with a channel length LCH of 20 nm. For the vertically stacked GaSb NW p-FET (LCH of 500 nm), the lowest reported SS of 188 mV/decade and highest ION/IOFF ratio of 3.5 orders were achieved for III-V p-FETs on Si substrate.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409618
K. Parat, C. Dennison
NAND Flash has followed Moore's law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.
{"title":"A floating gate based 3D NAND technology with CMOS under array","authors":"K. Parat, C. Dennison","doi":"10.1109/IEDM.2015.7409618","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409618","url":null,"abstract":"NAND Flash has followed Moore's law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"34 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132540153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409800
T. Sakai, H. Seo, T. Takagi, M. Kubota, H. Ohtake, M. Furuta
A color image sensor with three stacked organic photoconductive films (OPFs) and transparent readout circuits for a high-resolution, high-sensitivity, compact color video camera is described. The sensor separates and simultaneously detects the three primary colors. We fabricated test image sensors and confirmed the feasibility of the color video camera with three stacked OPFs.
{"title":"Color image sensor with organic photoconductive films","authors":"T. Sakai, H. Seo, T. Takagi, M. Kubota, H. Ohtake, M. Furuta","doi":"10.1109/IEDM.2015.7409800","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409800","url":null,"abstract":"A color image sensor with three stacked organic photoconductive films (OPFs) and transparent readout circuits for a high-resolution, high-sensitivity, compact color video camera is described. The sensor separates and simultaneously detects the three primary colors. We fabricated test image sensors and confirmed the feasibility of the color video camera with three stacked OPFs.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134560218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409757
S. Blaeser, S. Glass, C. Schulte-Braucks, K. Narimani, N. V. D. Driesch, S. Wirths, A. Tiedemann, S. Trellenkamp, D. Buca, Q. Zhao, S. Mantl
This paper presents a novel SiGe/Si tunneling field-effect transistor (TFET) which exploits line tunneling parallel with the gate electric field. The device makes use of selective and self-adjusted silicidation and a counter doped pocket within the SiGe layer at the source tunnel junction, resulting in a high on-current Ion = 6.7 μA/μm at a supply voltage VDD = -0.5 V and a constant subthreshold swing (SS) of about 80 mV/dec over four orders of magnitude of drain-current Id.
{"title":"Novel SiGe/Si line tunneling TFET with high Ion at low Vdd and constant SS","authors":"S. Blaeser, S. Glass, C. Schulte-Braucks, K. Narimani, N. V. D. Driesch, S. Wirths, A. Tiedemann, S. Trellenkamp, D. Buca, Q. Zhao, S. Mantl","doi":"10.1109/IEDM.2015.7409757","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409757","url":null,"abstract":"This paper presents a novel SiGe/Si tunneling field-effect transistor (TFET) which exploits line tunneling parallel with the gate electric field. The device makes use of selective and self-adjusted silicidation and a counter doped pocket within the SiGe layer at the source tunnel junction, resulting in a high on-current Ion = 6.7 μA/μm at a supply voltage VDD = -0.5 V and a constant subthreshold swing (SS) of about 80 mV/dec over four orders of magnitude of drain-current Id.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123975109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409716
Sangbum Kim, M. Ishii, S. Lewis, T. Perri, M. BrightSky, Wanki Kim, R. Jordan, G. Burr, N. Sosa, A. Ray, Jin P. Han, Christopher P. Miller, K. Hosokawa, C. Lam
We demonstrate a neuromorphic core with 64k-cell phase change memory (PCM) synaptic array (256 axons by 256 dendrites) with in-situ learning capability. 256 configurable on-chip neuron circuits perform leaky integrate and fire (LIF) and synaptic weight update based on spike-timing dependent plasticity (STDP). 2T-1R PCM unit cell design separates LIF and STDP learning paths, minimizing neuron circuit size. The circuit implementation of STDP learning algorithm along with 2T-1R structure enables both LIF and STDP learning to operate asynchronously and simultaneously within the array, avoiding additional complication and power consumption associated with timing schemes. We show hardware demonstration of in-situ learning with large representational capacity, enabled by large array size and analog synaptic weights of PCM cells.
{"title":"NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning","authors":"Sangbum Kim, M. Ishii, S. Lewis, T. Perri, M. BrightSky, Wanki Kim, R. Jordan, G. Burr, N. Sosa, A. Ray, Jin P. Han, Christopher P. Miller, K. Hosokawa, C. Lam","doi":"10.1109/IEDM.2015.7409716","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409716","url":null,"abstract":"We demonstrate a neuromorphic core with 64k-cell phase change memory (PCM) synaptic array (256 axons by 256 dendrites) with in-situ learning capability. 256 configurable on-chip neuron circuits perform leaky integrate and fire (LIF) and synaptic weight update based on spike-timing dependent plasticity (STDP). 2T-1R PCM unit cell design separates LIF and STDP learning paths, minimizing neuron circuit size. The circuit implementation of STDP learning algorithm along with 2T-1R structure enables both LIF and STDP learning to operate asynchronously and simultaneously within the array, avoiding additional complication and power consumption associated with timing schemes. We show hardware demonstration of in-situ learning with large representational capacity, enabled by large array size and analog synaptic weights of PCM cells.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127659438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409657
Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Y. Hou, Yi-Ju Chen, Yao-Jen Lee, Min-Cheng Chen, Fu-Liang Yang, Yu-Hsiu Chen, Meng-Chyi Wu, W. Yeh
Local and selective far-infrared ray laser annealing (FIR-LA) process with very short heating duration (<;100μs) and low substrate temperature (<;400°C) enables sequentially stacked gate-first nanowire FETs (NWFETs), including 3D+ Si NWFET and poly-Ge junctionless (JL) NWFET, and BEOL compatible monolithic 3D+ nanoelectronics. The 3D+ Si NWFETs, demonstrated by green nano-second laser crystallization (GNS-LC) and FIR-LA processes exhibit steep subthreshold swing (<;90mV/dec.) and high driving current (n-type: 310μA/μm and p-type: 220μA/μm). The 7nm poly-Ge JLNWFET shows high Ion/Ioff ratio (>5×104) and small DIBL. Furthermore, the thus fabricated low driving voltage 6T SRAM shows a static noise margin (SNM) of 130 mV at Vd=0.4V enabling the low power and low cost 3D+IC for internet of things (IoTs).
局部和选择性远红外激光退火(FIR-LA)工艺，加热时间极短(+ Si NWFET和多锗无结(JL) NWFET, BEOL兼容单片3D+纳米电子。通过绿色纳秒激光结晶(GNS-LC)和FIR-LA工艺制备的3D+ Si nwfet具有陡峭的亚阈值摆动(开/关比>5×104)和较小的DIBL。此外，由此制备的低驱动电压6T SRAM在Vd=0.4V时显示出130 mV的静态噪声裕度(SNM)，使物联网(iot)的低功耗低成本3D+IC成为可能。
{"title":"Enabling low power BEOL compatible monolithic 3D+ nanoelectronics for IoTs using local and selective far-infrared ray laser anneal technology","authors":"Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Y. Hou, Yi-Ju Chen, Yao-Jen Lee, Min-Cheng Chen, Fu-Liang Yang, Yu-Hsiu Chen, Meng-Chyi Wu, W. Yeh","doi":"10.1109/IEDM.2015.7409657","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409657","url":null,"abstract":"Local and selective far-infrared ray laser annealing (FIR-LA) process with very short heating duration (<;100μs) and low substrate temperature (<;400°C) enables sequentially stacked gate-first nanowire FETs (NWFETs), including 3D<sup>+</sup> Si NWFET and poly-Ge junctionless (JL) NWFET, and BEOL compatible monolithic 3D<sup>+</sup> nanoelectronics. The 3D<sup>+</sup> Si NWFETs, demonstrated by green nano-second laser crystallization (GNS-LC) and FIR-LA processes exhibit steep subthreshold swing (<;90mV/dec.) and high driving current (n-type: 310μA/μm and p-type: 220μA/μm). The 7nm poly-Ge JLNWFET shows high I<sub>on</sub>/I<sub>off</sub> ratio (>5×10<sup>4</sup>) and small DIBL. Furthermore, the thus fabricated low driving voltage 6T SRAM shows a static noise margin (SNM) of 130 mV at Vd=0.4V enabling the low power and low cost 3D<sup>+</sup>IC for internet of things (IoTs).","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121153579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409674
Y. Woo, M. Ichihashi, S. Parihar, Lei Yuan, S. Banna, J. Kye
Due to the resolution limit of the lithography tools, multiple patterning technologies are being introduced to the back-end of the line (BEOL). For example, LELELE (or LE3, triple litho-etch) or SADP (self-aligned double patterning) [1] are already implemented in 10nm node technology based on a polygon's geometry, its orientation and pitch requirement. However, metal architecture, arrangement of signal and power lines in a metal layer or across metal layers, cause a significant impact on operating performance as well as determine the metal's orientation, which is also an important element for lithographic performance. Therefore, all the factors should be addressed together to arrive at an optimal chip performance.
{"title":"Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell","authors":"Y. Woo, M. Ichihashi, S. Parihar, Lei Yuan, S. Banna, J. Kye","doi":"10.1109/IEDM.2015.7409674","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409674","url":null,"abstract":"Due to the resolution limit of the lithography tools, multiple patterning technologies are being introduced to the back-end of the line (BEOL). For example, LELELE (or LE3, triple litho-etch) or SADP (self-aligned double patterning) [1] are already implemented in 10nm node technology based on a polygon's geometry, its orientation and pitch requirement. However, metal architecture, arrangement of signal and power lines in a metal layer or across metal layers, cause a significant impact on operating performance as well as determine the metal's orientation, which is also an important element for lithographic performance. Therefore, all the factors should be addressed together to arrive at an optimal chip performance.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116805836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409713
D. Piedra, B. Lu, Min-Chul Sun, Yuhao Zhang, E. Matioli, F. Gao, Jinwook Chung, O. Saadat, L. Xia, M. Azize, T. Palacios
It is the most exciting time for power electronics in decades. The combination of new applications, such as microinverters, electric vehicles and solid state lighting, with the new opportunities brought by wide bandgap semiconductors is expected to significantly increase the reach and impact of power electronics. This paper describes some of the recent advances on developing power devices based on Gallium Nitride (GaN), the key design constrains, and the process to take a new device material and structure from the research laboratory of universities to full commercialization.
{"title":"Advanced power electronic devices based on Gallium Nitride (GaN)","authors":"D. Piedra, B. Lu, Min-Chul Sun, Yuhao Zhang, E. Matioli, F. Gao, Jinwook Chung, O. Saadat, L. Xia, M. Azize, T. Palacios","doi":"10.1109/IEDM.2015.7409713","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409713","url":null,"abstract":"It is the most exciting time for power electronics in decades. The combination of new applications, such as microinverters, electric vehicles and solid state lighting, with the new opportunities brought by wide bandgap semiconductors is expected to significantly increase the reach and impact of power electronics. This paper describes some of the recent advances on developing power devices based on Gallium Nitride (GaN), the key design constrains, and the process to take a new device material and structure from the research laboratory of universities to full commercialization.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116862076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409611
Xiao Yu, Jian Kang, M. Takenaka, S. Takagi
In this paper, we have successfully demonstrated high quality Extremely-thin body (ETB) Ge-on-insulator (GOI) p-MOSFETs with thickness ranging from 25 nm to 2 nm. Furthermore, the hole mobility and the GOI thickness dependence over a wide range of GOI thickness down to 2 nm are systematically analyzed and understood from the viewpoint of the scattering mechanisms, for the first time.
{"title":"Experimental study on carrier transport properties in extremely-thin body Ge-on-insulator (GOI) p-MOSFETs with GOI thickness down to 2 nm","authors":"Xiao Yu, Jian Kang, M. Takenaka, S. Takagi","doi":"10.1109/IEDM.2015.7409611","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409611","url":null,"abstract":"In this paper, we have successfully demonstrated high quality Extremely-thin body (ETB) Ge-on-insulator (GOI) p-MOSFETs with thickness ranging from 25 nm to 2 nm. Furthermore, the hole mobility and the GOI thickness dependence over a wide range of GOI thickness down to 2 nm are systematically analyzed and understood from the viewpoint of the scattering mechanisms, for the first time.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117035818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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