Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409808
C. Zota, L. Wernersson, E. Lind
We report on In0.85Ga0.15As NWFETs utilizing a single suspended (above the substrate) selectively grown nanowire as the channel. These devices exhibit gm = 3.3 mS/μm and subthreshold slope SS = 118 mV/dec, both at VDS = 0.5 V and LG = 60 nm. This is the highest reported value of gm for all MOSFETs and HEMTs, as well as a strong combination of on and off performance, with Q = gm/SS = 28, the highest for non-planar III-V MOSFETs.
{"title":"Single suspended InGaAs nanowire MOSFETs","authors":"C. Zota, L. Wernersson, E. Lind","doi":"10.1109/IEDM.2015.7409808","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409808","url":null,"abstract":"We report on In<sub>0.85</sub>Ga<sub>0.15</sub>As NWFETs utilizing a single suspended (above the substrate) selectively grown nanowire as the channel. These devices exhibit g<sub>m</sub> = 3.3 mS/μm and subthreshold slope SS = 118 mV/dec, both at V<sub>DS</sub> = 0.5 V and L<sub>G</sub> = 60 nm. This is the highest reported value of gm for all MOSFETs and HEMTs, as well as a strong combination of on and off performance, with Q = g<sub>m</sub>/SS = 28, the highest for non-planar III-V MOSFETs.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114490998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409725
Y. Tang, K. Najafi
This paper presents a two-gap CMOS-compatible technology to fabricate very tall (>500μm) 3D high aspect-ratio (HAR) silicon structures with narrow HAR sensing gaps (<;5μm) to achieve high sensitivity in capacitive sensors. This technology is especially suited for forming capacitive MEMS sensor arrays and offers the following advantages: 1) hundreds or thousands of small-footprint high-sensitivity devices can be integrated on a single chip to provide multiplicity of functions (greater dynamic range, fault-tolerance, reconfigurability, etc.); and 2) the ability to integrate MEMS devices on top of CMOS circuitry perform local signal processing for individual elements in the array. We designed, fabricated and tested capacitive accelerometer arrays in 1mm thick silicon using this technology, and demonstrated 8X increase in capacitive sensitivity thanks to the narrow HAR gaps, increased transduction area, increased device height (larger proof-mass), and reduced spring stiffness.
{"title":"A two-gap capacitive structure for high aspect-ratio capacitive sensor arrays","authors":"Y. Tang, K. Najafi","doi":"10.1109/IEDM.2015.7409725","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409725","url":null,"abstract":"This paper presents a two-gap CMOS-compatible technology to fabricate very tall (>500μm) 3D high aspect-ratio (HAR) silicon structures with narrow HAR sensing gaps (<;5μm) to achieve high sensitivity in capacitive sensors. This technology is especially suited for forming capacitive MEMS sensor arrays and offers the following advantages: 1) hundreds or thousands of small-footprint high-sensitivity devices can be integrated on a single chip to provide multiplicity of functions (greater dynamic range, fault-tolerance, reconfigurability, etc.); and 2) the ability to integrate MEMS devices on top of CMOS circuitry perform local signal processing for individual elements in the array. We designed, fabricated and tested capacitive accelerometer arrays in 1mm thick silicon using this technology, and demonstrated 8X increase in capacitive sensitivity thanks to the narrow HAR gaps, increased transduction area, increased device height (larger proof-mass), and reduced spring stiffness.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114559300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409653
Y. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, K. Arai, T. Ohba
An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.
{"title":"A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications","authors":"Y. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, K. Arai, T. Ohba","doi":"10.1109/IEDM.2015.7409653","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409653","url":null,"abstract":"An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126199305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409769
T. Miyata, H. Tanaka, K. Kagimoto, M. Kamiyashiki, M. Kamimura, A. Hidaka, M. Goto, K. Adachi, A. Hokazono, T. Ohguro, K. Nagaoka, Y. Watanabe, S. Hirooka, Y. Ito, S. Kawanaka, K. Ishimaru
We propose Multi Gate Oxide - Dual Work-Function (MGO-DWF)-MOSFET which is suitable for low power AB-class RF power amplifier (RF PA). This was examined for the first time by comparing with a standard Cascode connection circuitry composed of LV- and HVMOSFETs. Dramatically improved FMAX (150 GHz) with sufficient drain break-down voltage (VBD) was experimentally confirmed in a practical device structure. MGO-DWF-MOSFET has multiple roles in a unit device such as LV-MOSFET in source side regions and HV-MOSFET in drain side regions. This distinctive structure enables the reduction of the device area and a gate capacitance (CG) with a higher transconductance (GM) and the suppression of drain conductance (GDS). Enhancement of FMAX, in other words, DC operation current reduction is achieved at a given operation point. This indicates that MGO-DWF MOSFET is advantageous for low power amplifier circuitry applications, typically for RF PA in internet of things (IoT) products.
{"title":"150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET","authors":"T. Miyata, H. Tanaka, K. Kagimoto, M. Kamiyashiki, M. Kamimura, A. Hidaka, M. Goto, K. Adachi, A. Hokazono, T. Ohguro, K. Nagaoka, Y. Watanabe, S. Hirooka, Y. Ito, S. Kawanaka, K. Ishimaru","doi":"10.1109/IEDM.2015.7409769","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409769","url":null,"abstract":"We propose Multi Gate Oxide - Dual Work-Function (MGO-DWF)-MOSFET which is suitable for low power AB-class RF power amplifier (RF PA). This was examined for the first time by comparing with a standard Cascode connection circuitry composed of LV- and HVMOSFETs. Dramatically improved FMAX (150 GHz) with sufficient drain break-down voltage (VBD) was experimentally confirmed in a practical device structure. MGO-DWF-MOSFET has multiple roles in a unit device such as LV-MOSFET in source side regions and HV-MOSFET in drain side regions. This distinctive structure enables the reduction of the device area and a gate capacitance (CG) with a higher transconductance (GM) and the suppression of drain conductance (GDS). Enhancement of FMAX, in other words, DC operation current reduction is achieved at a given operation point. This indicates that MGO-DWF MOSFET is advantageous for low power amplifier circuitry applications, typically for RF PA in internet of things (IoT) products.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128176402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409787
Xiaobo Jiang, Xingsheng Wang, Runsheng Wang, B. Cheng, A. Asenov, Ru Huang
Predictive compact models for two key variability sources in FinFET technology, the gate edge roughness (GER) and Fin edge roughness (FER), are proposed for the first time, and integrated into industry standard BSIM-CMG core model. Excellent accuracy and predictivity is verified through atomistic TCAD simulations. The inherent correlations between the variations of device electrical parameters are well captured. In addition, an abnormal non-monotonous dependence of variations on Fin-width is observed, which can be explained with the newly found correlation between random variations and electrostatic integrity in FinFETs. The impacts of GER and FER on circuits are efficiently predicted for 16/14nm node and beyond, providing helpful guidelines for variation-aware design and technology process development.
{"title":"Predictive compact modeling of random variations in FinFET technology for 16/14nm node and beyond","authors":"Xiaobo Jiang, Xingsheng Wang, Runsheng Wang, B. Cheng, A. Asenov, Ru Huang","doi":"10.1109/IEDM.2015.7409787","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409787","url":null,"abstract":"Predictive compact models for two key variability sources in FinFET technology, the gate edge roughness (GER) and Fin edge roughness (FER), are proposed for the first time, and integrated into industry standard BSIM-CMG core model. Excellent accuracy and predictivity is verified through atomistic TCAD simulations. The inherent correlations between the variations of device electrical parameters are well captured. In addition, an abnormal non-monotonous dependence of variations on Fin-width is observed, which can be explained with the newly found correlation between random variations and electrostatic integrity in FinFETs. The impacts of GER and FER on circuits are efficiently predicted for 16/14nm node and beyond, providing helpful guidelines for variation-aware design and technology process development.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124982058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409610
Heng Wu, Wangran Wu, M. Si, P. Ye
Ge nanowire CMOS circuits are experimentally demonstrated on a Ge on insulator (GeOI) substrate for the first time. The nanowire CMOS devices have channel lengths (Lch) from 100 to 40 nm, nanowire height (HNW) of 10 nm and nanowire widths (WNW) from 40 to 10 nm, and dielectric EOTs of 2 and 5 nm. Four types of Ge MOSFETs: accumulation mode (AM) and inversion mode (IM) nFETs and pFETs are studied in great details. Record low SS of 64 mV/dec and high maximum trans-conductance (gmax) of 1057 μS/μm are obtained on Ge nanowire nFETs. Furthermore, hybrid Ge nanowire CMOS with AM nFET and IM pFET is also first realized. The highest maximum voltage gain reaches 54 V/V.
{"title":"First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters","authors":"Heng Wu, Wangran Wu, M. Si, P. Ye","doi":"10.1109/IEDM.2015.7409610","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409610","url":null,"abstract":"Ge nanowire CMOS circuits are experimentally demonstrated on a Ge on insulator (GeOI) substrate for the first time. The nanowire CMOS devices have channel lengths (Lch) from 100 to 40 nm, nanowire height (HNW) of 10 nm and nanowire widths (WNW) from 40 to 10 nm, and dielectric EOTs of 2 and 5 nm. Four types of Ge MOSFETs: accumulation mode (AM) and inversion mode (IM) nFETs and pFETs are studied in great details. Record low SS of 64 mV/dec and high maximum trans-conductance (gmax) of 1057 μS/μm are obtained on Ge nanowire nFETs. Furthermore, hybrid Ge nanowire CMOS with AM nFET and IM pFET is also first realized. The highest maximum voltage gain reaches 54 V/V.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131582626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409763
C. Tsai, J. Hsieh, Wei-Heng Lin, L. Yen, J. Hung, T. Peng, Hsi-Ching Wang, Cheng-Yu Kuo, I.L. Huang, W. Chu, Yi-Yang Lei, C. H. Yu, L. Sheu, C. Hsieh, C. S. Liu, K. Yee, Chuei-Tang Wang, Doug C. H. Yu
High performance passive devices for millimeter wave (MMW) system, including inductor, ring resonator, power combiner, coupler, balun, transmission line, and antenna, are first realized using integrated fan-out (InFO) wafer level packaging technology. The inductors has quality factor over 40; the power combiner, coupler, and balun show lower transmission loss than on-chip passives; antenna has the efficiency of over 60%. These devices on InFO enable low noise and power MMW system for mobile communication and IoT applications.
{"title":"High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology","authors":"C. Tsai, J. Hsieh, Wei-Heng Lin, L. Yen, J. Hung, T. Peng, Hsi-Ching Wang, Cheng-Yu Kuo, I.L. Huang, W. Chu, Yi-Yang Lei, C. H. Yu, L. Sheu, C. Hsieh, C. S. Liu, K. Yee, Chuei-Tang Wang, Doug C. H. Yu","doi":"10.1109/IEDM.2015.7409763","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409763","url":null,"abstract":"High performance passive devices for millimeter wave (MMW) system, including inductor, ring resonator, power combiner, coupler, balun, transmission line, and antenna, are first realized using integrated fan-out (InFO) wafer level packaging technology. The inductors has quality factor over 40; the power combiner, coupler, and balun show lower transmission loss than on-chip passives; antenna has the efficiency of over 60%. These devices on InFO enable low noise and power MMW system for mobile communication and IoT applications.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131844394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409613
Y. Yeo, X. Gong, M. V. van Dal, G. Vellianitis, M. Passlack
High mobility channel materials could replace strained Si to enhance speed performance and/or reduce power consumption in future transistors. Ge has the highest hole mobility among common elemental and compound semiconductors, and an electron mobility that is two times larger than that of Si. Ge is thus a promising channel material for future CMOS (Fig. 1). Key challenges include cost-effective integration of Ge on Si in a manufacturable process, formation of high-quality gate stack on Ge for n- and p-FETs at aggressively scaled EOTs that deliver high channel mobilities, and leakage issues related to its small bandgap. In this paper, we discuss recent research progress in advancing Ge-based transistor technologies. Integration of Ge on Si substrate to enable fabrication of high performance devices and formation of high-quality gate stack for Ge FETs (particularly for n-FETs) will be discussed. We also explore opportunities to boost the mobility of Ge, e.g. by incorporating Sn in Ge to form Ge1-xSnx. Furthermore, by raising the Sn composition, the band gap EG of Ge1-xSnx becomes smaller and transits from indirect to direct, making Ge1-xSnx a promising material for tunneling transistors.
在未来的晶体管中，高迁移率沟道材料可以取代应变硅，以提高速度性能和/或降低功耗。在普通元素和化合物半导体中，Ge的空穴迁移率最高，其电子迁移率是Si的两倍。因此，Ge是未来CMOS的一种很有前途的通道材料(图1)。主要挑战包括在可制造工艺中经济高效地集成Ge on Si，在大规模的eot上为n-和p- fet形成高质量的栅极堆，提供高通道迁移率，以及与小带隙相关的泄漏问题。本文讨论了推进ge基晶体管技术的最新研究进展。将讨论Ge在Si衬底上的集成，以实现高性能器件的制造，并形成用于Ge fet(特别是n- fet)的高质量栅极堆栈。我们还探索了提高Ge迁移率的机会，例如将Sn掺入Ge中形成Ge1-xSnx。此外，通过提高Sn的组成，Ge1-xSnx的带隙EG变小，并从间接过渡到直接，使Ge1-xSnx成为一种有前途的隧道晶体管材料。
{"title":"Germanium-based transistors for future high performance and low power logic applications","authors":"Y. Yeo, X. Gong, M. V. van Dal, G. Vellianitis, M. Passlack","doi":"10.1109/IEDM.2015.7409613","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409613","url":null,"abstract":"High mobility channel materials could replace strained Si to enhance speed performance and/or reduce power consumption in future transistors. Ge has the highest hole mobility among common elemental and compound semiconductors, and an electron mobility that is two times larger than that of Si. Ge is thus a promising channel material for future CMOS (Fig. 1). Key challenges include cost-effective integration of Ge on Si in a manufacturable process, formation of high-quality gate stack on Ge for n- and p-FETs at aggressively scaled EOTs that deliver high channel mobilities, and leakage issues related to its small bandgap. In this paper, we discuss recent research progress in advancing Ge-based transistor technologies. Integration of Ge on Si substrate to enable fabrication of high performance devices and formation of high-quality gate stack for Ge FETs (particularly for n-FETs) will be discussed. We also explore opportunities to boost the mobility of Ge, e.g. by incorporating Sn in Ge to form Ge1-xSnx. Furthermore, by raising the Sn composition, the band gap EG of Ge1-xSnx becomes smaller and transits from indirect to direct, making Ge1-xSnx a promising material for tunneling transistors.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409775
M. Sung, S. Jang, Hyunjin Lee, Y. Ji, Jae-Il Kang, Tae-Oh Jung, T. Ahn, Y. Son, Hyungchul Kim, Sun-Woo Lee, Seungmin Lee, Jung-Hak Lee, S. Baek, Eun-Hyup Doh, Heung-Jae Cho, T. Jang, I. Jang, Jae-Hwan Han, Kyung-Bo Ko, Yu-Jun Lee, Su-Bum Shin, Jae-Seon Yu, S. Cho, Ji-Hye Han, Dong-Kyun Kang, Jinsung Kim, Jae-Sang Lee, Keundo Ban, S. Yeom, H. Nam, Dong-Kyu Lee, M. Jeong, Byungil Kwak, Jeongsoo Park, K. Choi, Sung-Kye Park, N. Kwak, Sung-Joo Hong
It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.
{"title":"Gate-first high-k/metal gate DRAM technology for low power and high performance products","authors":"M. Sung, S. Jang, Hyunjin Lee, Y. Ji, Jae-Il Kang, Tae-Oh Jung, T. Ahn, Y. Son, Hyungchul Kim, Sun-Woo Lee, Seungmin Lee, Jung-Hak Lee, S. Baek, Eun-Hyup Doh, Heung-Jae Cho, T. Jang, I. Jang, Jae-Hwan Han, Kyung-Bo Ko, Yu-Jun Lee, Su-Bum Shin, Jae-Seon Yu, S. Cho, Ji-Hye Han, Dong-Kyun Kang, Jinsung Kim, Jae-Sang Lee, Keundo Ban, S. Yeom, H. Nam, Dong-Kyu Lee, M. Jeong, Byungil Kwak, Jeongsoo Park, K. Choi, Sung-Kye Park, N. Kwak, Sung-Joo Hong","doi":"10.1109/IEDM.2015.7409775","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409775","url":null,"abstract":"It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129760369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409634
Jinfeng Kang, B. Gao, Peng Huang, Haitong Li, Yudi Zhao, Zheng Chen, Changze Liu, L. Liu, X. Liu
New physical insights on the underlying physics from switching behaviors to operating mechanisms of oxide-based RRAM are presented by taking the microstructure nature of switching materials and correlated physical effects with switching process into account. Based on the new physical insights, a platform for HfOx- and TaOx-based RRAM including simulation tools and compact models is developed, which is able to reproduce the essential electrical and microscopic characteristics of RRAM and bridge the link between device and circuit systems, meeting the requirements of device-circuit-system co-design and optimization.
{"title":"Oxide-based RRAM: Requirements and challenges of modeling and simulation","authors":"Jinfeng Kang, B. Gao, Peng Huang, Haitong Li, Yudi Zhao, Zheng Chen, Changze Liu, L. Liu, X. Liu","doi":"10.1109/IEDM.2015.7409634","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409634","url":null,"abstract":"New physical insights on the underlying physics from switching behaviors to operating mechanisms of oxide-based RRAM are presented by taking the microstructure nature of switching materials and correlated physical effects with switching process into account. Based on the new physical insights, a platform for HfOx- and TaOx-based RRAM including simulation tools and compact models is developed, which is able to reproduce the essential electrical and microscopic characteristics of RRAM and bridge the link between device and circuit systems, meeting the requirements of device-circuit-system co-design and optimization.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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