Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409637
M. Oda, K. Sakuma, Y. Kamimuta, M. Saitoh
This paper presents the fundamental carrier transport analysis of high-mobility poly-Si nanowire transistors (NW Tr). By adopting advanced SPC (solid-phase crystallization) process, record-high electron mobility (192cm2/Vs) and Ion (200μA/μm) at Ioff of 4nA/μm are achieved without using lasers or catalysts. Carrier density and temperature dependence of mobility, and also physical analysis of poly-Si crystallinity and the channel size, reveal that the origin of mobility degradation in conventional SPC poly-Si Tr. is Coulomb scattering due to defects inside grains as well as defects at grain boundaries and enhanced surface roughness scattering at poly-Si/gate oxide interface, all of which are weakened by advanced SPC process. At high carrier density, mobility of poly-Si nFETs and pFETs by advanced SPC process even exceeds bulk-Si (110) nFETs and (100) pFETs.
{"title":"Carrier transport analysis of high-performance poly-Si Nanowire transistor fabricated by advanced SPC with record-high electron mobility","authors":"M. Oda, K. Sakuma, Y. Kamimuta, M. Saitoh","doi":"10.1109/IEDM.2015.7409637","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409637","url":null,"abstract":"This paper presents the fundamental carrier transport analysis of high-mobility poly-Si nanowire transistors (NW Tr). By adopting advanced SPC (solid-phase crystallization) process, record-high electron mobility (192cm2/Vs) and Ion (200μA/μm) at Ioff of 4nA/μm are achieved without using lasers or catalysts. Carrier density and temperature dependence of mobility, and also physical analysis of poly-Si crystallinity and the channel size, reveal that the origin of mobility degradation in conventional SPC poly-Si Tr. is Coulomb scattering due to defects inside grains as well as defects at grain boundaries and enhanced surface roughness scattering at poly-Si/gate oxide interface, all of which are weakened by advanced SPC process. At high carrier density, mobility of poly-Si nFETs and pFETs by advanced SPC process even exceeds bulk-Si (110) nFETs and (100) pFETs.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127322367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409812
Saungeun Park, Weinan Zhu, Hsiao-Yu Chang, M. Yogeesh, R. Ghosh, S. Banerjee, D. Akinwande
We report on the state of the art sub-μm length (L) flexible two dimensional radio frequency thin film transistors operating in the velocity saturation regime for achieving maximum carrier transport or under high-field. We realize large-area monolayer MoS2 on flexible polyimide with 5 GHz cut-off frequency (fT), a record value for flexible synthesized transitional metal dichalcogenides (TMDs). For higher frequency devices, flexible black phosphorus (BP) RF TFT is demonstrated for the first time with fT ~ 17.5 GHz for L = 0.5 μm, yielding vsat ~ 5.5 × 106 cm/s. In addition, for flexible sub-THz nanosystem front-ends, we have achieved record 100 GHz graphene TFTs (vsat ~ 8.8 × 106 cm/s) on flexible glass, 56% higher than that of graphene TFTs on polymeric substrates.
{"title":"High-frequency prospects of 2D nanomaterials for flexible nanoelectronics from baseband to sub-THz devices","authors":"Saungeun Park, Weinan Zhu, Hsiao-Yu Chang, M. Yogeesh, R. Ghosh, S. Banerjee, D. Akinwande","doi":"10.1109/IEDM.2015.7409812","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409812","url":null,"abstract":"We report on the state of the art sub-μm length (L) flexible two dimensional radio frequency thin film transistors operating in the velocity saturation regime for achieving maximum carrier transport or under high-field. We realize large-area monolayer MoS<sub>2</sub> on flexible polyimide with 5 GHz cut-off frequency (f<sub>T</sub>), a record value for flexible synthesized transitional metal dichalcogenides (TMDs). For higher frequency devices, flexible black phosphorus (BP) RF TFT is demonstrated for the first time with f<sub>T</sub> ~ 17.5 GHz for L = 0.5 μm, yielding v<sub>sat</sub> ~ 5.5 × 10<sup>6</sup> cm/s. In addition, for flexible sub-THz nanosystem front-ends, we have achieved record 100 GHz graphene TFTs (v<sub>sat</sub> ~ 8.8 × 106 cm/s) on flexible glass, 56% higher than that of graphene TFTs on polymeric substrates.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409815
M. Shulaker, G. Hills, Tony F. Wu, Zhenan Bao, H. Wong, S. Mitra
While carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the performance and energy efficiency of digital systems beyond the limitations of silicon CMOS, the presence of metallic CNTs (m-CNTs) remains a major challenge. Existing techniques for removing m-CNTs are inadequate, as they face one or more of the following scalability challenges: scaling to large circuits (≥99.99% of m-CNTs must be removed without inadvertently removing semiconducting CNTs, s-CNTs), scaling to short channel lengths (for highly-scaled contacted gate pitch (CPP)), and scaling to small inter-CNT spacing (for high CNT densities required for high CNFET ION). We demonstrate a new m-CNT removal technique that, for the first time, overcomes all of these scalability challenges, as it: (a) removes ≥99.99% of m-CNTs vs. ≤1% of s-CNTs, (b) scales to any arbitrary CPP, and (c) scales to high CNT densities (≥200 CNTs/μm).
{"title":"Efficient metallic carbon nanotube removal for highly-scaled technologies","authors":"M. Shulaker, G. Hills, Tony F. Wu, Zhenan Bao, H. Wong, S. Mitra","doi":"10.1109/IEDM.2015.7409815","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409815","url":null,"abstract":"While carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the performance and energy efficiency of digital systems beyond the limitations of silicon CMOS, the presence of metallic CNTs (m-CNTs) remains a major challenge. Existing techniques for removing m-CNTs are inadequate, as they face one or more of the following scalability challenges: scaling to large circuits (≥99.99% of m-CNTs must be removed without inadvertently removing semiconducting CNTs, s-CNTs), scaling to short channel lengths (for highly-scaled contacted gate pitch (CPP)), and scaling to small inter-CNT spacing (for high CNT densities required for high CNFET ION). We demonstrate a new m-CNT removal technique that, for the first time, overcomes all of these scalability challenges, as it: (a) removes ≥99.99% of m-CNTs vs. ≤1% of s-CNTs, (b) scales to any arbitrary CPP, and (c) scales to high CNT densities (≥200 CNTs/μm).","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409656
D. Benoit, J. Mazurier, B. Varadarajan, S. Chhun, S. Lagrasta, C. Gaumer, D. Galpin, C. Fenouillet-Béranger, D. Vo-Thanh, D. Barge, R. Duru, R. Beneyton, B. Gong, N. Sun, N. Chauvet, P. Ruault, D. Winandy, B. van Schravendijk, P. Meijer, O. Hinsinger
For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and translates into a 5% decrease for both effective capacitance and delay of FO3 Ring Oscillators in a 14FDSOI technology. In addition, a NMOS breakdown voltage improvement of 3.5V and a decrease in leakage current of 0.7 decade is demonstrated on thick oxide devices. This electrical performance together with the low temperature deposition makes SiCO a very appealing candidate for 3D VLSI in a CoolCube™ integration scheme.
首次从3D VLSI集成的角度评估了400°C沉积的新型SiCO低k间隔材料的兴趣。SiCO低k值(4.5 vs 7 SiN)的优势在整个集成过程中得以保留，并转化为14FDSOI技术中FO3环形振荡器的有效电容和延迟降低5%。此外，在厚氧化物器件上，NMOS击穿电压提高了3.5V，漏电流降低了0.7 decade。这种电气性能加上低温沉积使SiCO成为CoolCube™集成方案中3D超大规模集成电路的非常有吸引力的候选者。
{"title":"Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration","authors":"D. Benoit, J. Mazurier, B. Varadarajan, S. Chhun, S. Lagrasta, C. Gaumer, D. Galpin, C. Fenouillet-Béranger, D. Vo-Thanh, D. Barge, R. Duru, R. Beneyton, B. Gong, N. Sun, N. Chauvet, P. Ruault, D. Winandy, B. van Schravendijk, P. Meijer, O. Hinsinger","doi":"10.1109/IEDM.2015.7409656","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409656","url":null,"abstract":"For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and translates into a 5% decrease for both effective capacitance and delay of FO3 Ring Oscillators in a 14FDSOI technology. In addition, a NMOS breakdown voltage improvement of 3.5V and a decrease in leakage current of 0.7 decade is demonstrated on thick oxide devices. This electrical performance together with the low temperature deposition makes SiCO a very appealing candidate for 3D VLSI in a CoolCube™ integration scheme.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114935562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409633
D. Cornigli, S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani, P. Moens, P. Vanmeerbeek, A. Banerjee, G. Meneghesso
A 2D TCAD-based approach is proposed to investigate the leakage current and breakdown regime of GaN/AlGaN/Si structures at different ambient temperatures. Deep-level traps originated by Carbon doping, impact-ionization generation and thermally activated Poole-Frenkel conduction have been modeled to assess the role of such physical mechanisms on the forward-bias leakage current. A good agreement with experimental data has been obtained by implementing conduction and valence mini-bands within the deeper transition layer created by conductive dislocation defects or by superlattice structures. A 2D isolation device has been investigated up to breakdown and, for the first time to our knowledge, we prove with 2D TCAD simulation that in GaN based devices both impact-ionization and Poole-Frenkel conduction effects must be taken into account to correctly match experimental data.
{"title":"Numerical investigation of the lateral and vertical leakage currents and breakdown regimes in GaN-on-Silicon vertical structures","authors":"D. Cornigli, S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani, P. Moens, P. Vanmeerbeek, A. Banerjee, G. Meneghesso","doi":"10.1109/IEDM.2015.7409633","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409633","url":null,"abstract":"A 2D TCAD-based approach is proposed to investigate the leakage current and breakdown regime of GaN/AlGaN/Si structures at different ambient temperatures. Deep-level traps originated by Carbon doping, impact-ionization generation and thermally activated Poole-Frenkel conduction have been modeled to assess the role of such physical mechanisms on the forward-bias leakage current. A good agreement with experimental data has been obtained by implementing conduction and valence mini-bands within the deeper transition layer created by conductive dislocation defects or by superlattice structures. A 2D isolation device has been investigated up to breakdown and, for the first time to our knowledge, we prove with 2D TCAD simulation that in GaN based devices both impact-ionization and Poole-Frenkel conduction effects must be taken into account to correctly match experimental data.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117176968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409646
R. van Dalen, H. P. Tuinhout, M. Stoutjesdijk, J. van Zwol, J. J. M. Zaal, J. H. J. Janssen, F. H. M. Swartjes, P. A. M. Bastiaansen, M. C. Lammers, L. Brusamarello, M. Stekelenburg
A methodology is presented that allows quantitative prediction of the impact of WLCSP induced mechanical stress on high precision mixed-signal ICs. The simulation flow was tuned using high-resolution experimental variability data measured on dedicated test chips. The methodology is exemplified with an on-chip oscillator circuit suffering from WLCSP stress induced variability.
{"title":"A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits","authors":"R. van Dalen, H. P. Tuinhout, M. Stoutjesdijk, J. van Zwol, J. J. M. Zaal, J. H. J. Janssen, F. H. M. Swartjes, P. A. M. Bastiaansen, M. C. Lammers, L. Brusamarello, M. Stekelenburg","doi":"10.1109/IEDM.2015.7409646","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409646","url":null,"abstract":"A methodology is presented that allows quantitative prediction of the impact of WLCSP induced mechanical stress on high precision mixed-signal ICs. The simulation flow was tuned using high-resolution experimental variability data measured on dedicated test chips. The methodology is exemplified with an on-chip oscillator circuit suffering from WLCSP stress induced variability.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126117091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409721
Kibong Moon, E. Cha, Jaesung Park, Sang-gyun Gi, Myonglae Chu, K. Baek, Byunggeun Lee, S. Oh, H. Hwang
We report novel nanoscale synapse and neuron devices for ultra-high density neuromorphic system. By adopting a Mo electrode, the redox reaction at Mo/Pr0.7Ca0.3MnO3 (PCMO) interface was controlled which in turn significantly improve synapse characteristics such as switching uniformity, disturbance, retention and multi-level data storage under identical pulse condition. Furthermore, The NbO2 based Insulator-Metal Transition (IMT) oscillator was developed for neuron application. Finally, we have experimentally confirmed the realization of pattern recognition with high accuracy using the 11k-bit Mo/PCMO synapse array and NbO2 oscillator neuron.
{"title":"High density neuromorphic system with Mo/Pr0.7Ca0.3MnO3 synapse and NbO2 IMT oscillator neuron","authors":"Kibong Moon, E. Cha, Jaesung Park, Sang-gyun Gi, Myonglae Chu, K. Baek, Byunggeun Lee, S. Oh, H. Hwang","doi":"10.1109/IEDM.2015.7409721","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409721","url":null,"abstract":"We report novel nanoscale synapse and neuron devices for ultra-high density neuromorphic system. By adopting a Mo electrode, the redox reaction at Mo/Pr0.7Ca0.3MnO3 (PCMO) interface was controlled which in turn significantly improve synapse characteristics such as switching uniformity, disturbance, retention and multi-level data storage under identical pulse condition. Furthermore, The NbO2 based Insulator-Metal Transition (IMT) oscillator was developed for neuron application. Finally, we have experimentally confirmed the realization of pattern recognition with high accuracy using the 11k-bit Mo/PCMO synapse array and NbO2 oscillator neuron.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128355527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409670
H. Pan, K. Huang, S. Chen, P. C. Peng, Zhi-Sung Yang, C. Kuo, Y. Chih, Y. King, C. Lin
A fully CMOS process compatible FinFET Dielectric RRAM (FIND RRAM) is firstly proposed and demonstrated by 1kbit RRAM macro on 16nm standard FinFET CMOS logic platform. The new 16nm low voltage FIND RRAM consists of one FinFET transistor for select gate and an HfO2-based resistive film for a storage node of the cell. The FIND RRAM largely improves the set and reset characteristics by the locally enhanced field at fin corners and results in a low set voltage and reset current in array operation. Besides, by adopting the 16nm FinFET CMOS logic process, the FIND RRAM is shrink to an aggressive cell size of 0.07632μm2 without additional mask or process step. The low voltage operation, excellent reliability, and very stable LRS/HRS window are all realized in the new fabricated 1kbit macro. They all support the new FIND RRAM technology is a promising embedded NVM in the coming FinFET era.
{"title":"1Kbit FinFET Dielectric (FIND) RRAM in pure 16nm FinFET CMOS logic process","authors":"H. Pan, K. Huang, S. Chen, P. C. Peng, Zhi-Sung Yang, C. Kuo, Y. Chih, Y. King, C. Lin","doi":"10.1109/IEDM.2015.7409670","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409670","url":null,"abstract":"A fully CMOS process compatible FinFET Dielectric RRAM (FIND RRAM) is firstly proposed and demonstrated by 1kbit RRAM macro on 16nm standard FinFET CMOS logic platform. The new 16nm low voltage FIND RRAM consists of one FinFET transistor for select gate and an HfO2-based resistive film for a storage node of the cell. The FIND RRAM largely improves the set and reset characteristics by the locally enhanced field at fin corners and results in a low set voltage and reset current in array operation. Besides, by adopting the 16nm FinFET CMOS logic process, the FIND RRAM is shrink to an aggressive cell size of 0.07632μm2 without additional mask or process step. The low voltage operation, excellent reliability, and very stable LRS/HRS window are all realized in the new fabricated 1kbit macro. They all support the new FIND RRAM technology is a promising embedded NVM in the coming FinFET era.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127278992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409744
S. Pae, H. Sagong, C. Liu, M. Jin, Y. H. Kim, S. Choo, J. J. Kim, H. J. Kim, S. Yoon, H. Nam, H. Shim, S. M. Park, J. Park, S. Shin, J. Park
We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.
{"title":"Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations","authors":"S. Pae, H. Sagong, C. Liu, M. Jin, Y. H. Kim, S. Choo, J. J. Kim, H. J. Kim, S. Yoon, H. Nam, H. Shim, S. M. Park, J. Park, S. Shin, J. Park","doi":"10.1109/IEDM.2015.7409744","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409744","url":null,"abstract":"We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130234271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409734
M. Hussain, J. Rojas, G. T. Torres Sevilla, A. Hussain, M. Ghoneim, A. Hanna, A. Kutbee, J. M. Nassar, M. Cruz
Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.
{"title":"Free form CMOS electronics: Physically flexible and stretchable","authors":"M. Hussain, J. Rojas, G. T. Torres Sevilla, A. Hussain, M. Ghoneim, A. Hanna, A. Kutbee, J. M. Nassar, M. Cruz","doi":"10.1109/IEDM.2015.7409734","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409734","url":null,"abstract":"Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126675614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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