Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409771
Chando Park, J. Kan, C. Ching, Jaesoo Ahn, L. Xue, Rongjun Wang, A. Kontos, S. Liang, M. Bangar, Hao Chen, S. Hassan, M. Gottwald, Xiaochun Zhu, M. Pakala, Seung H. Kang
This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Heff <; 100 Oe, Δ = 85, Ic (35 ns) = 94 μA, Vbreakdown = 1.5 V, and high endurance (> 1012 write cycles). Reliable switching with small temporal variations (<; 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.
{"title":"Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond","authors":"Chando Park, J. Kan, C. Ching, Jaesoo Ahn, L. Xue, Rongjun Wang, A. Kontos, S. Liang, M. Bangar, Hao Chen, S. Hassan, M. Gottwald, Xiaochun Zhu, M. Pakala, Seung H. Kang","doi":"10.1109/IEDM.2015.7409771","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409771","url":null,"abstract":"This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Heff <; 100 Oe, Δ = 85, Ic (35 ns) = 94 μA, Vbreakdown = 1.5 V, and high endurance (> 1012 write cycles). Reliable switching with small temporal variations (<; 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121369315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409645
Kyung-do Kim, K. Kim, Min-Soo Yoo, Yong-Taik Kim, Sung-Kye Park, Sung-Joo Hong, C. Park, Byung-Gook Park, Jong-Ho Lee
To characterize electrically the effect of the Cu diffusion in TSVs, a new test pattern is proposed and its effectiveness is verified experimentally. The test pattern has a shallow n+ region formed in an n-well region butted to the TSV dielectric surrounding the TSV. Through the n+/n well region, we can measure the diode and gated diode currents, the charge pumping current, and C-V to accurately analyze the effect. Our approach is demonstrated to be very useful by investigating the Cu diffusion effect in samples with two different barrier metal thicknesses.
{"title":"A novel method to characterize the effect from the diffusion of Cu in through silicon via (TSV)","authors":"Kyung-do Kim, K. Kim, Min-Soo Yoo, Yong-Taik Kim, Sung-Kye Park, Sung-Joo Hong, C. Park, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/IEDM.2015.7409645","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409645","url":null,"abstract":"To characterize electrically the effect of the Cu diffusion in TSVs, a new test pattern is proposed and its effectiveness is verified experimentally. The test pattern has a shallow n+ region formed in an n-well region butted to the TSV dielectric surrounding the TSV. Through the n+/n well region, we can measure the diode and gated diode currents, the charge pumping current, and C-V to accurately analyze the effect. Our approach is demonstrated to be very useful by investigating the Cu diffusion effect in samples with two different barrier metal thicknesses.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114365340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409741
S. Shin, M. A. Wahab, W. Ahn, A. Ziabari, K. Maize, A. Shakouri, M. Alam
Extremely thin silicon-on-insulator (ETSOI) structure has been developed to improve gate control and to suppress the short-channel effect (SCE) associated with bulk MOSFET. However, since self-heating in ETSOI may compromise both performance and reliability, a careful analysis of the trade-off between short-channel control and self-heating is needed. In this paper, we (i) characterize channel and surface self-heating of a ETSOI technology as a function of channel thickness (Tsi) and length (Lch) using electrical and optical methods, respectively; (ii) theoretically interpret the trade-off between gate controllability and self-heating effects, (iii) correlate HCI degradation to the degree of self-heating, and (vi) find distinctive universality of HCI degradation (as a function of Tsi and Lch) that enables a long term reliability projection. We conclude that the trade-off between HCI and channel control suggests that thinnest channel may not be optimum; and that the universality of HCI degradation would hold only if self-heating is accounted for.
{"title":"Fundamental trade-off between short-channel control and hot carrier degradation in an extremely-thin silicon-on-insulator (ETSOI) technology","authors":"S. Shin, M. A. Wahab, W. Ahn, A. Ziabari, K. Maize, A. Shakouri, M. Alam","doi":"10.1109/IEDM.2015.7409741","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409741","url":null,"abstract":"Extremely thin silicon-on-insulator (ETSOI) structure has been developed to improve gate control and to suppress the short-channel effect (SCE) associated with bulk MOSFET. However, since self-heating in ETSOI may compromise both performance and reliability, a careful analysis of the trade-off between short-channel control and self-heating is needed. In this paper, we (i) characterize channel and surface self-heating of a ETSOI technology as a function of channel thickness (Tsi) and length (Lch) using electrical and optical methods, respectively; (ii) theoretically interpret the trade-off between gate controllability and self-heating effects, (iii) correlate HCI degradation to the degree of self-heating, and (vi) find distinctive universality of HCI degradation (as a function of Tsi and Lch) that enables a long term reliability projection. We conclude that the trade-off between HCI and channel control suggests that thinnest channel may not be optimum; and that the universality of HCI degradation would hold only if self-heating is accounted for.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114822419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409693
P. Eyben, T. Chiarella, S. Kubicek, H. Bender, O. Richard, J. Mitard, A. Mocuta, N. Horiguchi, A. Thean
Site-specific real three-dimensional (3D) carrier profiling in sub-10nm WFIN devices is demonstrated for the first time. Extension-gate overlap, active dopant concentration and distribution inside extensions and epi source/drain are observed with 1 nm-spatial resolution along X, Y and Z-directions. Using this new technique providing full 3D-carrier mapping we analyzed different processing flows for sub-10nm fin width FinFETs, identified possible failure mechanisms, and demonstrated the direct link between improved performance and 3D-carrier distribution at the nm-scale.
{"title":"Scalpel soft retrace scanning spreading resistance microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET","authors":"P. Eyben, T. Chiarella, S. Kubicek, H. Bender, O. Richard, J. Mitard, A. Mocuta, N. Horiguchi, A. Thean","doi":"10.1109/IEDM.2015.7409693","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409693","url":null,"abstract":"Site-specific real three-dimensional (3D) carrier profiling in sub-10nm WFIN devices is demonstrated for the first time. Extension-gate overlap, active dopant concentration and distribution inside extensions and epi source/drain are observed with 1 nm-spatial resolution along X, Y and Z-directions. Using this new technique providing full 3D-carrier mapping we analyzed different processing flows for sub-10nm fin width FinFETs, identified possible failure mechanisms, and demonstrated the direct link between improved performance and 3D-carrier distribution at the nm-scale.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114876537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409806
M. Berg, Karl‐Magnus Persson, Olli-Pekka Kilpi, J. Svensson, E. Lind, L. Wernersson
In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on- and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
{"title":"Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si","authors":"M. Berg, Karl‐Magnus Persson, Olli-Pekka Kilpi, J. Svensson, E. Lind, L. Wernersson","doi":"10.1109/IEDM.2015.7409806","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409806","url":null,"abstract":"In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on- and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124521323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409749
Yu-Hsun Chen, Chin-Yu Chen, Cheng-Lin Cho, C. Hsieh, Yung-Chun Wu, K. Chang-Liao, Yung-Hsien Wu
HK-2/HK-1 stacked dielectric was proposed as the gate dielectric for sub-20 nm FinFET technology. Compared to single HK-1 dielectric, the stacked gate dielectric exhibits superior performance in terms of improved drive current by 20~22% and increased transconductance by ~22%. The main reason accounting for the better performance, besides the higher gate capacitance by 4%, is the enhanced carrier mobility by ~33% resulting from less remote scattering due to smaller amount of charged oxygen vacancies which was physically confirmed by EELS and XPS. Owing to the reduced oxygen vacancies, from bias temperature instability and lifetime test, the stacked gate dielectric demonstrates augmented reliability as well. Most importantly, HK-1 and HK-2 are common dielectrics completely compatible with typical processes, rendering the stacked dielectric a promising one for next-generation FinFETs technology.
{"title":"Enhanced sub 20-nm FinFET performance by stacked gate dielectric with less oxygen vacancies featuring higher current drive capability and superior reliability","authors":"Yu-Hsun Chen, Chin-Yu Chen, Cheng-Lin Cho, C. Hsieh, Yung-Chun Wu, K. Chang-Liao, Yung-Hsien Wu","doi":"10.1109/IEDM.2015.7409749","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409749","url":null,"abstract":"HK-2/HK-1 stacked dielectric was proposed as the gate dielectric for sub-20 nm FinFET technology. Compared to single HK-1 dielectric, the stacked gate dielectric exhibits superior performance in terms of improved drive current by 20~22% and increased transconductance by ~22%. The main reason accounting for the better performance, besides the higher gate capacitance by 4%, is the enhanced carrier mobility by ~33% resulting from less remote scattering due to smaller amount of charged oxygen vacancies which was physically confirmed by EELS and XPS. Owing to the reduced oxygen vacancies, from bias temperature instability and lifetime test, the stacked gate dielectric demonstrates augmented reliability as well. Most importantly, HK-1 and HK-2 are common dielectrics completely compatible with typical processes, rendering the stacked dielectric a promising one for next-generation FinFETs technology.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115983088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409835
A. Seabaugh, S. Fathipour, Wenjun Li, Hao Lu, J. Park, A. Kummel, D. Jena, S. Fullerton‐Shirey, P. Fay
As the understanding of tunnel field-effect transistors (TFET) advances, new approaches are emerging to lower off-currents, lower defect density in tunnel junctions, and to increase the highest current at which the subthreshold swing of 60 mV/decade (I60) appears. III-N heterojunctions and transition-metal-dichalcogenide (TMD) materials are forcing some new thinking in junction design and doping.
{"title":"Steep subthreshold swing tunnel FETs: GaN/InN/GaN and transition metal dichalcogenide channels","authors":"A. Seabaugh, S. Fathipour, Wenjun Li, Hao Lu, J. Park, A. Kummel, D. Jena, S. Fullerton‐Shirey, P. Fay","doi":"10.1109/IEDM.2015.7409835","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409835","url":null,"abstract":"As the understanding of tunnel field-effect transistors (TFET) advances, new approaches are emerging to lower off-currents, lower defect density in tunnel junctions, and to increase the highest current at which the subthreshold swing of 60 mV/decade (I60) appears. III-N heterojunctions and transition-metal-dichalcogenide (TMD) materials are forcing some new thinking in junction design and doping.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131434766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409700
G. Nicosia, G. M. Paolucci, C. M. Compagnoni, D. Resnati, C. Miccoli, A. Spinelli, A. Lacaita, A. Visconti, A. Goda
We present the first single-electron analysis of the program operation of NAND Flash arrays. The analysis leads, first of all, to a direct extraction not only of the average value but also of the statistical spread of the control-gate to floating-gate cell capacitance (Cpp). This allows, then, to assess the impact of Cpp variability, electron injection statistics and read noise on the distribution of the threshold-voltage shift coming from a programming pulse applied to the array cells. Finally, the electron leakage through the inter-gate dielectric along program is easily and directly quantified under real operating conditions.
{"title":"A single-electron analysis of NAND flash memory programming","authors":"G. Nicosia, G. M. Paolucci, C. M. Compagnoni, D. Resnati, C. Miccoli, A. Spinelli, A. Lacaita, A. Visconti, A. Goda","doi":"10.1109/IEDM.2015.7409700","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409700","url":null,"abstract":"We present the first single-electron analysis of the program operation of NAND Flash arrays. The analysis leads, first of all, to a direct extraction not only of the average value but also of the statistical spread of the control-gate to floating-gate cell capacitance (Cpp). This allows, then, to assess the impact of Cpp variability, electron injection statistics and read noise on the distribution of the threshold-voltage shift coming from a programming pulse applied to the array cells. Finally, the electron leakage through the inter-gate dielectric along program is easily and directly quantified under real operating conditions.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132067316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409782
T. Chu, Zhihong Chen
Bandgap engineering is a powerful technique for the design of new electronic and optoelectronic devices. Different from traditional approaches that rely on sophisticated material synthesis systems, we demonstrate that bandgap engineering is feasible in 2D layered materials through electric field control. We will show that a bandgap of ~200meV can be opened in bilayer graphene, while a large bandgap reduction is achievable in bilayer MoS2. More importantly, this spontaneous field-controlled bandgap tuning occurs during device operation, which creates a new platform to design novel electronic devices with dynamic bandwidth.
{"title":"Bandgap engineering in 2D layered materials","authors":"T. Chu, Zhihong Chen","doi":"10.1109/IEDM.2015.7409782","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409782","url":null,"abstract":"Bandgap engineering is a powerful technique for the design of new electronic and optoelectronic devices. Different from traditional approaches that rely on sophisticated material synthesis systems, we demonstrate that bandgap engineering is feasible in 2D layered materials through electric field control. We will show that a bandgap of ~200meV can be opened in bilayer graphene, while a large bandgap reduction is achievable in bilayer MoS2. More importantly, this spontaneous field-controlled bandgap tuning occurs during device operation, which creates a new platform to design novel electronic devices with dynamic bandwidth.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132134295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409672
An Chen
The stochastic behavior and intrinsic variability of resistive random access memory (RRAM) can be utilized to implement physical unclonable function (PUF) for hardware security applications. Performance of RRAM PUF depends on RRAM device characteristics. Reliability of RRAM PUF may degrade with retention loss, read instability and thermal variation, while PUF uniqueness is maintained as long as the randomness in RRAM resistance distribution is preserved. Based on key PUF metrics, this paper presents a systematic approach for a comprehensive evaluation of this novel application of RRAM.
{"title":"Comprehensive assessment of RRAM-based PUF for hardware security applications","authors":"An Chen","doi":"10.1109/IEDM.2015.7409672","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409672","url":null,"abstract":"The stochastic behavior and intrinsic variability of resistive random access memory (RRAM) can be utilized to implement physical unclonable function (PUF) for hardware security applications. Performance of RRAM PUF depends on RRAM device characteristics. Reliability of RRAM PUF may degrade with retention loss, read instability and thermal variation, while PUF uniqueness is maintained as long as the randomness in RRAM resistance distribution is preserved. Based on key PUF metrics, this paper presents a systematic approach for a comprehensive evaluation of this novel application of RRAM.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134124187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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