Pub Date : 2014-08-11DOI: 10.1109/ISTDM.2014.6874642
Dong Wang, Sho Kamezawa, K. Yamamoto, H. Nakashima
As a promising material for fabricating on-chip optoelectronic devices, germanium (Ge) has a direct band gap of 0.8 eV, which matches with the wavelength for optical communication. The energy difference is only 134 meV between direct and indirect band gaps, implying the possibility of a direct band gap light emission. In general, a p-i-n diode structure is used for a Ge photo emitter, of which fabrication process is relatively complicated and high-quality n-type doping is still an issue. Recently we achieved high Schottky barrier heights for electrons ΦBN = 0.60 eV (HfGe/n-Ge) and holes ΦBP = 0.57 eV (TiN/p-Ge) [1,2]. Based on this technology, we demonstrate direct band gap room temperature electroluminescence (EL) from bulk Ge using a fin-type asymmetric metel/Ge/metal (HfGe/Ge/TiN) structure.
锗(Ge)具有0.8 eV的直接带隙，与光通信的波长相匹配，是一种很有前途的片上光电器件材料。直接带隙和间接带隙之间的能量差仅为134 meV，这意味着直接带隙发光的可能性。一般来说，锗光发射极采用p-i-n二极管结构，其制作工艺相对复杂，高质量的n型掺杂仍然是一个问题。最近我们实现了电子ΦBN = 0.60 eV (HfGe/n-Ge)和空穴ΦBP = 0.57 eV (TiN/p-Ge)的高肖特基势垒高度[1,2]。基于该技术，我们利用翅片型不对称金属/锗/金属(HfGe/Ge/TiN)结构，演示了块状锗的直接带隙室温电致发光(EL)。
{"title":"Direct band gap electroluminescence from bulk germanium at room temperature using an asymmetric metal/germanium/metal structure","authors":"Dong Wang, Sho Kamezawa, K. Yamamoto, H. Nakashima","doi":"10.1109/ISTDM.2014.6874642","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874642","url":null,"abstract":"As a promising material for fabricating on-chip optoelectronic devices, germanium (Ge) has a direct band gap of 0.8 eV, which matches with the wavelength for optical communication. The energy difference is only 134 meV between direct and indirect band gaps, implying the possibility of a direct band gap light emission. In general, a p-i-n diode structure is used for a Ge photo emitter, of which fabrication process is relatively complicated and high-quality n-type doping is still an issue. Recently we achieved high Schottky barrier heights for electrons ΦBN = 0.60 eV (HfGe/n-Ge) and holes ΦBP = 0.57 eV (TiN/p-Ge) [1,2]. Based on this technology, we demonstrate direct band gap room temperature electroluminescence (EL) from bulk Ge using a fin-type asymmetric metel/Ge/metal (HfGe/Ge/TiN) structure.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874671
Lingzi Li, Wei Wang, E. Tok, Y. Yeo
Formation of Sn wires on Ge0.83Sn0.17 layer during annealing was discovered. The phenomenon observed may be explained by surface undulation, Sn segregation and aggregation.
{"title":"Strain-induced morphological instability and self assembly of tin wires during controlled annealing of Ge0.83Sn0.17 epitaxial film on Ge(001) substrate","authors":"Lingzi Li, Wei Wang, E. Tok, Y. Yeo","doi":"10.1109/ISTDM.2014.6874671","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874671","url":null,"abstract":"Formation of Sn wires on Ge<sub>0.83</sub>Sn<sub>0.17</sub> layer during annealing was discovered. The phenomenon observed may be explained by surface undulation, Sn segregation and aggregation.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127376438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874657
K. Tan, W. Loke, S. Wicaksono, S. Yoon, S. Subramanian, Qian Zhou, Y. Yeo
Low defect InAs layers have been successfully grown on a GeOI substrate for the first time. The epitaxial structure grown allows the co-existence Si, Ge and InAs material on a single wafer. TEM and AFM results showed a low defect density and smooth InAs surface, respectively.
{"title":"Growth of indium arsenide on silicon-based substrates using molecular beam epitaxy","authors":"K. Tan, W. Loke, S. Wicaksono, S. Yoon, S. Subramanian, Qian Zhou, Y. Yeo","doi":"10.1109/ISTDM.2014.6874657","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874657","url":null,"abstract":"Low defect InAs layers have been successfully grown on a GeOI substrate for the first time. The epitaxial structure grown allows the co-existence Si, Ge and InAs material on a single wafer. TEM and AFM results showed a low defect density and smooth InAs surface, respectively.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126957981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874624
F. Montalenti, M. Salvalaglio, A. Marzegalli, P. Zaumseil, G. Capellini, T. Schulli, M. Schubert, Y. Yamamoto, B. Tillack, T. Schroeder
In this paper, we revisited the so-called "compliance" heteroepitaxy concept which was e.g. reported by Hirth and Lothe already in the early sixties. The vision of this concept is to shift the critical thickness for plastic relaxation by defect injection of a growing heteroepitaxial thin film structure on a substrate to infinity. In other words, in case of the Ge/Si heterosystem, defect free Ge heterostructures on Si(001) without threading arm defects in the volume of the Ge film and without misfit dislocations at the Ge/Si heterostructure interface would result. To achieve this goal, the compliance approach is based on a subtle strain partitioning between Ge film and Si substrate so that the increasing mismatch strain is not only absorbed in the epitaxial Ge film but also in part into the Si substrate. As Hirth and Lothe proposed the use of nanometer thick and thus unrealistically thin Si substrates, it was our goal to establish compliant growth for the Ge/Si heterosystem under Si CMOS compatible conditions.
{"title":"Si CMOS compatible, compliant integration of lattice-mismatched semiconductors on Si(001): Example of fully coherent Ge/Si nanostructures","authors":"F. Montalenti, M. Salvalaglio, A. Marzegalli, P. Zaumseil, G. Capellini, T. Schulli, M. Schubert, Y. Yamamoto, B. Tillack, T. Schroeder","doi":"10.1109/ISTDM.2014.6874624","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874624","url":null,"abstract":"In this paper, we revisited the so-called \"compliance\" heteroepitaxy concept which was e.g. reported by Hirth and Lothe already in the early sixties. The vision of this concept is to shift the critical thickness for plastic relaxation by defect injection of a growing heteroepitaxial thin film structure on a substrate to infinity. In other words, in case of the Ge/Si heterosystem, defect free Ge heterostructures on Si(001) without threading arm defects in the volume of the Ge film and without misfit dislocations at the Ge/Si heterostructure interface would result. To achieve this goal, the compliance approach is based on a subtle strain partitioning between Ge film and Si substrate so that the increasing mismatch strain is not only absorbed in the epitaxial Ge film but also in part into the Si substrate. As Hirth and Lothe proposed the use of nanometer thick and thus unrealistically thin Si substrates, it was our goal to establish compliant growth for the Ge/Si heterosystem under Si CMOS compatible conditions.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115996028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874638
Y. Yamamoto, R. Kurps, Juichi Murota, B. Tillack
Results of arsenic atomic layer doping in Si (100) are presented in this study. Arsenic adsorption and segregation behavior on the Si(100) surface are also discussed. SIMS and four-point probe methods are used for As profile and dosage measurements.
{"title":"Arsenic atomic layer doping in Si using AsH3","authors":"Y. Yamamoto, R. Kurps, Juichi Murota, B. Tillack","doi":"10.1109/ISTDM.2014.6874638","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874638","url":null,"abstract":"Results of arsenic atomic layer doping in Si (100) are presented in this study. Arsenic adsorption and segregation behavior on the Si(100) surface are also discussed. SIMS and four-point probe methods are used for As profile and dosage measurements.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128286159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874696
S. Takagi, M. Takenaka
CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future [1, 2]. There can be several CMOS structures using III-V/Ge channels, as schematically shown in Fig. 1. Viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies of III-V/Ge MOS devices. Here, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of SCEs by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs, as shown in Fig. 2. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. As for Ge-based CMOS, easy integration of GOI/SGOI is possible under the present SOI/sSOI platform. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks. Our approach for the channel formation is the wafer bonding and the Ge condensation. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeOx-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT.
{"title":"III–V/Ge CMOS device technologies for future logic LSIs","authors":"S. Takagi, M. Takenaka","doi":"10.1109/ISTDM.2014.6874696","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874696","url":null,"abstract":"CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future [1, 2]. There can be several CMOS structures using III-V/Ge channels, as schematically shown in Fig. 1. Viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies of III-V/Ge MOS devices. Here, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of SCEs by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs, as shown in Fig. 2. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. As for Ge-based CMOS, easy integration of GOI/SGOI is possible under the present SOI/sSOI platform. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks. Our approach for the channel formation is the wafer bonding and the Ge condensation. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeOx-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127621276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874637
Yan Liu, Jing Yan, G. Han, Hongjuan Wang, Mingshan Liu, Chunfu Zhang, B. Cheng, Y. Hao
We developed process flow for GeSn pMOSFET fabrication with in situ low temperature Si2H6 passivation module. High performance Ge0.96Sn0.04 pMOSFETs were fabricated. At a Qmv of 6×1012 cm-2, a 24% enhancement in μeff is demonstrated in Ge0.96Sn0.04 pMOSFETs compared to Ge control.
{"title":"Strained Ge0.96Sn0.04 P-channel MOSFETs with in situ low temperature Si2H6 surface passivation","authors":"Yan Liu, Jing Yan, G. Han, Hongjuan Wang, Mingshan Liu, Chunfu Zhang, B. Cheng, Y. Hao","doi":"10.1109/ISTDM.2014.6874637","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874637","url":null,"abstract":"We developed process flow for GeSn pMOSFET fabrication with in situ low temperature Si<sub>2</sub>H<sub>6</sub> passivation module. High performance Ge<sub>0.96</sub>Sn<sub>0.04</sub> pMOSFETs were fabricated. At a Q<sub>mv</sub> of 6×10<sup>12</sup> cm<sup>-2</sup>, a 24% enhancement in μ<sub>eff</sub> is demonstrated in Ge<sub>0.96</sub>Sn<sub>0.04</sub> pMOSFETs compared to Ge control.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131384518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874633
T. Sadoh, J. Park, M. Kurosawa, M. Miyao
Development of a low-temperature (≤250°C) formation technique of orientation-controlled large-grain (<;10 μm) SiGe on insulator is essential to realize flexible electronics, where various advanced devices are integrated on flexible plastic substrates (softening temperature: ~300°C). This is because SiGe provides higher carrier mobility and superior optical properties compared with Si, as well as epitaxial template of various functional materials. In line with this, we have been developing metal-induced crystallization of SiGe. This achieves selectively (100)- or (111)-oriented large-grain (≥20 μm) SiGe at low temperatures (~250°C) [1-4]. Present paper reviews our recent progress in this novel growth technique.
{"title":"Ultralow-temperature catalyst-induced-crystallization of SiGe on plastic for flexible electronics","authors":"T. Sadoh, J. Park, M. Kurosawa, M. Miyao","doi":"10.1109/ISTDM.2014.6874633","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874633","url":null,"abstract":"Development of a low-temperature (≤250°C) formation technique of orientation-controlled large-grain (<;10 μm) SiGe on insulator is essential to realize flexible electronics, where various advanced devices are integrated on flexible plastic substrates (softening temperature: ~300°C). This is because SiGe provides higher carrier mobility and superior optical properties compared with Si, as well as epitaxial template of various functional materials. In line with this, we have been developing metal-induced crystallization of SiGe. This achieves selectively (100)- or (111)-oriented large-grain (≥20 μm) SiGe at low temperatures (~250°C) [1-4]. Present paper reviews our recent progress in this novel growth technique.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130100838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874650
F. Benistant, M. Bazizi, L. Jiang, J. H. B. Tng, M. H. J. Goh
3D TCAD process and device simulations are used to gain physical understanding and to optimize the performance of bulk-FinFETs. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. For the first time, the full FinFET process flow simulation was performed using diffusion. activation and segregation models identical to those used in planar technology nodes. Thus, all the calibration methodologies and results gained previously in 2D TCAD could be re-used for the 3D FinFET process calibration. The simulated 3D doping and stress profiles are integrated as input to the device simulations. In this work, the 3D simulation results show good agreement with experimental data in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.
{"title":"Full 3D process/device simulations re-using 2D TCAD knowledge for optimizing N and P-type FinFET transistors","authors":"F. Benistant, M. Bazizi, L. Jiang, J. H. B. Tng, M. H. J. Goh","doi":"10.1109/ISTDM.2014.6874650","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874650","url":null,"abstract":"3D TCAD process and device simulations are used to gain physical understanding and to optimize the performance of bulk-FinFETs. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. For the first time, the full FinFET process flow simulation was performed using diffusion. activation and segregation models identical to those used in planar technology nodes. Thus, all the calibration methodologies and results gained previously in 2D TCAD could be re-used for the 3D FinFET process calibration. The simulated 3D doping and stress profiles are integrated as input to the device simulations. In this work, the 3D simulation results show good agreement with experimental data in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130945004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-02DOI: 10.1109/ISTDM.2014.6874700
J. Kouvetakis, J. Menéndez
Significant advances have been achieved in the development and applications of Si-Ge-Sn materials over the past few years, with several groups demonstrating high performance optoelectronic devices with characteristics beyond those achievable with pure Ge. In this presentation we review synthesis, optical properties and preliminary device studies of crystalline Ge1-ySny and Ge1-X-ySiiSny alloys developed at ASU.
{"title":"Epitaxy of light emitting SiGeSn materials using novel precursors","authors":"J. Kouvetakis, J. Menéndez","doi":"10.1109/ISTDM.2014.6874700","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874700","url":null,"abstract":"Significant advances have been achieved in the development and applications of Si-Ge-Sn materials over the past few years, with several groups demonstrating high performance optoelectronic devices with characteristics beyond those achievable with pure Ge. In this presentation we review synthesis, optical properties and preliminary device studies of crystalline Ge1-ySny and Ge1-X-ySiiSny alloys developed at ASU.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127411232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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