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2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)最新文献

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Fabrication of germanium-on-insulator (GOI) with improved threading dislocation density (TDD) via buffer-less epitaxy and bonding 通过无缓冲外延和键合制备具有提高螺纹位错密度(TDD)的绝缘子上锗(GOI)
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874660
K. Lee, Shuyu Bao, G. Y. Chong, Yew Heng Tan, E. Fitzgerald, C. S. Tan
The GOI substrate is fabricated through buffer-less epitaxy (the growth of Ge on Si), bonding and layer transfer. The misfit dislocations which are previously “buried” along the Ge/Si interface are now accessible from the top surface. Through TDD reduction method, the TDD is reduced by at least two orders of magnitude. Hence, a Ge epilayer with lower TDD can be realized and useful for subsequent III-V integration and device fabrication.
GOI衬底是通过无缓冲外延(Ge在Si上生长)、键合和层转移制备的。以前沿Ge/Si界面“埋藏”的失配位错现在可以从顶部表面进入。通过TDD降低方法,将TDD降低至少两个数量级。因此,可以实现具有较低TDD的Ge脱膜,并可用于后续的III-V集成和器件制造。
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引用次数: 1
A reliable 40 GHz opto-electrical system for characterization of frequency response of Ge PIN photo detectors 一种可靠的40 GHz光电系统用于Ge PIN光电探测器的频率响应表征
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874649
Wogong Zhang, Kaiheng Ye, S. Bechler, K. Ulbricht, M. Oehme, E. Kasper, J. Schulze
This study presents calibration of a self-built 40 GHz measurement setup using vector network analyzer and Mach-Zehnder modulator. The setup is used for frequency response characterization of Ge PIN photodetectors.
本文介绍了利用矢量网络分析仪和马赫-曾德调制器对自建的40ghz测量装置进行校准。该装置用于锗PIN光电探测器的频率响应表征。
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引用次数: 0
Spin accumulation in n-Ge on Si with sputtered Mn5Ge3C0.8-contacts 溅射mn5ge3c0.8触点的Si上n-Ge自旋积累
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874647
I. Fischer, Li-Te Chang, C. Surgers, S. Chiussi, Kang L. Wang, J. Schulze
We demonstrate electrical injection of spin-polarized electrons from sputtered Mn5Ge3C0.8 contacts into degenerately doped n-Ge layers on Si as an important step towards integrating spin injection into Ge channels into a CMOS-compatible fabrication process.
我们证明了自旋极化电子从溅射的Mn5Ge3C0.8触点注入到Si上简并掺杂的n-Ge层中,这是将自旋注入到Ge通道中集成到cmos兼容制造工艺中的重要一步。
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引用次数: 0
III/V on large diameter silicon substrates using LPCVD germanium templates 在大直径硅衬底上使用LPCVD锗模板的III/V
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874678
R. Harper, A. Morgan, A. Liu, A. Snyder, D. Hartzell, J. Fastenau, D. Lubychev
We describe the use of LPCVD grown Ge layers on off-axis silicon wafers (200mm) as suitable templates for growth of subsequent III/V layers using solid source molecular beam epitaxy (MBE). A reproducible process for direct III-V semiconductor growth on Ge-coated Si substrates [1,2] has been developed using both single-wafer R&D MBE systems (Veeco GEN-III model) and multi-wafer production tools (Oxford V-100). Epitaxial growths have included GaAs- and InP-based structures. The structural properties of the III-V epilayers have been evaluated using optical microscopy, AFM, and (004) high-resolution x-ray diffraction (HRXRD).
我们描述了在离轴硅片(200mm)上使用LPCVD生长的Ge层作为使用固体源分子束外延(MBE)生长后续III/V层的合适模板。利用单晶片研发MBE系统(Veeco GEN-III模型)和多晶片生产工具(Oxford V-100),已经开发出了在ge涂层Si衬底上直接生长III-V半导体的可重复工艺[1,2]。外延生长包括GaAs和inp基结构。利用光学显微镜、原子力显微镜(AFM)和(004)高分辨率x射线衍射(HRXRD)对III-V型涂层的结构特性进行了评价。
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引用次数: 0
Impact of stressors in future SiGe-based FinFETs: Mobility boost and scalability 压力源对未来基于sigf的finfet的影响:移动性提升和可扩展性
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874646
G. Eneman, D. Brunco, L. Witters, J. Mitard, A. Hikavyy, A. De Keersgieter, P. Roussel, R. Loo, A. Veloso, N. Horiguchi, N. Collaert, A. Thean
S/D epitaxial layers and SRBs are the most effective stressors in scaled FinFETs. While S/D stressors are well established, for SRBs the remaining technical difficulties are significant. However, its expected performance boost and enhanced scalability makes developing SRBs worthwhile, especially when combined with alternative channel materials.
S/D外延层和srb是缩放finfet中最有效的应力源。虽然S/D压力源已经建立,但对于srb来说,仍然存在重大的技术困难。然而,其预期的性能提升和增强的可扩展性使得开发srb是值得的,特别是当与其他通道材料结合使用时。
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引用次数: 1
Phosphorus delta-doping in germanium 磷在锗中的δ掺杂
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874623
Giordano Scappucci
We have demonstrated that phosphorus delta-doping of germanium in ultra-high vacuum is a promising technique to tune doping at high densities (>1020 cm-3) in thin Ge films. Eventually, high doping densities on demand for photonic or electronic applications may be delivered by suitably choosing the total number of layers, tuning their separation in the δ-layer stack, and engineering the amount of P incorporated in each layer.
我们已经证明,在超高真空中磷δ掺杂锗是一种很有前途的技术,可以在高密度(>1020 cm-3)的锗薄膜中调谐掺杂。最终,光子或电子应用所需的高掺杂密度可以通过适当选择层的总数,调整它们在δ层堆栈中的分离,以及设计每层中P的掺入量来实现。
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引用次数: 2
Effect of Sn-doped Ge insertion layers on epitaxial growth of ferromagnetic Fe3Si films on a flexible substrate 掺锡Ge插入层对柔性衬底上铁磁Fe3Si薄膜外延生长的影响
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874683
H. Higashi, Y. Fujita, M. Kawano, J. Hirayama, S. Yamada, Jong-Hyeok Park, T. Sadoh, M. Miyao, K. Hamaya
By an insertion of a Ge(Sn) layer and its CMP treatments, we have improved the crystalline and magnetic characteristics of one of the Heusler-compounds, Fe3Si, on (111)-oriented Ge on a flexible substrate. This work is a first step of high-performance flexible spintronics for flexible system-in-display devices.
通过插入Ge(Sn)层及其CMP处理,我们改善了一种heusler化合物Fe3Si在柔性衬底上(111)取向Ge上的晶体和磁性。这项工作是柔性显示系统器件高性能柔性自旋电子学的第一步。
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引用次数: 0
Revealing the high room and low temperature mobilities of 2D holes in a strained Ge quantum well heterostructures grown on a standard Si(001) substrate 揭示了在标准Si(001)衬底上生长的应变Ge量子阱异质结构中二维空穴的高室温和低温迁移率
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874628
M. Myronov, C. Morrison, J. Halpin, S. Rhead, J. Foronda, D. Leadley
We report an extremely high 2DHG mobility of 4500 cm2V-1s-1 and 777000 cm2V-1s-1 at 293 and 0.333 K, respectively, in a compressively strained Ge QW grown by industrial type RP-CVD on a standard Si(001) substrate. The obtained 2DHG mobility is substantially higher than those reported so far and in structures grown by research type epitaxial growth techniques, i.e. SS-MBE and LEPE-CVD. Also, the room and low temperature hole mobilities obtained are the highest not only among the group-IV Si and Ge based semiconductors, but also among p-type III-V and II-VI ones. These results demonstrate the very high quality of the strained Ge QW epilayers grown by RP-CVD and the huge potential for further applications of such materials in modern and future CMOS, p-MOSFET and p-MODFET electronic devices. The 2DHG mobility is already sufficiently high to fabricate sub-100 nm electronic devices and demonstrate ballistic transport therein at or around room temperature.
在标准Si(001)衬底上通过工业型RP-CVD生长的压缩应变Ge QW中,在293 K和0.333 K下,2DHG迁移率分别为4500 cm2V-1s-1和777000 cm2V-1s-1。所获得的2DHG迁移率大大高于迄今为止报道的,并且在研究型外延生长技术(即SS-MBE和LEPE-CVD)中生长的结构中。得到的室温和低温空穴迁移率不仅在iv族Si和Ge基半导体中最高,而且在III-V和II-VI型半导体中也最高。这些结果证明了RP-CVD生长的应变Ge QW薄膜的高质量,以及这种材料在现代和未来CMOS, p-MOSFET和p-MODFET电子器件中的进一步应用的巨大潜力。2DHG的迁移率已经足够高,可以制造低于100纳米的电子器件,并在室温或室温附近演示其中的弹道传输。
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引用次数: 5
Migration enhanced epitaxy of InGaP on offcut Ge (001) using solid-source molecular beam epitaxy 基于固体源分子束外延的InGaP在Ge(001)上的迁移增强外延
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874658
W. Loke, Qian Zhou, X. Gong, M. Owen, S. Wicaksono, K. Tan, Y. Yeo, S. Yoon
MEE growth of InGaP on a (001) oriented Ge surface with 10° offcut on GeOI substrate was presented. TEM inspection shows good crystalline quality of InGaP material on Ge surface. Further study is required to further optimize the MEE-InGaP process for defect-free InGaP/Ge interface and subsequent epilayers.
研究了InGaP在(001)取向Ge表面(10°切边)上在GeOI衬底上的MEE生长。TEM检测表明,在Ge表面,InGaP材料的结晶质量良好。为了实现无缺陷的InGaP/Ge界面和后续的涂层,需要进一步优化MEE-InGaP工艺。
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引用次数: 1
A study of hole mobility in the inversion layer of relaxed and strained SiGe PMOS devices 松弛和应变SiGe PMOS器件反转层空穴迁移率的研究
Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874629
K.-T. Chen, S. T. Chang
The hole mobility performance in strained SiGe PMOS devices is studied. Calculations have then been used for considering the impact of device structures including BULK, SOI, and DG, SiGe materials, alloy scattering and biaxial compressive strain owing to (001), (110), and (111) Si substrate orientation on the hole mobility performance to give an indication of the potential performance of this potential PMOS device.
研究了应变SiGe PMOS器件的空穴迁移性能。然后,计算用于考虑器件结构(包括BULK、SOI和DG)、SiGe材料、合金散射和(001)、(110)和(111)Si衬底取向对空穴迁移性能的影响,以表明这种潜在的PMOS器件的潜在性能。
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引用次数: 0
期刊
2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)
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