Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004109
V. Biolková, D. Biolek, T. Dostál
In the paper, 9 rules are given on which the operation of so-called Object Analysis Hake Utility is based. The basic resource is represented by VERTEX graphs, which describe a set of nonlinear equations between the parameters of circuit elements and the coefficients of circuit functions. Some feasible techniques of transforming these graphs into simpler structures are shown. As a result, the couplings among variations of individual parameters are made obvious that hold the monitored circuit features.
{"title":"OAHU - Object Analysis Hake Utility","authors":"V. Biolková, D. Biolek, T. Dostál","doi":"10.1109/ICCDCS.2002.1004109","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004109","url":null,"abstract":"In the paper, 9 rules are given on which the operation of so-called Object Analysis Hake Utility is based. The basic resource is represented by VERTEX graphs, which describe a set of nonlinear equations between the parameters of circuit elements and the coefficients of circuit functions. Some feasible techniques of transforming these graphs into simpler structures are shown. As a result, the couplings among variations of individual parameters are made obvious that hold the monitored circuit features.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128877373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004069
M. M. De Souza, G. Cao, E. M. Sankara Narayanan, F. Youming, S. K. Manhas, J. Luo, N. Moguilnaia
In this paper, the current progress and factors limiting the performance of silicon RF Power device technologies are reviewed. Silicon VDMOSFETs have high linearity but the gain is low at frequencies in excess of 1 GHz. LDMOSFETs have higher gain and can operate up to 2.4 GHz. However, the linearity and reliability of LDMOSFETs is poor in comparison to VDMOSFETs. New architectures and evolving trends are discussed.
{"title":"Progress in silicon RF Power MOS technologies - current and future trends","authors":"M. M. De Souza, G. Cao, E. M. Sankara Narayanan, F. Youming, S. K. Manhas, J. Luo, N. Moguilnaia","doi":"10.1109/ICCDCS.2002.1004069","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004069","url":null,"abstract":"In this paper, the current progress and factors limiting the performance of silicon RF Power device technologies are reviewed. Silicon VDMOSFETs have high linearity but the gain is low at frequencies in excess of 1 GHz. LDMOSFETs have higher gain and can operate up to 2.4 GHz. However, the linearity and reliability of LDMOSFETs is poor in comparison to VDMOSFETs. New architectures and evolving trends are discussed.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004035
D. Tomaszewski, L. Lukasiak, K. Domanski, A. Jakubowski
A new non-quasi static small-signal model of partially-depleted SOI MOSFETs is presented together with parameter extraction procedure. A method to eliminate parasitic capacitances from experimental data is also shown.
{"title":"Small-signal model of partially-depleted SOI MOSFETs and its parameter extraction","authors":"D. Tomaszewski, L. Lukasiak, K. Domanski, A. Jakubowski","doi":"10.1109/ICCDCS.2002.1004035","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004035","url":null,"abstract":"A new non-quasi static small-signal model of partially-depleted SOI MOSFETs is presented together with parameter extraction procedure. A method to eliminate parasitic capacitances from experimental data is also shown.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114849254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004075
D. Harame, A. Joseph, D. Coolbaugh, G. Freeman, K. Newton, S. Parker, R. Groves, M. Erturk, K. Stein, R. Volant, C. Dickey, J. Dunn, S. Subbanna, H. Zamat, V.S. Marangos, M. Doherty, O. Schreiber, T. Tanji, D. Herman, B. Meyerson
SiGe BiCMOS technology is well suited for both wired and wireless communication areas. For the wired space, the key requirements are very high speed active devices, extremely accurate interconnect modeling (lumped elements and transmission lines), and the ability to do very highly integrated analog and mixed signal chips. With data rates at 40 Gb/s, the distinction between digital and analog circuits becomes blurred and low frequency models are no longer adequate. RF/Analog layouts and models are needed for all active devices. SiGe BiCMOS satisfies all these requirements.
{"title":"The emerging role of SiGe BiCMOS technology in wired and wireless communications","authors":"D. Harame, A. Joseph, D. Coolbaugh, G. Freeman, K. Newton, S. Parker, R. Groves, M. Erturk, K. Stein, R. Volant, C. Dickey, J. Dunn, S. Subbanna, H. Zamat, V.S. Marangos, M. Doherty, O. Schreiber, T. Tanji, D. Herman, B. Meyerson","doi":"10.1109/ICCDCS.2002.1004075","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004075","url":null,"abstract":"SiGe BiCMOS technology is well suited for both wired and wireless communication areas. For the wired space, the key requirements are very high speed active devices, extremely accurate interconnect modeling (lumped elements and transmission lines), and the ability to do very highly integrated analog and mixed signal chips. With data rates at 40 Gb/s, the distinction between digital and analog circuits becomes blurred and low frequency models are no longer adequate. RF/Analog layouts and models are needed for all active devices. SiGe BiCMOS satisfies all these requirements.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123899455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004070
V. Kumar, I. Adesida
This paper presents the recent progress in the development of fabrication processes and device performance of recessed as well as non recessed AlGaN/GaN HEMTs at the University of Illinois. Maximum drain current density as high as 1.31 A/mm, record high extrinsic transconductance of 402 mS/mm, unity gain cut-off frequency (f/sub T/) of 107 GHz, and maximum frequency of oscillation (f/sub max/) of 148 GHz were demonstrated for recessed AlGaN/GaN HEMTs with a gate length of 0.15 /spl mu/m grown by MOCVD. Results for MBE-grown devices are also presented.
{"title":"AlGaN/GaN HEMTs on sapphire","authors":"V. Kumar, I. Adesida","doi":"10.1109/ICCDCS.2002.1004070","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004070","url":null,"abstract":"This paper presents the recent progress in the development of fabrication processes and device performance of recessed as well as non recessed AlGaN/GaN HEMTs at the University of Illinois. Maximum drain current density as high as 1.31 A/mm, record high extrinsic transconductance of 402 mS/mm, unity gain cut-off frequency (f/sub T/) of 107 GHz, and maximum frequency of oscillation (f/sub max/) of 148 GHz were demonstrated for recessed AlGaN/GaN HEMTs with a gate length of 0.15 /spl mu/m grown by MOCVD. Results for MBE-grown devices are also presented.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128634687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004103
G. Brando, A. Del Pizzo, E. Faccenda
This paper deals with parallel active filtering by means of IGBT-Voltage Source Inverters. The control algorithm is based on the evaluation of active and reactive power by detecting line voltages and load currents. Then these powers are split in their average and alternative components using proper low-pass filters. The features linked to some different techniques of current control are investigated with reference to time behaviour and frequency spectrum of the resultant line current. Simulation results are discussed and compared with reference to a specific case-study.
{"title":"A comparison between some control algorithms of parallel active filtering","authors":"G. Brando, A. Del Pizzo, E. Faccenda","doi":"10.1109/ICCDCS.2002.1004103","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004103","url":null,"abstract":"This paper deals with parallel active filtering by means of IGBT-Voltage Source Inverters. The control algorithm is based on the evaluation of active and reactive power by detecting line voltages and load currents. Then these powers are split in their average and alternative components using proper low-pass filters. The features linked to some different techniques of current control are investigated with reference to time behaviour and frequency spectrum of the resultant line current. Simulation results are discussed and compared with reference to a specific case-study.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"885 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128661140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004099
Jia Luo, Xiaofang Gao, I. Batarseh
Normally, socket inductance is very small and it seldom influences the performance of chips. However, for new generation of microprocessor, the slew rate of load change is so large that the socket inductance response delay is dominant in transient response. The existing of a socket generates large voltage spike under such a load-change transient due to the current response delay of inductance. A novel active compensator is presented to minimize total voltage variation within 2.5% when microprocessor operates at 1V, 100A and 2A/ns of current slew rate with the package capacitance decreasing to less than one-half of Pentium 4 level.
{"title":"Active compensator to improve transient response delay for future generation of microprocessor","authors":"Jia Luo, Xiaofang Gao, I. Batarseh","doi":"10.1109/ICCDCS.2002.1004099","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004099","url":null,"abstract":"Normally, socket inductance is very small and it seldom influences the performance of chips. However, for new generation of microprocessor, the slew rate of load change is so large that the socket inductance response delay is dominant in transient response. The existing of a socket generates large voltage spike under such a load-change transient due to the current response delay of inductance. A novel active compensator is presented to minimize total voltage variation within 2.5% when microprocessor operates at 1V, 100A and 2A/ns of current slew rate with the package capacitance decreasing to less than one-half of Pentium 4 level.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129830640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004104
K. Shenai
In the information age, power electronic systems need to demonstrate, "nine 9's" of field reliability. The current reliability performance of most power converters is at best is in the range of "six 9's." A dramatic improvement in device robustness is needed to successfully address the emerging market demand. In this paper, we discuss a new "top-down" system-level approach to identify and correct excessive field failures in compact high-frequency computer and telecom power supplies. We outline approaches to design and manufacture robust power semiconductor switches that guarantee "built-in" field reliability.
{"title":"Power semiconductor devices: design and manufacturing for improved field reliability (invited)","authors":"K. Shenai","doi":"10.1109/ICCDCS.2002.1004104","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004104","url":null,"abstract":"In the information age, power electronic systems need to demonstrate, \"nine 9's\" of field reliability. The current reliability performance of most power converters is at best is in the range of \"six 9's.\" A dramatic improvement in device robustness is needed to successfully address the emerging market demand. In this paper, we discuss a new \"top-down\" system-level approach to identify and correct excessive field failures in compact high-frequency computer and telecom power supplies. We outline approaches to design and manufacture robust power semiconductor switches that guarantee \"built-in\" field reliability.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127943280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004080
M. Billaud, T. Zimmer, D. Geoffroy, Y. Danto, H. Effinger, W. Seifert, J. Martinez, F. Gomez
This paper presents the realisation of a remote lab on a European scale. The involved countries are France, Germany, and Spain. The architecture of the lab is described and the functionality has been tested. It concerns the instrumentation in the field of microelectronics. It has been applied to the characterisation of MOS transistors.
{"title":"Real measures, virtual instruments","authors":"M. Billaud, T. Zimmer, D. Geoffroy, Y. Danto, H. Effinger, W. Seifert, J. Martinez, F. Gomez","doi":"10.1109/ICCDCS.2002.1004080","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004080","url":null,"abstract":"This paper presents the realisation of a remote lab on a European scale. The involved countries are France, Germany, and Spain. The architecture of the lab is described and the functionality has been tested. It concerns the instrumentation in the field of microelectronics. It has been applied to the characterisation of MOS transistors.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115953595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004044
M. Pavanello, B. Iñíguez, J. Martino, D. Flandre
In this work a continuous model for analog simulation of long-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is presented. The model is based in a series association of two conventional fully-depleted (FD) SOI nMOSFETs with different characteristics, representing each part of the GC nMOSFET channel region. MEDICI numerical bidimensional simulations and experimental results are used to validate the proposed model.
本文提出了一种用于长沟道梯度沟道(GC)绝缘子上硅(SOI) nmosfet模拟仿真的连续模型。该模型基于两个具有不同特性的传统全耗尽(FD) SOI nMOSFET的一系列关联，代表GC nMOSFET通道区域的每个部分。MEDICI二维数值模拟和实验结果验证了该模型的有效性。
{"title":"A physically-based continuous analytical graded-channel SOI nMOSFET model for analog applications","authors":"M. Pavanello, B. Iñíguez, J. Martino, D. Flandre","doi":"10.1109/ICCDCS.2002.1004044","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004044","url":null,"abstract":"In this work a continuous model for analog simulation of long-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is presented. The model is based in a series association of two conventional fully-depleted (FD) SOI nMOSFETs with different characteristics, representing each part of the GC nMOSFET channel region. MEDICI numerical bidimensional simulations and experimental results are used to validate the proposed model.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122579383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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