E. A. Alias, M. Samsudin, S. Denbaars, J. Speck, S. Nakamura, N. Zainal
Purpose This study aims to focus on roughening N-face (backside) GaN substrate prior to GaN-on-GaN light-emitting diode (LED) growth as an attempt to improve the LED performance. Design/methodology/approach The N-face of GaN substrate was roughened by three different etchants; ammonium hydroxide (NH4OH), a mixture of NH4OH and H2O2 (NH4OH: H2O2) and potassium hydroxide (KOH). Hexagonal pyramids were successfully formed on the surface when the substrate was subjected to the etching in all cases. Findings Under 30 min of etching, the highest density of pyramids was obtained by NH4OH: H2O2 etching, which was 5 × 109 cm–2. The density by KOH and NH4OH etchings was 3.6 × 109 and 5 × 108 cm–2, respectively. At standard operation of current density at 20 A/cm2, the optical power and external quantum efficiency of the LED on the roughened GaN substrate by NH4OH: H2O2 were 12.3 mW and 22%, respectively, which are higher than its counterparts. Originality/value This study demonstrated NH4OH: H2O2 is a new etchant for roughening the N-face GaN substrate. The results showed that such etchant increased the density of the pyramids on the N-face GaN substrate, which subsequently resulted in higher optical power and external quantum efficiency to the LED as compared to KOH and NH4OH.
{"title":"N-face GaN substrate roughening for improved performance GaN-on-GaN LED","authors":"E. A. Alias, M. Samsudin, S. Denbaars, J. Speck, S. Nakamura, N. Zainal","doi":"10.1108/mi-02-2021-0011","DOIUrl":"https://doi.org/10.1108/mi-02-2021-0011","url":null,"abstract":"\u0000Purpose\u0000This study aims to focus on roughening N-face (backside) GaN substrate prior to GaN-on-GaN light-emitting diode (LED) growth as an attempt to improve the LED performance.\u0000\u0000\u0000Design/methodology/approach\u0000The N-face of GaN substrate was roughened by three different etchants; ammonium hydroxide (NH4OH), a mixture of NH4OH and H2O2 (NH4OH: H2O2) and potassium hydroxide (KOH). Hexagonal pyramids were successfully formed on the surface when the substrate was subjected to the etching in all cases.\u0000\u0000\u0000Findings\u0000Under 30 min of etching, the highest density of pyramids was obtained by NH4OH: H2O2 etching, which was 5 × 109 cm–2. The density by KOH and NH4OH etchings was 3.6 × 109 and 5 × 108 cm–2, respectively. At standard operation of current density at 20 A/cm2, the optical power and external quantum efficiency of the LED on the roughened GaN substrate by NH4OH: H2O2 were 12.3 mW and 22%, respectively, which are higher than its counterparts.\u0000\u0000\u0000Originality/value\u0000This study demonstrated NH4OH: H2O2 is a new etchant for roughening the N-face GaN substrate. The results showed that such etchant increased the density of the pyramids on the N-face GaN substrate, which subsequently resulted in higher optical power and external quantum efficiency to the LED as compared to KOH and NH4OH.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41369512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Azman, N. Nayan, M. M. Megat Hasnan, N. Othman, A. S. Bakri, A. S. Abu Bakar, M. H. Mamat, M. Z. Mohd Yusop
PurposeThis study aims to investigate the effect of temperature applied at the initial deposition of Aluminium Nitride (AlN) thin-film on a silicon substrate by high-power impulse magnetron sputtering (HiPIMS) technique. Design/methodology/approachHiPIMS system was used to deposit AlN thin film at a low output power of 200 W. The ramping temperature was introduced to substrate from room temperature to maximum 100°Cat the initial deposition of thin-film, and the result was compared to thin-film sputtered with no additional heat. For the heat assistance AlN deposition, the substrate was let to cool down to room temperature for the remaining deposition time. The thin-films were characterized by X-ray diffraction (XRD) and atomic force microscope (AFM) while the MIS Schottky diode characteristic investigated through current-voltage response by a two-point probe method. FindingsThe XRD pattern shows significant improvement of the strong peak of the c-axis (002) preferred orientation of the AlN thin-film. The peak was observed narrowed with temperature assisted where FWHM calculated at 0.35° compared to FWHM of AlN thin film deposited at room temperature at around 0.59°. The degree of crystallinity of bulk thin film was improved by 28% with temperature assisted. The AFM images show significant improvement as low surface roughness achieved at around 0.7 nm for temperature assisted sample compares to 3 nm with no heat applied. Originality/valueThe small amount of heat introduced to the substrate has significantly improved the growth of the c-axis AlN thin film, and this method is favorable in the deposition of the high-quality thin film at the low-temperature process.
{"title":"Improvement of c-axis (002) AlN crystal plane by temperature assisted HiPIMS technique","authors":"Z. Azman, N. Nayan, M. M. Megat Hasnan, N. Othman, A. S. Bakri, A. S. Abu Bakar, M. H. Mamat, M. Z. Mohd Yusop","doi":"10.1108/mi-02-2021-0013","DOIUrl":"https://doi.org/10.1108/mi-02-2021-0013","url":null,"abstract":"\u0000PurposeThis study aims to investigate the effect of temperature applied at the initial deposition of Aluminium Nitride (AlN) thin-film on a silicon substrate by high-power impulse magnetron sputtering (HiPIMS) technique.\u0000\u0000\u0000Design/methodology/approachHiPIMS system was used to deposit AlN thin film at a low output power of 200 W. The ramping temperature was introduced to substrate from room temperature to maximum 100°Cat the initial deposition of thin-film, and the result was compared to thin-film sputtered with no additional heat. For the heat assistance AlN deposition, the substrate was let to cool down to room temperature for the remaining deposition time. The thin-films were characterized by X-ray diffraction (XRD) and atomic force microscope (AFM) while the MIS Schottky diode characteristic investigated through current-voltage response by a two-point probe method.\u0000\u0000\u0000FindingsThe XRD pattern shows significant improvement of the strong peak of the c-axis (002) preferred orientation of the AlN thin-film. The peak was observed narrowed with temperature assisted where FWHM calculated at 0.35° compared to FWHM of AlN thin film deposited at room temperature at around 0.59°. The degree of crystallinity of bulk thin film was improved by 28% with temperature assisted. The AFM images show significant improvement as low surface roughness achieved at around 0.7 nm for temperature assisted sample compares to 3 nm with no heat applied.\u0000\u0000\u0000Originality/valueThe small amount of heat introduced to the substrate has significantly improved the growth of the c-axis AlN thin film, and this method is favorable in the deposition of the high-quality thin film at the low-temperature process.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49493928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Muhammad Ahmad Raza Tahir, M. M. Saleem, Syed Ali Asadullah Bukhari, Amir Hamza, R. I. Shakoor
PurposeThis paper aims to present an efficient design approach for the micro electromechanical systems (MEMS) accelerometers considering design parameters affecting the long-term reliability of these inertial sensors in comparison to traditional iterative microfabrication and experimental characterization approach. Design/methodology/approachA dual-axis capacitive MEMS accelerometer design is presented considering the microfabrication process constraints of the foundry process. The performance of the MEMS accelerometer is analyzed through finite element method– based simulations considering main design parameters affecting the long-term reliability. The effect of microfabrication process induced residual stress, operating pressure variations in the range of 10 mTorr to atmospheric pressure, thermal variations in the operating temperature range of −40°C to 100°C and impulsive input acceleration at different input frequency values is presented in detail. FindingsThe effect of residual stress is negligible on performance of the MEMS accelerometer due to efficient design of mechanical suspension beams. The effect of operating temperature and pressure variations is negligible on energy loss factor. The thermal strain at high temperature causes the sensing plates to deform out of plane. The input dynamic acceleration range is 34 g at room temperature, which decreases with operating temperature variations. At low frequency input acceleration, the input acts as a quasi-static load, whereas at high frequency, it acts as a dynamic load for the MEMS accelerometer. Originality/valueIn comparison with the traditional MEMS accelerometer design approaches, the proposed design approach focuses on the analysis of critical design parameters that affect the long-term reliability of MEMS accelerometer.
{"title":"An efficient design of dual-axis MEMS accelerometer considering microfabrication process limitations and operating environment variations","authors":"Muhammad Ahmad Raza Tahir, M. M. Saleem, Syed Ali Asadullah Bukhari, Amir Hamza, R. I. Shakoor","doi":"10.1108/mi-02-2021-0023","DOIUrl":"https://doi.org/10.1108/mi-02-2021-0023","url":null,"abstract":"\u0000PurposeThis paper aims to present an efficient design approach for the micro electromechanical systems (MEMS) accelerometers considering design parameters affecting the long-term reliability of these inertial sensors in comparison to traditional iterative microfabrication and experimental characterization approach.\u0000\u0000\u0000Design/methodology/approachA dual-axis capacitive MEMS accelerometer design is presented considering the microfabrication process constraints of the foundry process. The performance of the MEMS accelerometer is analyzed through finite element method– based simulations considering main design parameters affecting the long-term reliability. The effect of microfabrication process induced residual stress, operating pressure variations in the range of 10 mTorr to atmospheric pressure, thermal variations in the operating temperature range of −40°C to 100°C and impulsive input acceleration at different input frequency values is presented in detail.\u0000\u0000\u0000FindingsThe effect of residual stress is negligible on performance of the MEMS accelerometer due to efficient design of mechanical suspension beams. The effect of operating temperature and pressure variations is negligible on energy loss factor. The thermal strain at high temperature causes the sensing plates to deform out of plane. The input dynamic acceleration range is 34 g at room temperature, which decreases with operating temperature variations. At low frequency input acceleration, the input acts as a quasi-static load, whereas at high frequency, it acts as a dynamic load for the MEMS accelerometer.\u0000\u0000\u0000Originality/valueIn comparison with the traditional MEMS accelerometer design approaches, the proposed design approach focuses on the analysis of critical design parameters that affect the long-term reliability of MEMS accelerometer.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47404804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA. Design/methodology/approach As the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator. Findings Four elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects. Originality/value A novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.
{"title":"A fault-tolerant design for a digital comparator based on nano-scale quantum-dotcellular automata","authors":"Wenhua Huang, Juan Ren, Jinglong Jiang, J. Cheng","doi":"10.1108/mi-01-2021-0006","DOIUrl":"https://doi.org/10.1108/mi-01-2021-0006","url":null,"abstract":"\u0000Purpose\u0000Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA.\u0000\u0000\u0000Design/methodology/approach\u0000As the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator.\u0000\u0000\u0000Findings\u0000Four elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects.\u0000\u0000\u0000Originality/value\u0000A novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47336506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Premmilaah Gunasegaran, J. Rajendran, S. Mariappan, Y. Yusof, Z. Aziz, Narendra Kumar
Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.
{"title":"A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3","authors":"Premmilaah Gunasegaran, J. Rajendran, S. Mariappan, Y. Yusof, Z. Aziz, Narendra Kumar","doi":"10.1108/mi-01-2021-0008","DOIUrl":"https://doi.org/10.1108/mi-01-2021-0008","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).\u0000\u0000\u0000Design/methodology/approach\u0000The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.\u0000\u0000\u0000Findings\u0000With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.\u0000\u0000\u0000Practical implications\u0000The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.\u0000\u0000\u0000Originality/value\u0000The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47593964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this study is to present a systematic investigation of the effect of high temperatures on transport characteristics of nitrogen-doped silicon carbide nanowire-based field-effect transistor (SiC-NWFET). The 3C-SiC nanowires can endure high-temperature environments due to their wide bandgap, high thermal conductivity and outstanding physical and chemical properties. Design/methodology/approach The metal-organic chemical vapor deposition process was used to synthesize in-situ nitrogen-doped SiC nanowires on SiO2/Si substrate. To fabricate the proposed SiC-NWFET device, the dielectrophoresis method was used to integrate the grown nanowires on the surface of pre-patterned electrodes onto the SiO2 layer on a highly doped Si substrate. The transport properties of the fabricated device were evaluated at various temperatures ranging from 25°C to 350°C. Findings The SiC-NWFET device demonstrated an increase in conductance (from 0.43 mS to 1.2 mS) after applying a temperature of 150°C, and then a decrease in conductance (from 1.2 mS to 0.3 mS) with increasing the temperature to 350°C. The increase in conductance can be attributed to the thermionic emission and tunneling mechanisms, while the decrease can be attributed to the phonon scattering. Additionally, the device revealed high electron and hole mobilities, as well as very low resistivity values at both room temperature and high temperatures. Originality/value High-temperature transport properties (above 300°C) of 3C-SiC nanowires have not been reported yet. The SiC-NWFET demonstrates a high transconductance, high electron and hole mobilities, very low resistivity, as well as good stability at high temperatures. Therefore, this study could offer solutions not only for high-power but also for low-power circuit and sensing applications in high-temperature environments (∼350°C).
{"title":"High-transconductance silicon carbide nanowire-based field-effect transistor (SiC-NWFET) for high-temperature applications","authors":"Habeeb Mousa, K. Teker","doi":"10.1108/mi-05-2021-0043","DOIUrl":"https://doi.org/10.1108/mi-05-2021-0043","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to present a systematic investigation of the effect of high temperatures on transport characteristics of nitrogen-doped silicon carbide nanowire-based field-effect transistor (SiC-NWFET). The 3C-SiC nanowires can endure high-temperature environments due to their wide bandgap, high thermal conductivity and outstanding physical and chemical properties.\u0000\u0000\u0000Design/methodology/approach\u0000The metal-organic chemical vapor deposition process was used to synthesize in-situ nitrogen-doped SiC nanowires on SiO2/Si substrate. To fabricate the proposed SiC-NWFET device, the dielectrophoresis method was used to integrate the grown nanowires on the surface of pre-patterned electrodes onto the SiO2 layer on a highly doped Si substrate. The transport properties of the fabricated device were evaluated at various temperatures ranging from 25°C to 350°C.\u0000\u0000\u0000Findings\u0000The SiC-NWFET device demonstrated an increase in conductance (from 0.43 mS to 1.2 mS) after applying a temperature of 150°C, and then a decrease in conductance (from 1.2 mS to 0.3 mS) with increasing the temperature to 350°C. The increase in conductance can be attributed to the thermionic emission and tunneling mechanisms, while the decrease can be attributed to the phonon scattering. Additionally, the device revealed high electron and hole mobilities, as well as very low resistivity values at both room temperature and high temperatures.\u0000\u0000\u0000Originality/value\u0000High-temperature transport properties (above 300°C) of 3C-SiC nanowires have not been reported yet. The SiC-NWFET demonstrates a high transconductance, high electron and hole mobilities, very low resistivity, as well as good stability at high temperatures. Therefore, this study could offer solutions not only for high-power but also for low-power circuit and sensing applications in high-temperature environments (∼350°C).\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41474950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Hamzah, M. A. Ahmad, R. Asri, E. A. Alias, M. Sahar, N. S. Shiong, Z. Hassan
Purpose The purpose of this paper is to enhance the efficiency of the LED by introducing three-step magnesium (Mg) doping profile. Attention was paid to the effects of the Mg doping concentration of the first p-GaN layer (i.e. layer close to the active region). Attention was paid to the effects of the Mg doping concentration of the first p-GaN layer (i.e. layer close to the active region). Design/methodology/approach Indium gallium nitride (InGaN)–based light-emitting diode (LED) was grown on a 4-inch c-plane patterned sapphire substrate using metal organic chemical vapor deposition. The Cp2Mg flow rates for the second and third p-GaN layers were set at 50 sccm and 325 sccm, respectively. For the first p-GaN layer, the Cp2Mg flow rate varied from 150 sccm to 300 sccm to achieve different Mg dopant concentrations. Findings The full width at half maximum (FWHM) for the GaN (102) plane increases with increasing Cp2Mg flow rate. FWHM for the sample with 150, 250 and 300 sccm Cp2Mg flow rates was 233 arcsec, 236 arcsec and 245 arcsec, respectively. This result indicates that the edge and mixed dislocations in the p-GaN layer were increased with increasing Cp2Mg flow rate. Atomic force microscopy (AFM) results reveal that the sample grown with 300 sccm exhibits the highest surface roughness, followed by 150 sccm and 250 sccm. The surface roughness of these samples is 2.40 nm, 2.12 nm and 2.08 nm, respectively. Simultaneously, the photoluminescence (PL) spectrum of the 250 sccm sample shows the highest band edge intensity over the yellow band ratio compared to that of other samples. The light output power measurements found that the sample with 250 sccm exhibits high output power because of sufficient hole injection toward the active region. Originality/value Through this study, the three steps of the Mg profile on the p-GaN layer were proposed to show high-efficiency InGaN-based LED. The optimal Mg concentration was studied on the first p-GaN layer (i.e. layer close to active region) to improve the LED performance by varying the Cp2Mg flow rate. This finding was in line with the result of PL and AFM results when the samples with 250 sccm have the highest Mg acceptor and good surface quality of the p-GaN layer. It can be deduced that the first p-GaN layer doping has a significant effect on the crystalline quality, surface roughness and light emission properties of the LED epi structure.
{"title":"Effects of three-step magnesium doping in p-GaN layer on the properties of InGaN-based light-emitting diode","authors":"N. Hamzah, M. A. Ahmad, R. Asri, E. A. Alias, M. Sahar, N. S. Shiong, Z. Hassan","doi":"10.1108/mi-02-2021-0016","DOIUrl":"https://doi.org/10.1108/mi-02-2021-0016","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to enhance the efficiency of the LED by introducing three-step magnesium (Mg) doping profile. Attention was paid to the effects of the Mg doping concentration of the first p-GaN layer (i.e. layer close to the active region). Attention was paid to the effects of the Mg doping concentration of the first p-GaN layer (i.e. layer close to the active region).\u0000\u0000\u0000Design/methodology/approach\u0000Indium gallium nitride (InGaN)–based light-emitting diode (LED) was grown on a 4-inch c-plane patterned sapphire substrate using metal organic chemical vapor deposition. The Cp2Mg flow rates for the second and third p-GaN layers were set at 50 sccm and 325 sccm, respectively. For the first p-GaN layer, the Cp2Mg flow rate varied from 150 sccm to 300 sccm to achieve different Mg dopant concentrations.\u0000\u0000\u0000Findings\u0000The full width at half maximum (FWHM) for the GaN (102) plane increases with increasing Cp2Mg flow rate. FWHM for the sample with 150, 250 and 300 sccm Cp2Mg flow rates was 233 arcsec, 236 arcsec and 245 arcsec, respectively. This result indicates that the edge and mixed dislocations in the p-GaN layer were increased with increasing Cp2Mg flow rate. Atomic force microscopy (AFM) results reveal that the sample grown with 300 sccm exhibits the highest surface roughness, followed by 150 sccm and 250 sccm. The surface roughness of these samples is 2.40 nm, 2.12 nm and 2.08 nm, respectively. Simultaneously, the photoluminescence (PL) spectrum of the 250 sccm sample shows the highest band edge intensity over the yellow band ratio compared to that of other samples. The light output power measurements found that the sample with 250 sccm exhibits high output power because of sufficient hole injection toward the active region.\u0000\u0000\u0000Originality/value\u0000Through this study, the three steps of the Mg profile on the p-GaN layer were proposed to show high-efficiency InGaN-based LED. The optimal Mg concentration was studied on the first p-GaN layer (i.e. layer close to active region) to improve the LED performance by varying the Cp2Mg flow rate. This finding was in line with the result of PL and AFM results when the samples with 250 sccm have the highest Mg acceptor and good surface quality of the p-GaN layer. It can be deduced that the first p-GaN layer doping has a significant effect on the crystalline quality, surface roughness and light emission properties of the LED epi structure.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42777174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Sahar, Z. Hassan, S. Ng, W. F. Lim, K. S. Lau, E. A. Alias, M. A. Ahmad, N. Hamzah, R. Asri
Purpose The aims of this paper is to study the effects of the V/III ratio of indium gallium nitride (InGaN) quantum wells (QWs) on the structural, optical and electrical properties of near-ultraviolet light-emitting diode (NUV-LED). Design/methodology/approach InGaN-based NUV-LED is successfully grown on the c-plane patterned sapphire substrate at atmospheric pressure using metal organic chemical vapor deposition. Findings The indium composition and thickness of InGaN QWs increased as the V/III ratio increased from 20871 to 11824, according to high-resolution X-ray diffraction. The V/III ratio was also found to have an important effect on the surface morphology of the InGaN QWs and thus the surface morphology of the subsequent layers. Apart from that, the electroluminescence measurement revealed that the V/III ratio had a major impact on the light output power (LOP) and the emission peak wavelength of the NUV-LED. The LOP increased by up to 53% at 100 mA, and the emission peak wavelength of the NUV-LED changed to a longer wavelength as the V/III ratio decreased from 20871 to 11824. Originality/value This study discovered a relation between the V/III ratio and the properties of QWs, which resulted in the LOP enhancement of the NUV-LED. High TMIn flow rates, which produced a low V/III ratio, contribute to the increased LOP of NUV-LED.
{"title":"Effects of V/III ratio of InGaN quantum well at high growth temperature for near ultraviolet light emitting diodes","authors":"M. Sahar, Z. Hassan, S. Ng, W. F. Lim, K. S. Lau, E. A. Alias, M. A. Ahmad, N. Hamzah, R. Asri","doi":"10.1108/MI-02-2021-0017","DOIUrl":"https://doi.org/10.1108/MI-02-2021-0017","url":null,"abstract":"\u0000Purpose\u0000The aims of this paper is to study the effects of the V/III ratio of indium gallium nitride (InGaN) quantum wells (QWs) on the structural, optical and electrical properties of near-ultraviolet light-emitting diode (NUV-LED).\u0000\u0000\u0000Design/methodology/approach\u0000InGaN-based NUV-LED is successfully grown on the c-plane patterned sapphire substrate at atmospheric pressure using metal organic chemical vapor deposition.\u0000\u0000\u0000Findings\u0000The indium composition and thickness of InGaN QWs increased as the V/III ratio increased from 20871 to 11824, according to high-resolution X-ray diffraction. The V/III ratio was also found to have an important effect on the surface morphology of the InGaN QWs and thus the surface morphology of the subsequent layers. Apart from that, the electroluminescence measurement revealed that the V/III ratio had a major impact on the light output power (LOP) and the emission peak wavelength of the NUV-LED. The LOP increased by up to 53% at 100 mA, and the emission peak wavelength of the NUV-LED changed to a longer wavelength as the V/III ratio decreased from 20871 to 11824.\u0000\u0000\u0000Originality/value\u0000This study discovered a relation between the V/III ratio and the properties of QWs, which resulted in the LOP enhancement of the NUV-LED. High TMIn flow rates, which produced a low V/III ratio, contribute to the increased LOP of NUV-LED.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48235746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Si-based micro electro mechanical systems (MEMS) magnetometer does not require specialized magnetic materials avoiding magnetic hysteresis, ease in fabrication and low power consumption. It can be fabricated using the same processes used for gyroscope and accelerometer fabrication. The paper reports the dicing mechanism for the released MEMS xylophone magnetic sensor fabricated using wafer bonding technology and its characterization in ambient pressure and under vacuum conditions. The purpose of this paper is to dice the wafer bonded Si-magnetometer in a cost-effective way without the use of laser dicing and test it for Lorentz force transduction. Design/methodology/approach A xylophone bar MEMS magnetometer using Lorentz force transduction is developed. The fabricated MEMS-based xylophone bars in literature are approximately 500 µm. The present work shows the released structure (L = 592 µm) fabricated by anodic bonding technique using conducting Si as the structural layer and tested for Lorentz force transduction. The microstructures fabricated at the wafer level are released. Dicing these released structures using conventional diamond blade dicing may damage the structures and reduce the yield. To avoid the problem, positive photoresist S1813 was filled before dicing. The dicing of the wafer, filled with photoresist and later removal of photoresist post dicing, is proposed. Findings The devices realized are stiction free and straight. The dynamic measurements are done using laser Doppler vibrometer to verify the released structure and test its functionality for Lorentz force transduction. The magnetic field is applied using a permanent magnet and Helmholtz coil. Two sensors with quality factors 70 and 238 are tested with resonant frequency 112.38 kHz and 114.38 kHz, respectively. The sensor D2, with Q as 238, shows a mechanical sensitivity of 500 pm/Gauss and theoretical Brownian noise-limited resolution of 53 nT/vHz. Originality/value The methodology and the study will help develop Lorentz force–based MEMS magnetometers such that stiction-free structures are released using wet etch after the mechanical dicing.
{"title":"Development and post-dicing wet release of MEMS magnetometer: an approach","authors":"Aditi, S. Das, R. Gopal","doi":"10.1108/MI-12-2020-0081","DOIUrl":"https://doi.org/10.1108/MI-12-2020-0081","url":null,"abstract":"\u0000Purpose\u0000Si-based micro electro mechanical systems (MEMS) magnetometer does not require specialized magnetic materials avoiding magnetic hysteresis, ease in fabrication and low power consumption. It can be fabricated using the same processes used for gyroscope and accelerometer fabrication. The paper reports the dicing mechanism for the released MEMS xylophone magnetic sensor fabricated using wafer bonding technology and its characterization in ambient pressure and under vacuum conditions. The purpose of this paper is to dice the wafer bonded Si-magnetometer in a cost-effective way without the use of laser dicing and test it for Lorentz force transduction.\u0000\u0000\u0000Design/methodology/approach\u0000A xylophone bar MEMS magnetometer using Lorentz force transduction is developed. The fabricated MEMS-based xylophone bars in literature are approximately 500 µm. The present work shows the released structure (L = 592 µm) fabricated by anodic bonding technique using conducting Si as the structural layer and tested for Lorentz force transduction. The microstructures fabricated at the wafer level are released. Dicing these released structures using conventional diamond blade dicing may damage the structures and reduce the yield. To avoid the problem, positive photoresist S1813 was filled before dicing. The dicing of the wafer, filled with photoresist and later removal of photoresist post dicing, is proposed.\u0000\u0000\u0000Findings\u0000The devices realized are stiction free and straight. The dynamic measurements are done using laser Doppler vibrometer to verify the released structure and test its functionality for Lorentz force transduction. The magnetic field is applied using a permanent magnet and Helmholtz coil. Two sensors with quality factors 70 and 238 are tested with resonant frequency 112.38 kHz and 114.38 kHz, respectively. The sensor D2, with Q as 238, shows a mechanical sensitivity of 500 pm/Gauss and theoretical Brownian noise-limited resolution of 53 nT/vHz.\u0000\u0000\u0000Originality/value\u0000The methodology and the study will help develop Lorentz force–based MEMS magnetometers such that stiction-free structures are released using wet etch after the mechanical dicing.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2021-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44079585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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