Microelectronics Reliability最新文献

Wire bonding is a fundamental and mature technology in semiconductor packaging process, primarily using materials such as gold, silver, aluminum, and copper for the wires. To address application limitations of aluminum wires, such as low electromigration resistance and limited ductility, techniques including to enhance alloying (with Zn and Si), heat treatment, and surface treatment are employed to enhance the performance of aluminum alloy wires and broaden their application value. This study selects Al-3Zn-0.3Si (AZS303) and Al-7Zn-0.3Si (AZS703), with AZS303 undergoing gold plating to produce AC-AZS303 wires. Various high-temperature heat treatments are applied, verifying that under 400 °C conditions, the AZS series aluminum alloy wires exhibit grain growth and form single-crystal equiaxed grain structures, resulting in stable mechanical properties and excellent electrical performance. Additionally, the AC-AZS303 wires optimize resistance values through gold layer diffusion induced by the electrothermal effect.

Chlorine experiments indicates that the gold plating on AC-AZS303 can't enhance the aluminum wire's resistance to chlorine corrosion. However, the alloying effect of zine and silicon elements imparts excellent chlorine corrosion resistance to the Al-Zn-Si wires. This study of bonding properties examines the bond strength and observes the bonded area of Al-Zn-Si wires after bonding. It is noted that the H400-AZS303 wire exhibits the best bond strength and bonding area, demonstrating good bonding with the substrate.

The aerospace environment contains extremely energetic particles that trigger single-event transients (SET), leading to single-event upsets (SEU) in the memory cell. An efficient SRAM cell must be designed to tolerate soft error to withstand the extreme environment. This paper proposes a highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. The proposed cell has better writability, and WSNM is 1.08$\times$ higher than its counterpart We-Quatro SRAM cell. The read access time of the proposed SRAM cell is 0.96$\times$, 0.91$\times$, 0.99$\times$, 0.98$\times$ smaller than 6T, Quatro, We-Quatro, and NQuatro SRAM cells, and 1.01$\times$ higher than RHD12T cell, and the write delay of the proposed SRAM is 0.93$\times$, 0.46$\times$, 0.72$\times$, 0.41$\times$, 0.47$\times$, less than that of 6T, Quatro, We-Quatro, RHD12T, and NQuatro respectively. 2000 Monte Carlo simulation for power dissipation and upset margin reveals that the process variation has less impact on the proposed SRAM and 1.64$\times$ better tolerance against logic flipping. Further, for the P-Quatro, the critical charge is 41.51 fC and is 2.05$\times$, 1.75$\times$, 1.93$\times$, and 1.48$\times$ greater than Quatro, We-Quatro, RHD12T, and NQuatro memory cells. We conducted an assessment using an electrical quality matrix (EQM) that takes into account all performance parameters. The findings reveal that the EQM of the proposed cell surpasses that of the 6T, Quatro, We-Quatro, RHD12T, and NQuatro SRAM cells by factors of 0.82$\times$, 0.35$\times$, 0.49$\times$, 0.71$\times$, and 0.21$\times$, respectively. This indicates that the proposed cell demonstrates superior electrical quality across various metrics compared to the other SRAM cell designs evaluated.

The study of chip-level and package-level heat transfer in a GaN high electron mobility transistor (HEMT) is often disconnected due to limited resources and tools. In this work, device simulation from Silvaco Victory Device is carried forward to the chip-to-package-level simulation using Icepak to provide a complete picture of the proposed thermal management strategies using polycrystalline diamond (PCD) heat spreaders. The max junction temperature, T_j = 105.8 °C and the relative magnitude of max temperature on the GaN surface, ΔT_j = 18 % are recorded for the original Si-GaN-Si₃N₄ chip inside TO-220 at 6.0 Wmm⁻¹. Replacing the Si₃N₄ with PCD (thermal conductivity of 500 Wm⁻¹ K⁻¹) results in T_j = 98.2 °C and ΔT_j = 8 %, while replacing the Si results in T_j = 97.0 °C and ΔT_j = 11 %. The top layer PCD spreads the heat from hotspot regions to the surrounding epoxy, while the bottom layer PCD improves the heat path from the hotspots to the base plate. Therefore, the reduction in T_j by the bottom layer PCD is more important than the reduction in ΔT_j by the top layer PCD. Implementing both the top and bottom layers of PCD results in the best offers of T_j = 92.9 °C and ΔT_j = 6 %. The performance of PCD as heat spreaders in multi-finger gate GaN HEMT suggested by these chip-to-package-level simulations are more reliable than device simulation alone since they cover the complete heat path from generation, conduction within the package, and convection to the ambient air.

Considering the reliability of the bond wire comes as the main factor determining the reliability of power devices at present, and the geometric parameters of the bond wire have an in-negligible effect. A Finite Element (FE) simulation model based on a discrete device with TO-247 package and a single bond wire is established in this paper, and the influences of the geometric parameters are analyzed, which include the joint length L, the diameter D, and the aspect ratio λ. Then to understand the influence degree of the parameter on the reliability, the sensitivity analysis of these geometric parameters is carried out based on the sobol' method, using the Monte Carlo method for estimating the sensitivity index. The results show that increasing the joint length L, the diameter D and the aspect ratio λ all have a negative impact on the bond wire reliability, while a positive influence is presented by increasing the aspect ratio λ in the case without epoxy mold compound (EMC). This is because of the EMC's protective effect which inhibits the bond wire's thermal expansion. The aspect ratio λ is the most sensitive parameter of the three geometric parameters since it has the largest total sensitive index.

This work analyzes the mechanical and electrical properties of molybdenum (Mo) thin films at 100 and 200 nm thicknesses under different strain and strain rate circumstances. The study examines Mo film deposition by RF magnetron sputtering on PET substrates and their mechanical stress behavior. The investigation reveals distinct patterns of crack initiation and propagation, where primary cracks predominantly appear perpendicular to the direction of applied strain, and secondary cracks develop due to stress redistribution, displaying a complex interplay between film thickness, strain rate, and crack morphology. A key finding of this study is the observation of more advanced and irregular crack patterns in thicker films (200 nm) subjected to higher strain rates (1000 mm/min), suggesting a heightened sensitivity to mechanical stress and a more chaotic fracture process compared to thinner films or those under lower strain rates. Additionally, instances of film edge delamination, particularly under high strain conditions, highlight the challenges in maintaining film-substrate adhesion and integrity under extreme mechanical deformation. The research provides critical insights into the mechanical robustness and electrical performance of Mo thin films, emphasizing the influence of microstructural properties, deposition parameters, and external stressors on their applicability in high-tech industries. The findings underscore the importance of optimizing deposition techniques and understanding material behavior under stress to enhance the durability and reliability of Mo thin films in practical applications, ranging from semiconductor devices to photovoltaic systems.

Power semiconductor modules, such as IGBT and power MOSFET modules, have been increasingly used due to the growing application market, such as electric vehicles and renewable energy. A long lifetime of power semiconductor modules is strongly required, and the power cycle test is an important evaluation. Cracks in the mount solder of power semiconductor package are one of the main factors affecting the power cycle lifetime due to the increase in thermal resistance. Variations in the mounting process during the package assembly may lead to solder voids in the initial state, causing stress within the solder joint and influencing the power cycle lifetime. This paper reports the effect of the void ratio of chip mount solder on power cycle lifetime. Samples with intentionally varied initial void ratios and void positions were fabricated, and their power cycle lifetimes were evaluated. The results show that the power cycle lifetime is determined by the Coffin-Manson law, even with different void ratios and positions.

Nanowire Field Effect Transistors (NWFETs) have been considered as the next-generation technology for sub-10 nm technology nodes, succeeding FinFETs. However, the highly confined nature of Nanowire FETs creates reliability issues that significantly impact their performance. Therefore, this work proposes a machine learning-based technique for analyzing the self-heating-induced reliability issues in NWFETs. The influence of self-heating effects in NWFET has been predicted in terms of saturation current (I_dsat), threshold voltage (V_th), the maximum carrier temperature along the channel (eTmax), and the maximum Lattice temperature (LTmax) with multivariable regression. TCAD-assisted machine learning has been used for algorithm training and prediction. A dataset has been created by varying the parameters of the NWFETs like the thickness of the channel (t_si), the thickness of oxide (t_ox), Length of source/drain (L_sd), length of source/drain contact (L_sdc), doping concentrations etc. The Random Forest Regression algorithm has been used to estimate the performance of NWFETs in predicting the desired output parameters suitably with the given dataset.

To exploit the potential of wide-bandgap semiconductors in high-frequency applications, innovative packaging designs are developed to minimize the parasitic inductance of power modules. This study presents an integrated power module with a hybrid PCB/DBC structure, which uses top-side cooling prepackaged GaN enhancement-mode high-electron-mobility transistors. The module achieves a remarkably low parasitic inductance of 2.65 nH. However, there is relatively scarce research on the reliability of this heterostructure, particularly its sensitivity to thermomechanical stress due to the coefficients of thermal expansion mismatch among material interfaces. In this work, the thermal cycling characteristics of the integrated power module are comprehensively investigated. Electrical and thermal parameters were periodically and separately measured offline on a simplified package to monitor the health conditions and decouple possible synergy and competition effects among the failure modes from all packaging components. A thorough failure analysis was conducted using nondestructive visual inspections and scanning acoustic microscopy, complemented by destructive cross-sectional examination and scanning electron microscopy. The findings identified the delamination of the DBC upper copper layer, which exhibited a conchoidal fracture interface, as the primary factor that contributed to the failure of the power module with increased thermal resistance. Furthermore, the study dissected its initiation and propagation mechanisms. This investigation provides valuable insights for the development of more reliable low-inductance power module designs.

Current fatigue models for predicting the cycles to failure (fatigue life) of solder joints under thermo-mechanical loadings can only provide point estimates of the characteristic life or median life. Nevertheless, the prediction of fatigue life should be distributed with the uncertainties. Unfortunately, previous work has not discussed the uncertainty of the cycles to failure, especially for the solder joints under temperature cycling. Therefore, the uncertainty propagation of the cycles to failure is necessary to better estimate the distribution of the fatigue life of solder joint. This paper presents a four-part uncertainty propagation approach for this problem. Part I models the solder joint using finite element analysis. Part II uses the eigenvector dimension reduction method and finite element analysis simulation tool to determine the distribution of the system response, which is the strain energy density accumulation. Part III uses a fatigue model to convert the distribution of strain energy density accumulation into a distribution of characteristic life (in cycles) by choosing the appropriate fatigue model. Part IV determines the cumulative distribution functions of the fatigue life of solder joint. We applied this method to a specific example of a solder joint for a ball grid array component to illustrate the procedure. This paper contributes to the field of durability prediction by proposing a novel uncertainty propagation method to estimate the uncertainty in the fatigue life of solder joints. Using this method can help engineers make solder material selection decisions and understand the factors that contribute most to solder joint fatigue life uncertainty.

Advances in integrated circuit production technologies have reduced device sizes, leading to corresponding scaling in electrical characteristics, such as threshold voltage. This scaling has increased the susceptibility of devices to electromagnetic radiation, raising the bitflip probability. Systems requiring a certain level of fault tolerance employ techniques like Error Correction Codes (ECC), providing a degree of reliability in mitigating this issue. The error correction and detection efficacies and ECC scalability vary based on the encoding and codestruct employed. This study employs four Hamming and parity code organizations for performing four Two-Dimensional (2D)-ECCs (N × 4p, N × ExHam, N × Ham_p, and N × Ham2_2p). We investigated the scalability, synthesis results, and correction and detection rates employing the same number of check and data bits for the four 2D-ECCs. The results point to the advantages for ECCs that employ cross-checking using radiation-hardened memories for checkbits, especially when ECCs scale to large codestructs.