Pub Date : 2025-10-16DOI: 10.1016/j.microrel.2025.115935
I. Benjamin , S.R. Sriram , B. Bindu
The GaN high electron mobility transistor (HEMT) is a promising device for high speed and high power applications. The GaN material can withstand high voltages, high temperature and renders enhanced device performance in high operating frequency. However, there are several concerns that hinder the commercialization of GaN based transistors suitable for high speed and high power applications. The high-density defect formation and charge trapping in the surface and bulk degrade the dynamic performance of the device. This leads to various detrimental issues such as drain current collapse, increased dynamic ON-resistance, gate leakage current, low threshold voltage, low gate voltage swing, early breakdown, hot carrier effects and bias temperature instability. In this paper, the overview of various GaN structures, reliability and radiation effects and the solutions to suppress the defect formations and charge trapping effects along with improvised GaN structures are reviewed.
{"title":"A review of dynamic effects, reliability and mitigation techniques of AlGaN/GaN HEMTs","authors":"I. Benjamin , S.R. Sriram , B. Bindu","doi":"10.1016/j.microrel.2025.115935","DOIUrl":"10.1016/j.microrel.2025.115935","url":null,"abstract":"<div><div>The GaN high electron mobility transistor (HEMT) is a promising device for high speed and high power applications. The GaN material can withstand high voltages, high temperature and renders enhanced device performance in high operating frequency. However, there are several concerns that hinder the commercialization of GaN based transistors suitable for high speed and high power applications. The high-density defect formation and charge trapping in the surface and bulk degrade the dynamic performance of the device. This leads to various detrimental issues such as drain current collapse, increased dynamic ON-resistance, gate leakage current, low threshold voltage, low gate voltage swing, early breakdown, hot carrier effects and bias temperature instability. In this paper, the overview of various GaN structures, reliability and radiation effects and the solutions to suppress the defect formations and charge trapping effects along with improvised GaN structures are reviewed.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115935"},"PeriodicalIF":1.9,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-16DOI: 10.1016/j.microrel.2025.115933
Jae-Ho Shin , Keun-Soo Kim , Sang-Wook Kim , Jae-Won Kim , Min-Su Kim , Soong-Keun Hyun
Lotus-type porous Cu (LPC) is a metallic material characterized by its cylindrical pore structure, which exhibits excellent thermal conductivity, fluid permeability, ductility, and impact energy absorption capabilities. To evaluate the applicability of LPC as electronic materials, LPC/dissimilar materials joints were fabricated using SAC305 solder. To consider the pore structure in LPC, the solder filling ratio was focused as key variables in this work. The microstructure, mechanical behaviors and thermal shock behavior of LPC joints were examined. As the solder filling ratio increased, the joint strength increased, while ductile behavior decreased. When the pores were filled by solder (solder filling ratio: 100 %), the shear strength was similar to that of the non-porous Cu joint. After thermal shock cycling, LPC joint demonstrated lower degradation of shear strength compared to the non-porous Cu joint due to its structural characteristics. These results were attributed to the low yield strength of LPC and unique joining interface by pore structure of LPC.
{"title":"Evaluation of reliability of lotus-type porous Cu joint soldered by SAC305","authors":"Jae-Ho Shin , Keun-Soo Kim , Sang-Wook Kim , Jae-Won Kim , Min-Su Kim , Soong-Keun Hyun","doi":"10.1016/j.microrel.2025.115933","DOIUrl":"10.1016/j.microrel.2025.115933","url":null,"abstract":"<div><div>Lotus-type porous Cu (LPC) is a metallic material characterized by its cylindrical pore structure, which exhibits excellent thermal conductivity, fluid permeability, ductility, and impact energy absorption capabilities. To evaluate the applicability of LPC as electronic materials, LPC/dissimilar materials joints were fabricated using SAC305 solder. To consider the pore structure in LPC, the solder filling ratio was focused as key variables in this work. The microstructure, mechanical behaviors and thermal shock behavior of LPC joints were examined. As the solder filling ratio increased, the joint strength increased, while ductile behavior decreased. When the pores were filled by solder (solder filling ratio: 100 %), the shear strength was similar to that of the non-porous Cu joint. After thermal shock cycling, LPC joint demonstrated lower degradation of shear strength compared to the non-porous Cu joint due to its structural characteristics. These results were attributed to the low yield strength of LPC and unique joining interface by pore structure of LPC.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115933"},"PeriodicalIF":1.9,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1016/j.microrel.2025.115931
Meng Li , Xin Xu , Yunpeng Li , Yiqun Shi , Qingqing Sun , Hao Zhu
The continuous scaling of semiconductor devices has made aging effects, such as hot carrier injection (HCI) and negative bias temperature instability (NBTI), increasingly significant in advanced technology nodes. The resulting threshold voltage shifts impose more severe propagation delays on standard cell libraries, ultimately affecting circuit timing reliability. In this paper, we introduce a transistor-level aging analysis methodology to mitigate aging effects on the timing reliability of Scan D Flip-Flops (DFFs) based on a 14-nm FinFET platform. This methodology provides a detailed and accurate assessment of aging impacts and enables the identification of the modules most susceptible to degradation. Subsequently, temporal aging mitigation techniques are comparatively analyzed, and structural improvement schemes are proposed and validated. Simulation results demonstrate that the proposed improvements achieve stable operation across different process corners. At the cost of a 20 % increase in the Power-Delay Product (PDP), the aging-induced delay increase is reduced in all corners, with an average reduction of 55.5 % observed in the slow–slow (ss) corner.
{"title":"Aging mitigation of FinFET-based DFF through transistor-level analysis","authors":"Meng Li , Xin Xu , Yunpeng Li , Yiqun Shi , Qingqing Sun , Hao Zhu","doi":"10.1016/j.microrel.2025.115931","DOIUrl":"10.1016/j.microrel.2025.115931","url":null,"abstract":"<div><div>The continuous scaling of semiconductor devices has made aging effects, such as hot carrier injection (HCI) and negative bias temperature instability (NBTI), increasingly significant in advanced technology nodes. The resulting threshold voltage shifts impose more severe propagation delays on standard cell libraries, ultimately affecting circuit timing reliability. In this paper, we introduce a transistor-level aging analysis methodology to mitigate aging effects on the timing reliability of Scan D Flip-Flops (DFFs) based on a 14-nm FinFET platform. This methodology provides a detailed and accurate assessment of aging impacts and enables the identification of the modules most susceptible to degradation. Subsequently, temporal aging mitigation techniques are comparatively analyzed, and structural improvement schemes are proposed and validated. Simulation results demonstrate that the proposed improvements achieve stable operation across different process corners. At the cost of a 20 % increase in the Power-Delay Product (PDP), the aging-induced delay increase is reduced in all corners, with an average reduction of 55.5 % observed in the slow–slow (ss) corner.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115931"},"PeriodicalIF":1.9,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1016/j.microrel.2025.115934
Borui Yang , Guicui Fu , Bo Wan , Xiangfen Wang
The high density of interface defects at the gate oxide interface is closely related to the device characteristics and reliability of silicon carbide metal-oxide-semiconductor field effect transistors. However, an efficient and reliable characterization method for interface defects remains to be developed. In this work, we propose a neural network method for evaluating the interface trap density distribution and fixed oxide charge density using the transfer characteristics of devices. The neural network utilizes a long short-term memory structure to capture the mapping relationship between the transfer characteristic and the interface defect parameters. The numerical simulation data are used to form the training dataset of the network, and an effective preprocessing method is also presented. The proposed method was successfully verified by comparing simulated transfer characteristics using the evaluated results of commercial devices with corresponding measurements. Also, the interface defect parameters were evaluated by the subthreshold current method for comparison. The result shows that the evaluated results of the proposed method are close to the experimental evaluated results, with relative errors of 3.3 %, 6.6 %, and 28.2 % for the three devices under threshold voltage, respectively. Further, the proposed method was successfully applied during the high temperature gate bias tests to detect the degradation trend of the gate oxide interface. The result reflects its practicality for the interface reliability analysis of silicon carbide metal-oxide-semiconductor field effect transistors.
{"title":"An interface trap density evaluation method for SiC MOSFET based on neural network","authors":"Borui Yang , Guicui Fu , Bo Wan , Xiangfen Wang","doi":"10.1016/j.microrel.2025.115934","DOIUrl":"10.1016/j.microrel.2025.115934","url":null,"abstract":"<div><div>The high density of interface defects at the gate oxide interface is closely related to the device characteristics and reliability of silicon carbide metal-oxide-semiconductor field effect transistors. However, an efficient and reliable characterization method for interface defects remains to be developed. In this work, we propose a neural network method for evaluating the interface trap density distribution and fixed oxide charge density using the transfer characteristics of devices. The neural network utilizes a long short-term memory structure to capture the mapping relationship between the transfer characteristic and the interface defect parameters. The numerical simulation data are used to form the training dataset of the network, and an effective preprocessing method is also presented. The proposed method was successfully verified by comparing simulated transfer characteristics using the evaluated results of commercial devices with corresponding measurements. Also, the interface defect parameters were evaluated by the subthreshold current method for comparison. The result shows that the evaluated results of the proposed method are close to the experimental evaluated results, with relative errors of 3.3 %, 6.6 %, and 28.2 % for the three devices under threshold voltage, respectively. Further, the proposed method was successfully applied during the high temperature gate bias tests to detect the degradation trend of the gate oxide interface. The result reflects its practicality for the interface reliability analysis of silicon carbide metal-oxide-semiconductor field effect transistors.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115934"},"PeriodicalIF":1.9,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-11DOI: 10.1016/j.microrel.2025.115930
Chao Peng , Zhifeng Lei , Zhangang Zhang , Teng Ma , Hong Zhang , Yujuan He , Rui Gao , Xuefei Liu , Yun Huang
The radiation-induced single event burnout (SEB) is observed for SiC MOSFETs by conducting proton and spallation neutron irradiation. Proton irradiation experiments reveal that the SEB cross-section rises monotonically with increasing proton energy. When the SiC MOSFET is biased at 78 % of its rated voltage, the SEB cross-section increase from 5.02 × 10−11 cm2 to 5.12 × 10−10 cm2 as the proton energy increase from 60 MeV to 300 MeV. The SEB cross-sections for protons with energies above 100 MeV exceed those for spallation neutrons. It indicates that using the proton SEB cross-section at a single energy above 100 MeV would overestimate the atmospheric neutron-induced failure rate of SiC MOSFETs. The SEB caused by protons and spallation neutrons is strongly correlated with the ionizing energy deposition of their secondary ions from nuclear reactions. The information of the secondary ions produced by spallation neutron and proton is obtained through Particle and Heavy Ion Transport code System (PHITS) calculations. The simulation results indicate that the number of secondary ions capable of depositing sufficient energy to trigger SEB increases with proton energy. Therefore, the SEB cross section is correspondingly higher for higher-energy protons. For protons with energies above 100 MeV, the number of secondary ion products capable of triggering SEB is greater than that from spallation neutrons. This explains why the SEB cross-section for protons above 100 MeV is larger than that for spallation neutrons. By combining proton SEB cross-sections at five distinct energies, the atmospheric neutron-induced SEB failure rates at sea level for SiC MOSFETs are calculated to be range from 2.73 to 52.0 FIT when the devices are biased at 78 % to 94 % of their rated voltage. Based on the spallation neutron data, the failure rates range from 1.47 to 26.5 FIT for the same bias range. The failure rates calculated by these two methods are consistent, differing by less than 49 %. The findings indicate that both spallation neutrons and multi-energy proton irradiation are effective for estimating the failure rates of SiC MOSFETs under atmospheric neutron exposure.
{"title":"Comparison of SEB cross-sections between spallation neutron and mono-energetic proton for SiC MOSFETs","authors":"Chao Peng , Zhifeng Lei , Zhangang Zhang , Teng Ma , Hong Zhang , Yujuan He , Rui Gao , Xuefei Liu , Yun Huang","doi":"10.1016/j.microrel.2025.115930","DOIUrl":"10.1016/j.microrel.2025.115930","url":null,"abstract":"<div><div>The radiation-induced single event burnout (SEB) is observed for SiC MOSFETs by conducting proton and spallation neutron irradiation. Proton irradiation experiments reveal that the SEB cross-section rises monotonically with increasing proton energy. When the SiC MOSFET is biased at 78 % of its rated voltage, the SEB cross-section increase from 5.02 × 10<sup>−11</sup> cm<sup>2</sup> to 5.12 × 10<sup>−10</sup> cm<sup>2</sup> as the proton energy increase from 60 MeV to 300 MeV. The SEB cross-sections for protons with energies above 100 MeV exceed those for spallation neutrons. It indicates that using the proton SEB cross-section at a single energy above 100 MeV would overestimate the atmospheric neutron-induced failure rate of SiC MOSFETs. The SEB caused by protons and spallation neutrons is strongly correlated with the ionizing energy deposition of their secondary ions from nuclear reactions. The information of the secondary ions produced by spallation neutron and proton is obtained through Particle and Heavy Ion Transport code System (PHITS) calculations. The simulation results indicate that the number of secondary ions capable of depositing sufficient energy to trigger SEB increases with proton energy. Therefore, the SEB cross section is correspondingly higher for higher-energy protons. For protons with energies above 100 MeV, the number of secondary ion products capable of triggering SEB is greater than that from spallation neutrons. This explains why the SEB cross-section for protons above 100 MeV is larger than that for spallation neutrons. By combining proton SEB cross-sections at five distinct energies, the atmospheric neutron-induced SEB failure rates at sea level for SiC MOSFETs are calculated to be range from 2.73 to 52.0 FIT when the devices are biased at 78 % to 94 % of their rated voltage. Based on the spallation neutron data, the failure rates range from 1.47 to 26.5 FIT for the same bias range. The failure rates calculated by these two methods are consistent, differing by less than 49 %. The findings indicate that both spallation neutrons and multi-energy proton irradiation are effective for estimating the failure rates of SiC MOSFETs under atmospheric neutron exposure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115930"},"PeriodicalIF":1.9,"publicationDate":"2025-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-09DOI: 10.1016/j.microrel.2025.115928
Bandi Venkata Chandan, Kaushal Kumar Nigam, Bibhudendra Acharya, Adil Tanveer
This article investigates the performance of graphene based electrostatic doped tunnel field-effect transistors (G-ED-TFET) for energy-efficient applications. In this design, the drain and source regions are induced by applying polarity gate (PG) bias voltages, respectively. This approach eliminates doping control issues, reduces thermal budget constraints, and simplifies fabrication compared to conventional TFETs. Graphene is utilized in the channel region as a promising alternative material to silicon (Si) due to exceptional characteristics such as high electron mobility and a zero band gap. The G-ED-TFET device achieve an ON current of 1.34 × A/, threshold voltage (V) of 0.32 V, subthreshold swing (SS) of 3.34 mV/decade, and a switching ratio of 2.86 × . Analog/RF metrics suggest that their is minimum 10 improvement in every figure-of-metrics because graphene has an intrinsically small bandgap, which allows efficient tunneling from the P source to the graphene channel. To further use of G-ED-TFET device, it is important to assess its reliability for which we have chosen interface trap charges (ITCs) approach. In the presence of ITCs, G-ED-TFET shows less variation, as compare to ED-TFET indicates that the G-ED-TFET is more reliable. Overall, this work offers significant insights into the analog/RF characteristics of G-ED-TFET, enabling the development of optimized devices and ensuring dependable performance in many applications.
{"title":"Theoretical performance and reliability optimization of graphene based electrically doped tunnel FET under interface trap charge constraints: A device-level approach","authors":"Bandi Venkata Chandan, Kaushal Kumar Nigam, Bibhudendra Acharya, Adil Tanveer","doi":"10.1016/j.microrel.2025.115928","DOIUrl":"10.1016/j.microrel.2025.115928","url":null,"abstract":"<div><div>This article investigates the performance of graphene based electrostatic doped tunnel field-effect transistors (G-ED-TFET) for energy-efficient applications. In this design, the drain and source regions are induced by applying polarity gate (PG) bias voltages, respectively. This approach eliminates doping control issues, reduces thermal budget constraints, and simplifies fabrication compared to conventional TFETs. Graphene is utilized in the channel region as a promising alternative material to silicon (Si) due to exceptional characteristics such as high electron mobility and a zero band gap. The G-ED-TFET device achieve an ON current of 1.34 × <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>5</mn></mrow></msup></mrow></math></span> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span>, threshold voltage (V<span><math><msub><mrow></mrow><mrow><mi>t</mi><mi>h</mi></mrow></msub></math></span>) of 0.32 V, subthreshold swing (SS) of 3.34 mV/decade, and a switching ratio of 2.86 × <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>14</mn></mrow></msup></mrow></math></span>. Analog/RF metrics suggest that their is minimum 10<span><math><mo>×</mo></math></span> improvement in every figure-of-metrics because graphene has an intrinsically small bandgap, which allows efficient tunneling from the P<span><math><msup><mrow></mrow><mrow><mo>+</mo></mrow></msup></math></span> source to the graphene channel. To further use of G-ED-TFET device, it is important to assess its reliability for which we have chosen interface trap charges (ITCs) approach. In the presence of ITCs, G-ED-TFET shows less variation, as compare to ED-TFET indicates that the G-ED-TFET is more reliable. Overall, this work offers significant insights into the analog/RF characteristics of G-ED-TFET, enabling the development of optimized devices and ensuring dependable performance in many applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115928"},"PeriodicalIF":1.9,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-08DOI: 10.1016/j.microrel.2025.115929
Haonan Tian , Younis Ibrahim , Manasi Sharma , George Belev , Shijie Wen , Li Chen
This paper investigates the susceptibility of Transformer models, specifically DistilBERT, to Single Event Effects (SEEs) on the NVIDIA Jetson AGX Xavier, which poses significant risks in radiation-prone environments such as aerospace. One critical challenge is Silent Data Corruption (SDC), where errors caused by radiation may go undetected, potentially degrading model performance without immediate signs of failure. Using Two-Photon Absorption (TPA) laser testing, we analysed the model's robustness and innovatively proposed evaluating the impact of soft errors on the model by calculating the Euclidean distance (L2 distance) between the output tensor of each layer and its reference value. This approach allows us to assess the severity of soft errors on model performance. Our results reveal that critical errors significantly escalate when the L2 distance exceeds 1.0, highlighting the model's vulnerability to such disruptions. To address these issues, we firstly propose a layer-level Triple Modular Redundancy (TMR) strategy, achieving an 89.2 % reduction in error rates. Meanwhile, to alleviate the issue of excessive overhead in the TMR model, we introduce a Hybrid Selected Dual Modular Redundancy (HS-DMR) technique, which activates TMR operation only when the L2 distance threshold is surpassed. This approach maintains 85.8 % decrease of critical error rate with only 3.6 % latency overhead.
{"title":"Improving transformer model reliability on NVIDIA Jetson AGX: Insights from single event effects with two-photon absorption laser analysis","authors":"Haonan Tian , Younis Ibrahim , Manasi Sharma , George Belev , Shijie Wen , Li Chen","doi":"10.1016/j.microrel.2025.115929","DOIUrl":"10.1016/j.microrel.2025.115929","url":null,"abstract":"<div><div>This paper investigates the susceptibility of Transformer models, specifically DistilBERT, to Single Event Effects (SEEs) on the NVIDIA Jetson AGX Xavier, which poses significant risks in radiation-prone environments such as aerospace. One critical challenge is Silent Data Corruption (SDC), where errors caused by radiation may go undetected, potentially degrading model performance without immediate signs of failure. Using Two-Photon Absorption (TPA) laser testing, we analysed the model's robustness and innovatively proposed evaluating the impact of soft errors on the model by calculating the Euclidean distance (L2 distance) between the output tensor of each layer and its reference value. This approach allows us to assess the severity of soft errors on model performance. Our results reveal that critical errors significantly escalate when the L2 distance exceeds 1.0, highlighting the model's vulnerability to such disruptions. To address these issues, we firstly propose a layer-level Triple Modular Redundancy (TMR) strategy, achieving an 89.2 % reduction in error rates. Meanwhile, to alleviate the issue of excessive overhead in the TMR model, we introduce a Hybrid Selected Dual Modular Redundancy (HS-DMR) technique, which activates TMR operation only when the L2 distance threshold is surpassed. This approach maintains 85.8 % decrease of critical error rate with only 3.6 % latency overhead.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115929"},"PeriodicalIF":1.9,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-04DOI: 10.1016/j.microrel.2025.115925
Tianyuan Chen , Mengran Zhou , Hao Fu , Xiaohua Xu , Xinhua Dong , Yunjian Zhao , Gaoqiang Chen , Gong Zhang , Qingyu Shi
The reliability of different solder joints assembled with Sn-Zn, Sn-Ag-Cu, and Sn-Bi solders under thermal cycling conditions based on industrial production conditions was analyzed in this study. The results of dye and pull test indicated that there were significant differences in the number, types, and location of fractures at different component joints soldered with different solder. Due to the excellent mechanical properties and unique intermetallic compound (IMC) composition, the number of fractures in Sn-Zn solder joints is remarkably lower than the Sn-Ag-Cu and Sn-Bi solder, indicating that the Sn-Zn system is more reliable under thermal cycling. These findings demonstrated that Sn-Zn solder is more suitable for industrial production of the complex printed circuit boards (PCBs) and has a better durability.
{"title":"The thermal cycling response of Sn-Zn, Sn-Ag-Cu and Sn-Bi solder in industrial production","authors":"Tianyuan Chen , Mengran Zhou , Hao Fu , Xiaohua Xu , Xinhua Dong , Yunjian Zhao , Gaoqiang Chen , Gong Zhang , Qingyu Shi","doi":"10.1016/j.microrel.2025.115925","DOIUrl":"10.1016/j.microrel.2025.115925","url":null,"abstract":"<div><div>The reliability of different solder joints assembled with Sn-Zn, Sn-Ag-Cu, and Sn-Bi solders under thermal cycling conditions based on industrial production conditions was analyzed in this study. The results of dye and pull test indicated that there were significant differences in the number, types, and location of fractures at different component joints soldered with different solder. Due to the excellent mechanical properties and unique intermetallic compound (IMC) composition, the number of fractures in Sn-Zn solder joints is remarkably lower than the Sn-Ag-Cu and Sn-Bi solder, indicating that the Sn-Zn system is more reliable under thermal cycling. These findings demonstrated that Sn-Zn solder is more suitable for industrial production of the complex printed circuit boards (PCBs) and has a better durability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115925"},"PeriodicalIF":1.9,"publicationDate":"2025-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145226995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1016/j.microrel.2025.115919
T.S. Copetti , A. Chordia , M. Fieback , M. Taouil , S. Hamdioui , L.M. Bolzani Poehls
Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories adopted in several emerging applications. Despite all their advantages – mainly CMOS process compatibility, zero standby power, and high scalability and density – the use of ReRAMs in real applications depends on guaranteeing their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, including defects and process variations, that can cause faulty behaviors different from those observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into conventional and unique faults, considering three different temperatures (25, 100, and -40 °C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.
{"title":"Exploring the use of extreme temperatures to facilitate fault propagation in ReRAMs","authors":"T.S. Copetti , A. Chordia , M. Fieback , M. Taouil , S. Hamdioui , L.M. Bolzani Poehls","doi":"10.1016/j.microrel.2025.115919","DOIUrl":"10.1016/j.microrel.2025.115919","url":null,"abstract":"<div><div>Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories adopted in several emerging applications. Despite all their advantages – mainly CMOS process compatibility, zero standby power, and high scalability and density – the use of ReRAMs in real applications depends on guaranteeing their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, including defects and process variations, that can cause faulty behaviors different from those observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into conventional and unique faults, considering three different temperatures (25, 100, and -40 °C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115919"},"PeriodicalIF":1.9,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145226994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1016/j.microrel.2025.115922
Jing Sun , Xingyao Zhang , Mengjun Sun , Gang Yu , Yiyuan Wang , Lin Wen , Xuefeng Yu , Qi Guo , Yudong Li
As an important part of PMOS dosimeter, the radiation resistance of constant current source directly affects its measurement accuracy. This paper mainly analyzes the damage variation law of constant current source in space radiation environment, and studies the ionizing radiation effect of constant current source under different bias and dose rate. The results show that the three-terminal adjustable constant current source increases the percentage of current change caused by ionizing radiation when the constant current source is set to operate at a small current, causing more serious degradation.
{"title":"Ionizing radiation damage and accuracy degradation in PMOS dosimeter constant current sources under bias-dose rate coupling","authors":"Jing Sun , Xingyao Zhang , Mengjun Sun , Gang Yu , Yiyuan Wang , Lin Wen , Xuefeng Yu , Qi Guo , Yudong Li","doi":"10.1016/j.microrel.2025.115922","DOIUrl":"10.1016/j.microrel.2025.115922","url":null,"abstract":"<div><div>As an important part of PMOS dosimeter, the radiation resistance of constant current source directly affects its measurement accuracy. This paper mainly analyzes the damage variation law of constant current source in space radiation environment, and studies the ionizing radiation effect of constant current source under different bias and dose rate. The results show that the three-terminal adjustable constant current source increases the percentage of current change caused by ionizing radiation when the constant current source is set to operate at a small current, causing more serious degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115922"},"PeriodicalIF":1.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145159528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
扫码关注我们
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号