Journal of Computational Electronics最新文献

Lateral superjunctions (LSJ) are potential candidates for CMOS compatible high voltage devices in next-generation power integrated circuits. The prior works have modeled and developed design guidelines only for an ideal balanced LSJ, i.e., having equal charge in the n- and p-pillars. However, inevitable process variation during fabrication results in charge imbalance, ({k_{N}}), that yields a breakdown voltage, ({V_textrm{BR}}), significantly lower than the target breakdown voltage, ({V_textrm{BR,target}}). In this work, we use the method of Lagrange multipliers to derive analytical equations for the optimum pillar parameters of an LSJ; these parameters yield the minimum specific ON-resistance, ({R_textrm{ONSP}}), for a ({V_textrm{BR,target}}) and ({k_{N}}). The analytical solutions are verified using well-calibrated TCAD simulations for 0.1–1 kV Si LSJs and 1–10 kV 4H-SiC LSJs for ({k_{N}}) from 0.05 to 0.30 (signifying 5 to 30% imbalance between the n- and p-pillar charge). Our solutions show that the optimum aspect ratio, ({r_{0}}), varies between 8–12 for Si LSJs and 10–15 for 4H-SiC LSJs. Notably, our solution for an LSJ is found to yield significantly different optimum pillar parameters than our earlier solution for a vertical SJ for the same ({V_textrm{BR}}) and ({k_{N}}), due to the difference in their dependency of ({R_textrm{ONSP}}) on the pillar parameters. This justifies the need for customized solution for the design of LSJ.

In this paper, we study the dynamic of a position-dependent mass system confined in harmonic oscillator potential. We derive the eigensystems by solving the Schrödinger-like equation which describes this system. We construct coherent states à la Gazeau-Klauder for this system. We show that these states satisfy the Klauder’s mathematical condition to build coherent states. We compute and analyze some statistical properties of these states. We find that these states exhibit sub-Poissonian statistics. We also evaluate quasiprobability distributions such as the Wigner function to demonstrate graphically nonclassical features of these states.

As digital technology advances, the demand for high-performance, high-density, and low-power memory technologies continues to grow. To address these needs, the 2 Transistor 0 Capacitor (2T0C) DRAM architecture, featuring nondestructive read operations, has emerged as a promising alternative to conventional 1 Transistor 1 Capacitor DRAM. The InGaZnO (IGZO) channel material, known for low off-current and high mobility, enables long data retention and enhanced power efficiency in 2T0C DRAM. In this study, IGZO-based channel-all-around (CAA) and gate-all-around (GAA) FET structures were implemented using TCAD simulations, which were based on the well-calibrated physical carrier transport models with the measured IGZO channel device. The electrical characteristics, including the on/off-current ratio (I_on/I_off), were compared at the single-transistor level. For the 2T0C DRAM cell, variations in the gate length, critical dimension (CD), and underlap structure of the writing transistor (WTR) and reading transistor (RTR) were investigated, to evaluate memory characteristics such as data writing speed, retention, and single-cell disturbance, along with the feasibility of multi-bit operation. The analysis showed that the CAA structure provides faster data writing speeds, whereas the GAA structure—especially in the WTR configuration and 3 × 3 array design—offers significantly better retention and single-cell disturbance immunity. This study provides clear guidance for the structural optimization of IGZO-based 2T0C DRAM and practical insights into the designing next-generation high-density memory technologies.

The breakdown of GaN-based Schottky barrier diodes associated with impact ionization events initiated by electrons injected by tunneling is physically analyzed by means of a Monte Carlo simulator self-consistently coupled with a two-dimensional solution of the Poisson equation. Simulations of a realistic topology where different geometrical parameters are modified allow to identify their influence on the breakdown voltage. The correct physical modeling of two-dimensional effects is essential for a proper prediction of the breakdown. Epilayer doping and thickness, dielectric used for the passivation and lateral extension of the epilayer are analyzed. As expected, the lower the doping and the thicker the epilayer, the higher the value found for the breakdown voltage, but, interestingly, the results also indicate that the peak electric field present at the edge of the Schottky contact, which may be reduced by means of high-k dielectric passivation and a short lateral extension of the epilayer, plays a key role in the breakdown.

A quantum unitary gate is studied theoretically by perturbing a free charged particle in a one-dimensional box with a time- and position-varying electric field. The perturbed Hamiltonian is composed of a free particle Hamiltonian plus a perturbing electric potential such that the Schrödinger evolution in time T, the unitary evolution operator of the unperturbed system after truncation to a finite number of energy levels, approximates a given unitary gate such as the quantum Fourier transform gate. The idea is to truncate the half-wave Fourier sine series to M terms in the spatial variable (textbf{x}) before extending the potential as a Dyson series in the interaction picture to compute the evolution operator matrix elements up to the linear and quadratic integral functionals of ( textbf{V}_n(t)^{prime})s. As a result, we used the Dyson series with the Frobenius norm to reduce the difference between the derived gate energy and the given gate energy, and we determined the temporal performance criterion by plotting the noise-to-signal energy ratio. A mathematical explanation for a quantum gate’s magnetic control has also been provided. In addition, we provide a mathematical explanation for a quantum gate that uses magnetic control.

This study introduces a new memtranstor emulator circuit using second-generation current conveyors (CCII), providing an alternative to the only existing memtranstor emulator circuit in the literature. The proposed circuit consists of three CCIIs, one analog multiplier (AD633), two grounded resistors, and three grounded capacitors. The design is implemented using 180 nm CMOS technology, and its functionality is validated through PSPICE simulations. The circuit’s behavior is analyzed under various conditions including pinched hysteresis loops, Monte Carlo analysis, memory effect simulations, and temperature variation tests, all of which confirm its proper operation. Additionally, the circuit can be easily adapted between incremental and decremental memory emulators, demonstrating its versatility for various applications. The proposed emulator has been further validated through experimental implementation, confirming its feasibility for practical applications. A memtranstor-based chaotic oscillator is presented as an application example. Compared to the existing design in the literature, the proposed emulator offers several key advantages: It employs fewer active and passive components, leading to a simpler structure with the potential for more compact implementation. The absence of operational amplifiers (op-amps) improves bandwidth performance by eliminating the fixed gain-bandwidth product limitation, enabling higher gain levels at broader bandwidths. Additionally, the use of low-power CMOS parameters potentially allows for lower supply voltages, which, along with fewer components, can significantly reduce power consumption.

An oxide-based dual-gate thin film transistor (DGTFT) is considered an attractive option for flat panel displays due to its exceptional optical transparency and electronic performance. In this study, we use ZnO as an oxide semiconductor material for the channel region having rectangular multiple grain boundaries (GBs) and HfO₂ as gate dielectric to analyze the effect of GBs on the performance of DGTFT. It is challenging to precisely determine the threshold voltage (V_th) in accumulation-mode TFTs due to trap states within the GBs in a disordered semiconductor. In the proposed work, when depleted these GBs are modeled as a continuous line of charge with a Gaussian trap distribution, resulting in an analytical expression correlating the V_th to the GB trap density. It shows that the V_th increases as GB trap density increases. Additionally, the effect of multiple GBs on the electrical properties of a double-gate ZnO TFT is examined using TCAD at various trap energy levels (E_mid) and trap change densities (N_t). The performance of DGTFT is analyzed in CMG (common-mode-gate) and GTG (grounded-top-gate) modes. It was observed that for 40 GBs with increasing trap concentration from 10¹⁰ to 10¹² cm⁻² eV⁻¹, the V_th value rises from 0.5 to 1.4 V in CMG Mode. In contrast, GTG mode increases the V_th value from 1.0 to 2.2 V.

We present a comprehensive numerical and analytical study of information-theoretic measures–specifically, the Shannon entropy in position ((S_x)) and momentum ((S_{p_x})) spaces, for a non-relativistic fermion subject to a q-deformed Pöschl–Teller-like hyperbolic potential, including comparisons with the q-deformed Morse potential. By systematically varying the deformation parameter q, the inverse length scale (alpha), and the potential depth (V_0), we investigate their combined influence on spatial localization, uncertainty, and the global and local information content of the quantum states. Our results show that q induces a controllable trade-off between (S_x) and (S_{p_x}), while preserving their sum; (alpha) predominantly enhances total uncertainty, signaling increased delocalization; and (V_0) favors spatial localization at the cost of momentum spread. All configurations obey the Bialynicki-Birula–Mycielski (BBM) inequality, confirming the robustness of the approach. These findings underscore the deep connection between potential geometry and quantum information measures, with prospective implications for deformed quantum systems, relativistic extensions, and Lorentz symmetry-violating frameworks.

This manuscript investigates the mathematical modeling of a silicon nitride-based all-optical BVF reversible gate and reversible full adder modeled using an optical ring resonator (ORR). The design parameters of the proposed ORR are optimized to implement the desired mathematical model of reversible logic devices for all-optical computing. The capability of the proposed device is validated by the evaluated figure of merits like quality factor of 7750, contrast ratio of 19.54 dB, and extinction ratio of 20.29 dB. The CMOS compatibility nature of the silicon nitride-based structures also verifies the practical feasibility of the proposed device.

The rapid advancement of nanoelectronics demands materials with exceptional electrical and mechanical properties to support the development of high-performance, miniaturized devices. Graphene nanoplatelets (GNPs), a promising nanomaterial, have demonstrated significant potential in enhancing materials' electrical and structural characteristics at the nanoscale. This study explores the influence of GNPs on the electrical conductivity (EC) and compressive strength (CS) of nanoelectronic components, leveraging experimental investigations and advanced deep learning (DL) models, including non-autoregressive recurrent neural networks (NARNNs), verifiable convolutional neural networks (VCNNs), and Tsukamoto type-2 fuzzy inference system (TT2FIS). Experimental results revealed that the incorporation of GNPs at concentrations of 0.05% and 0.1% improved EC by 28.7% and 35.2%, respectively, while enhancing CS by 18.4% and 22.6%. These findings highlight the potential of GNP-enhanced materials for use in nanoelectronic devices that demand both high EC and mechanical reliability under thermal conditions. DL models demonstrated outstanding accuracy in predicting the properties of GNP-enhanced materials, with VCNNs achieving the highest performance. For EC predictions, VCNNs achieved a correlation coefficient (R) of 0.989, outperforming NARNNs (R = 0.976) and TT2FIS (R = 0.963). For CS, VCNNs exhibited an R-value of 0.993, compared to NARNNs (R = 0.982) and TT2FIS (R = 0.970). Error analysis further validated the superiority of VCNNs, as the mean square error (MSE) for EC predictions was 15.4% lower than NARNNs and 48.7% lower than TT2FIS. Similarly, for TS predictions, VCNNs achieved an MSE reduction of 12.8% compared to NARNNs and 51.3% compared to TT2FIS. SHapley Additive exPlanations analysis identified GNP concentration as the dominant factor influencing both EC and TS, followed by curing conditions. These results highlight the possible of DL-driven methods, particularly VCNNs, in optimizing GNP-enhanced materials for nanoelectronic applications, offering a fast and cost-effective pathway to design advanced materials for next-generation electronic devices.