Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243807
M. Floyd, A. Drake, R. Berry, H. Chase, Richard L. Willaman, Jarom Pena
An active processor throttling control loop using critical path timing measurements is enabled in the shipping POWER7™ based P775 supercomputer to prevent voltage droop induced failures. As a result, worst-case workload-induced voltage droop events are reduced by more than 50% compared to the system operating without the control loop. The reduction in operating voltage afforded by this technique translates to significant yield improvement, reduced failure rates, and improved power efficiency.
{"title":"Voltage droop reduction using throttling controlled by timing margin feedback","authors":"M. Floyd, A. Drake, R. Berry, H. Chase, Richard L. Willaman, Jarom Pena","doi":"10.1109/VLSIC.2012.6243807","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243807","url":null,"abstract":"An active processor throttling control loop using critical path timing measurements is enabled in the shipping POWER7™ based P775 supercomputer to prevent voltage droop induced failures. As a result, worst-case workload-induced voltage droop events are reduced by more than 50% compared to the system operating without the control loop. The reduction in operating voltage afforded by this technique translates to significant yield improvement, reduced failure rates, and improved power efficiency.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75533644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243770
S. Sano, Yasuhiko Takahashi, M. Horiguchi, M. Ota
A sub-1V 3.9μW bandgap reference (BGR) with small voltage variation of ±0.34% and low temperature drift (1mV) over a wide temperature range (-50°C ~ +150°C) and a wide voltage range (+0.9 V ~ +5.5V) by using a low power current mode BGR core and a piecewise-linear curvature compensation system. The BGR occupies 0.1mm2 in 0.13μm CMOS technology with triple well structure.
采用低功率电流模式BGR磁芯和分段线性曲率补偿系统，在-50°C ~ +150°C的宽温度范围和+0.9 V ~ +5.5V的宽电压范围内，获得了电压变化小(±0.34%)、温度漂移低(1mV)的亚1v 3.9μW带隙基准(BGR)。BGR占地0.1mm2，采用0.13μm CMOS技术，三孔结构。
{"title":"A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from −50°C to +150°C using piecewise-linear-current curvature compensation","authors":"S. Sano, Yasuhiko Takahashi, M. Horiguchi, M. Ota","doi":"10.1109/VLSIC.2012.6243770","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243770","url":null,"abstract":"A sub-1V 3.9μW bandgap reference (BGR) with small voltage variation of ±0.34% and low temperature drift (1mV) over a wide temperature range (-50°C ~ +150°C) and a wide voltage range (+0.9 V ~ +5.5V) by using a low power current mode BGR core and a piecewise-linear curvature compensation system. The BGR occupies 0.1mm<sup>2</sup> in 0.13μm CMOS technology with triple well structure.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85542030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243828
Jun Won Jung, B. Razavi
A half-rate clock and data recovery circuit and a deserializer employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz.
{"title":"A 25-Gb/s 5-mWCMOS CDR/deserializer","authors":"Jun Won Jung, B. Razavi","doi":"10.1109/VLSIC.2012.6243828","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243828","url":null,"abstract":"A half-rate clock and data recovery circuit and a deserializer employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75644240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243819
Yingzhe Hu, W. Rieutort-Louis, J. Sanz-Robinson, K. Song, J. Sturm, S. Wagner, N. Verma
Early-stage damage detection for buildings and bridges requires continuously sensing and assessing strain over large surfaces, yet with centimeter-scale resolution. To achieve this, we present a sensing sheet that combines high-performance ICs with flexible electronics, allowing bonding to such surfaces. The flexible electronics integrates thin-film strain gauges and amorphous-silicon control circuits, patterned on a polyimide sheet that can potentially span large areas. Non-contact links couple digital and analog signals to the ICs, allowing many ICs to be introduced via low-cost sheet lamination for energy-efficient readout and computation over a large number of sensors. Communication between distributed ICs is achieved by transceivers that exploit low-loss interconnects patterned on the polyimide sheet; the transceivers self-calibrate to the interconnect impedance to maximize transmit SNR. The system achieves multi-channel strain readout with sensitivity of 18μStrainRMS at an energy per measurement of 270nJ, while the communication energy is 12.8pJ/3.3pJ per bit (Tx/Rx) over 7.5m.
建筑物和桥梁的早期损伤检测需要连续地感知和评估大型表面上的应变，但具有厘米级的分辨率。为了实现这一目标，我们提出了一种结合高性能集成电路和柔性电子器件的传感片，允许在这些表面上进行键合。这种柔性电子设备将薄膜应变计和非晶硅控制电路集成在聚酰亚胺片上，可以覆盖大面积。非接触式链路将数字和模拟信号耦合到ic上，允许通过低成本片层压引入许多ic，从而在大量传感器上实现节能读出和计算。分布式集成电路之间的通信由利用聚酰亚胺片上图案的低损耗互连的收发器实现;收发器自校准到互连阻抗，以最大限度地提高发射信噪比。该系统在每次测量能量为270nJ的情况下实现了灵敏度为18μStrainRMS的多通道应变读出，而通信能量为12.8pJ/3.3pJ / bit (Tx/Rx)，传输距离为7.5m。
{"title":"High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs","authors":"Yingzhe Hu, W. Rieutort-Louis, J. Sanz-Robinson, K. Song, J. Sturm, S. Wagner, N. Verma","doi":"10.1109/VLSIC.2012.6243819","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243819","url":null,"abstract":"Early-stage damage detection for buildings and bridges requires continuously sensing and assessing strain over large surfaces, yet with centimeter-scale resolution. To achieve this, we present a sensing sheet that combines high-performance ICs with flexible electronics, allowing bonding to such surfaces. The flexible electronics integrates thin-film strain gauges and amorphous-silicon control circuits, patterned on a polyimide sheet that can potentially span large areas. Non-contact links couple digital and analog signals to the ICs, allowing many ICs to be introduced via low-cost sheet lamination for energy-efficient readout and computation over a large number of sensors. Communication between distributed ICs is achieved by transceivers that exploit low-loss interconnects patterned on the polyimide sheet; the transceivers self-calibrate to the interconnect impedance to maximize transmit SNR. The system achieves multi-channel strain readout with sensitivity of 18μStrainRMS at an energy per measurement of 270nJ, while the communication energy is 12.8pJ/3.3pJ per bit (Tx/Rx) over 7.5m.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76276232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243856
Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya
A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.
{"title":"A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW","authors":"Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2012.6243856","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243856","url":null,"abstract":"A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80151595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243846
Sudhir K. Satpathy, D. Sylvester, D. Blaauw
A thyristor-assisted standard cell compatible self-timed bidirectional repeater with no configuration overhead enables 8mm interconnects to achieve 37% higher speed at 20% lower energy over conventional repeaters in 65nm CMOS at 1.0V. Bidirectional operation without the need for configuration logic removes the need for clocking, yielding up to 14× higher energy efficiency at low data switching activity.
{"title":"A standard cell compatible bidirectional repeater with thyristor assist","authors":"Sudhir K. Satpathy, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2012.6243846","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243846","url":null,"abstract":"A thyristor-assisted standard cell compatible self-timed bidirectional repeater with no configuration overhead enables 8mm interconnects to achieve 37% higher speed at 20% lower energy over conventional repeaters in 65nm CMOS at 1.0V. Bidirectional operation without the need for configuration logic removes the need for clocking, yielding up to 14× higher energy efficiency at low data switching activity.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73832449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243785
Lingkai Kong, E. Alon
This paper presents a 65nm mm-wave transmitter efficiently supporting QPSK modulation and phased array functionality with a proposed oscillator modulation technique. The design delivers an average output power of 1mW at 10Gb/s and 0.8mW at 14Gb/s while consuming 21.5mA DC current from a 1V supply. At 10Gb/s, an overall transmitter efficiency of 4.65% is achieved, representing ~1.8X improvement over prior art [1].
{"title":"A 21.5mW 10+Gb/s mm-Wave phased-array transmitter in 65nm CMOS","authors":"Lingkai Kong, E. Alon","doi":"10.1109/VLSIC.2012.6243785","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243785","url":null,"abstract":"This paper presents a 65nm mm-wave transmitter efficiently supporting QPSK modulation and phased array functionality with a proposed oscillator modulation technique. The design delivers an average output power of 1mW at 10Gb/s and 0.8mW at 14Gb/s while consuming 21.5mA DC current from a 1V supply. At 10Gb/s, an overall transmitter efficiency of 4.65% is achieved, representing ~1.8X improvement over prior art [1].","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73451055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243804
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins
A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2.
{"title":"A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC","authors":"Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/VLSIC.2012.6243804","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243804","url":null,"abstract":"A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73559669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243808
M. Mansuri, B. Casper, F. O’Mahony
This paper demonstrates an in-situ delay measurement circuit which precisely characterizes key clocking circuits such as full phase rotation interpolators. This on-die all-digital circuit produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period. This circuit requires no calibration for variation or process, voltage, temperature (PVT) and measures the delay with 250fs absolute accuracy and repeatability of 10fs-rms.
{"title":"An on-die all-digital delay measurement circuit with 250fs accuracy","authors":"M. Mansuri, B. Casper, F. O’Mahony","doi":"10.1109/VLSIC.2012.6243808","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243808","url":null,"abstract":"This paper demonstrates an in-situ delay measurement circuit which precisely characterizes key clocking circuits such as full phase rotation interpolators. This on-die all-digital circuit produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period. This circuit requires no calibration for variation or process, voltage, temperature (PVT) and measures the delay with 250fs absolute accuracy and repeatability of 10fs-rms.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75937661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243811
J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang
This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10-15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.
{"title":"A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS","authors":"J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang","doi":"10.1109/VLSIC.2012.6243811","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243811","url":null,"abstract":"This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10-15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73862377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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