Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583134
Fengjiang Wang, Lili Zhou, Xiaojing Wang
The microstructure and electromigration of Bi and Sn in Cu/Sn58Bi/Cu and Cu/Sn58Bi /Sn3.0Ag0.5Cu/ Sn58Bi/Cu structural composite solder joint, were researched under the current density of 1.0×104 A/cm2 at room temperature. Two kinds of solder joints changed their morphology at both anode sides and cathode sides after current stressing. Bi layer was formed in the anode side while Sn layer was formed in the cathode side. The microanalysis indicated that Bi was the major diffusion element from cathode to anode and the migration of atomic Bi was faster than atomic Sn. Furthermore, through the comparison of two kinds of solder joints, it was easy to find that Sn3.0Ag0.5Cu suppressed the migration of atomic Bi and atomic Sn during electromigration.
{"title":"Electromigration behavior of Sn3.0Ag0.5Cu/Sn58Bi structural composite solder interconnect","authors":"Fengjiang Wang, Lili Zhou, Xiaojing Wang","doi":"10.1109/ICEPT.2016.7583134","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583134","url":null,"abstract":"The microstructure and electromigration of Bi and Sn in Cu/Sn58Bi/Cu and Cu/Sn58Bi /Sn3.0Ag0.5Cu/ Sn58Bi/Cu structural composite solder joint, were researched under the current density of 1.0×104 A/cm2 at room temperature. Two kinds of solder joints changed their morphology at both anode sides and cathode sides after current stressing. Bi layer was formed in the anode side while Sn layer was formed in the cathode side. The microanalysis indicated that Bi was the major diffusion element from cathode to anode and the migration of atomic Bi was faster than atomic Sn. Furthermore, through the comparison of two kinds of solder joints, it was easy to find that Sn3.0Ag0.5Cu suppressed the migration of atomic Bi and atomic Sn during electromigration.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"10 1","pages":"268-272"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82100176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583275
Hai-yang Chen, X. Jing, J. Shang
In order to meet the need of high integration and low cost of wireless communication systems, passive devices are widely used in all kinds of systems. This paper introduces an innovative method to manufacture integrated passive inductors based on glass reflow process. IPDs(integrated passive devices) have been simulated by 3D EM(electromagnetic) simulator software HFSS(high frequency structure simulator). From 0GHz to 10GHz, the Q value is above 200, higher than the Q value of conventional thin film inductors. Moreover, several key parameters of spiral inductors including inductor diameter, inductor thickness, substrate thickness, inductor width and inductor space are investigated. Finally, manufacturing process of inductors is presented.
{"title":"Electrical simulation and fabrication of high Q spiral inductors on glass substrate using the glass reflow process","authors":"Hai-yang Chen, X. Jing, J. Shang","doi":"10.1109/ICEPT.2016.7583275","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583275","url":null,"abstract":"In order to meet the need of high integration and low cost of wireless communication systems, passive devices are widely used in all kinds of systems. This paper introduces an innovative method to manufacture integrated passive inductors based on glass reflow process. IPDs(integrated passive devices) have been simulated by 3D EM(electromagnetic) simulator software HFSS(high frequency structure simulator). From 0GHz to 10GHz, the Q value is above 200, higher than the Q value of conventional thin film inductors. Moreover, several key parameters of spiral inductors including inductor diameter, inductor thickness, substrate thickness, inductor width and inductor space are investigated. Finally, manufacturing process of inductors is presented.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"9 1","pages":"901-904"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78789184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583161
Zhixue Liu, Xiaosong Ma, Qiulin Ding, G. Zhang
With the wide application of microelectronics packaging products in the industry, the chip have been more and more attention in the harsh environment of high temperature, high humidity. Therefore how to rapidly deliver high reliability products to market has been one of the issues of concern in the microelectronics industry. However moisture sensitivity level (MSL) analysis in microelectronics packaging is one of the most time consuming problem. Thus it is important to study the mechanism and method of the analysis of moisture sensitivity and shorten the analysis time. In this paper the fast analysis of microelectronic package MS L is achieved by the approach of an equal weight of water increasing at different conditions by simulation. According to project requirements, the ESOP8 is chosen as experimental device. Further the model is established, which is used to calculate equal moisture weight increase, and 10 to 67 acceleration factors are obtained. The purpose of this paper is to realize MSL the fast reliability evaluation method for microelectronics packaging industry. Finally using ANS YS finite element simulation is for the calculation.
{"title":"Fast MSL analysis of microelectronic packages by using equal weight increasing method","authors":"Zhixue Liu, Xiaosong Ma, Qiulin Ding, G. Zhang","doi":"10.1109/ICEPT.2016.7583161","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583161","url":null,"abstract":"With the wide application of microelectronics packaging products in the industry, the chip have been more and more attention in the harsh environment of high temperature, high humidity. Therefore how to rapidly deliver high reliability products to market has been one of the issues of concern in the microelectronics industry. However moisture sensitivity level (MSL) analysis in microelectronics packaging is one of the most time consuming problem. Thus it is important to study the mechanism and method of the analysis of moisture sensitivity and shorten the analysis time. In this paper the fast analysis of microelectronic package MS L is achieved by the approach of an equal weight of water increasing at different conditions by simulation. According to project requirements, the ESOP8 is chosen as experimental device. Further the model is established, which is used to calculate equal moisture weight increase, and 10 to 67 acceleration factors are obtained. The purpose of this paper is to realize MSL the fast reliability evaluation method for microelectronics packaging industry. Finally using ANS YS finite element simulation is for the calculation.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"28 1","pages":"391-394"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87907333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583315
K. Best, Gurvinder Singh, R. McCleary
For more than 50 years the semiconductor industry has pursued Moore's law, continuously improving device performance, reducing cost, and scaling transistor geometries down to where advanced CMOS has reached beyond the 10nm technology node. The commensurate increase in I/O count has created many challenges for device packaging which hitherto was considered low cost with simple solutions. It was once thought that old backend foundry lithography steppers could be used to address the new packaging requirements; which was true whilst the substrates remained in the traditional 300mm Silicon format. The recent unprecedented rapid growth in Fan Out Wafer Level Packaging (FOWLP) applications has introduced a more complicated landscape of process challenges, with no restriction on substrate format, where cost is the main driver and high yields are mandatory. This paper discusses the lithography process challenges that have ensued from disruptive FOWLP, and more recently the paradigm shift to Fan Out Panel Level Packaging (FOPLP). The work reports on lithography solutions for CD control over topography and high aspect ratio imaging of 2μm line/space RDL. In addition, the introduction of new inspection capabilities for defects and metrology is reported for both wafers and panels. The increase in lithography productivity and cost reduction provided by FOPLP is also discussed with production examples.
{"title":"Advanced packaging lithography and inspection solutions for next generation FOWLP-FOPLP processing","authors":"K. Best, Gurvinder Singh, R. McCleary","doi":"10.1109/ICEPT.2016.7583315","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583315","url":null,"abstract":"For more than 50 years the semiconductor industry has pursued Moore's law, continuously improving device performance, reducing cost, and scaling transistor geometries down to where advanced CMOS has reached beyond the 10nm technology node. The commensurate increase in I/O count has created many challenges for device packaging which hitherto was considered low cost with simple solutions. It was once thought that old backend foundry lithography steppers could be used to address the new packaging requirements; which was true whilst the substrates remained in the traditional 300mm Silicon format. The recent unprecedented rapid growth in Fan Out Wafer Level Packaging (FOWLP) applications has introduced a more complicated landscape of process challenges, with no restriction on substrate format, where cost is the main driver and high yields are mandatory. This paper discusses the lithography process challenges that have ensued from disruptive FOWLP, and more recently the paradigm shift to Fan Out Panel Level Packaging (FOPLP). The work reports on lithography solutions for CD control over topography and high aspect ratio imaging of 2μm line/space RDL. In addition, the introduction of new inspection capabilities for defects and metrology is reported for both wafers and panels. The increase in lithography productivity and cost reduction provided by FOPLP is also discussed with production examples.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"14 1","pages":"1090-1094"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88283913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583170
Yankang Han, Baotan Zhang, Pengli Zhu, Qianqian Liu, Yougen Hu, R. Sun, C. Wong
In this paper, Ag nano-particles (Ag-NPs) with size of 50 nm, good stability and dispersion have been prepared via the tradition polyol method. Then, a small amount of this prepared nanosized Ag particles combined with the common used Ag micro-flake (Ag-MFs) were used as the conductive fillers to fabricate the isotropic electrically conductive adhesive (ICA). The content of the Ag-NPs on the electrical properties of the ICAs have been studied systematically. It is showed that, only a small amount of Ag-NPs, much lower than literature reported previously, can dramatically improve the electrical conductivity of the ICA based on Ag-MFs. The results indicated that for the 80wt% Ag-MFs filled ICA, after introducing 0.24wt% Ag-NPs, the volume resistivity of the samples could be reduced from 1.14 ×10-3 Ω·cm to 1.37×10-4 Ω·cm. ICA made by above method with the 70wt % Ag fillers have excellent overall performance with higher shear strength of 26.35 Mpa and a lower volume resistivity of 8.00×10-4 Ω·cm, which was considered to be an ideal ICA candidate for electronic packaging applications.
{"title":"Preparation of highly conductive adhesives by insitu incorporation of silver nanoparticles","authors":"Yankang Han, Baotan Zhang, Pengli Zhu, Qianqian Liu, Yougen Hu, R. Sun, C. Wong","doi":"10.1109/ICEPT.2016.7583170","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583170","url":null,"abstract":"In this paper, Ag nano-particles (Ag-NPs) with size of 50 nm, good stability and dispersion have been prepared via the tradition polyol method. Then, a small amount of this prepared nanosized Ag particles combined with the common used Ag micro-flake (Ag-MFs) were used as the conductive fillers to fabricate the isotropic electrically conductive adhesive (ICA). The content of the Ag-NPs on the electrical properties of the ICAs have been studied systematically. It is showed that, only a small amount of Ag-NPs, much lower than literature reported previously, can dramatically improve the electrical conductivity of the ICA based on Ag-MFs. The results indicated that for the 80wt% Ag-MFs filled ICA, after introducing 0.24wt% Ag-NPs, the volume resistivity of the samples could be reduced from 1.14 ×10-3 Ω·cm to 1.37×10-4 Ω·cm. ICA made by above method with the 70wt % Ag fillers have excellent overall performance with higher shear strength of 26.35 Mpa and a lower volume resistivity of 8.00×10-4 Ω·cm, which was considered to be an ideal ICA candidate for electronic packaging applications.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"52 1","pages":"434-438"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83953379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583390
Wei Liu, Shunong Zhang, Yushen Jin, T. Zhang, L. C. Guo
The die bonding technology played a key role during the heat dissipating process in the high power LED packaging. At present, many manufacturers were confused about which kind of bonding technology they should choose. In this study, the high power LED devices from Cree and Lumileds were employed to study their die-bonding technologies. For the tested Cree's products, the initial interface had few voids before aged, however, under the action of injection current, the voids would initiated and propagated along the bonding boundary between LED chip and heats sink. For the tested Rebel LEDs, the crack and delamination of bonding pads were observed at the LED chip side.
{"title":"Failure analysis of die-bonding interfaces between LED chip and heat sink","authors":"Wei Liu, Shunong Zhang, Yushen Jin, T. Zhang, L. C. Guo","doi":"10.1109/ICEPT.2016.7583390","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583390","url":null,"abstract":"The die bonding technology played a key role during the heat dissipating process in the high power LED packaging. At present, many manufacturers were confused about which kind of bonding technology they should choose. In this study, the high power LED devices from Cree and Lumileds were employed to study their die-bonding technologies. For the tested Cree's products, the initial interface had few voids before aged, however, under the action of injection current, the voids would initiated and propagated along the bonding boundary between LED chip and heats sink. For the tested Rebel LEDs, the crack and delamination of bonding pads were observed at the LED chip side.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"36 1","pages":"1423-1426"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82944760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583179
H. Zhang, C. Li, P. Fan
In this work, thermal and flow characteristics for the metallic foam heat sinks (FHSs) with the central impingement flow were studied with de-ionized water coolant. Such a flow configuration helps to reduce the pressure drop inherent for straight flow in porous foams. The reduction in the pressure drop is analyzed based on the one-dimensional porous medium model and verified with experimental measurement. The FHSs was fabricated and their thermal and flow characteristics were experimentally tested by integrating with a thermal test chip in BGA package format. The test chip has been built in with thermal diodes and resistors as heating source and junction temperature measurement. The foam materials were made of copper with the porosity ranging 60%-90% at the same pore density of 60 PPI (pores per inch), which were first brazed to the copper cavity and then assembled with a cover plate to form the flow channels. The cover plate was fabricated with an inlet slot at the center and two outlets at the two ends to provide a uniform impingement flow on the top of the foam. The idea is to split the fluid flow at the center of the heating component so that the pressure drop through the bulk foam material is reduced. As a result, the pressure drop is found to drop significantly without sacrificing the thermal performance for the present FHSs.
{"title":"Thermal and flow characteristics of device integrated metallic foam heat sinks with central impingement flow","authors":"H. Zhang, C. Li, P. Fan","doi":"10.1109/ICEPT.2016.7583179","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583179","url":null,"abstract":"In this work, thermal and flow characteristics for the metallic foam heat sinks (FHSs) with the central impingement flow were studied with de-ionized water coolant. Such a flow configuration helps to reduce the pressure drop inherent for straight flow in porous foams. The reduction in the pressure drop is analyzed based on the one-dimensional porous medium model and verified with experimental measurement. The FHSs was fabricated and their thermal and flow characteristics were experimentally tested by integrating with a thermal test chip in BGA package format. The test chip has been built in with thermal diodes and resistors as heating source and junction temperature measurement. The foam materials were made of copper with the porosity ranging 60%-90% at the same pore density of 60 PPI (pores per inch), which were first brazed to the copper cavity and then assembled with a cover plate to form the flow channels. The cover plate was fabricated with an inlet slot at the center and two outlets at the two ends to provide a uniform impingement flow on the top of the foam. The idea is to split the fluid flow at the center of the heating component so that the pressure drop through the bulk foam material is reduced. As a result, the pressure drop is found to drop significantly without sacrificing the thermal performance for the present FHSs.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"23 1","pages":"477-481"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86719164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diamond-Cu matrix composite with high thermal conductivity and low coefficient of thermal expansion has been the high-performance thermal management materials. High-performance copper-coated diamond composite powders were successfully prepared using electroless plating at an appropriate bath temperature, pH value, copper ions concentration. The XRD results showed the coated Cu was highly pure with very little oxygen content. The SEM results that the particle size and surface roughness increased, with the increase of bath temperature, pH value, copper ions concentration separately. Finally, diamond-Cu composite powers with dense Cu coating and homogeneous Cu particles could be obtained under the optimum process conditions at the reaction temperature of 45 °C, pH value of 12.5 and copper ions concentration of 0.10 mol/L.
{"title":"The microanalysis of copper-coated diamond composite powders prepared by electroless plating","authors":"Lianmeng Zhang, Shuya Xiong, Ruxia Liu, Jian Zhang, G. Luo, Q. Shen","doi":"10.1109/ICEPT.2016.7583389","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583389","url":null,"abstract":"Diamond-Cu matrix composite with high thermal conductivity and low coefficient of thermal expansion has been the high-performance thermal management materials. High-performance copper-coated diamond composite powders were successfully prepared using electroless plating at an appropriate bath temperature, pH value, copper ions concentration. The XRD results showed the coated Cu was highly pure with very little oxygen content. The SEM results that the particle size and surface roughness increased, with the increase of bath temperature, pH value, copper ions concentration separately. Finally, diamond-Cu composite powers with dense Cu coating and homogeneous Cu particles could be obtained under the optimum process conditions at the reaction temperature of 45 °C, pH value of 12.5 and copper ions concentration of 0.10 mol/L.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"74 1","pages":"1418-1422"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88956286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583191
F. Huang, Yawei Liu, Mingliang L. Huang
A highly stable non-cyanide electroplating bath which can maintain clear at least one month was developed based on Au(III)-Sn(II) using 5,5-dimetheyl-hydantoin (DMH) and pyrophosphate as complexes. The combination of DMH and pyrophosphate can effectively minimize the difference of the deposition potentials between Au and Sn, making the codeposition of Au-Sn alloys possible. The cyclic voltammetry (CV) curve revealed that the codeposition of Au and Sn occurred at the potential of -790mV with a peak potential of -900mV. Pulsed plating was employed to optimize the morphology and composition of Au-Sn alloy films. The effects of pulse frequency, duty percentage and peak current density on the morphology and composition of the deposits were investigated. The compact Au-Sn eutectic alloy with Sn content controlled from 10 at.% to 50 at.% can be obtained. The Au-Sn deposits were characterized by the scanning electron microscopic (SEM) and energy-dispersive spectroscopic (EDS) analyses.
{"title":"Development of a stable non-cyanide gold-tin electroplating solution for optoelectronic applications","authors":"F. Huang, Yawei Liu, Mingliang L. Huang","doi":"10.1109/ICEPT.2016.7583191","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583191","url":null,"abstract":"A highly stable non-cyanide electroplating bath which can maintain clear at least one month was developed based on Au(III)-Sn(II) using 5,5-dimetheyl-hydantoin (DMH) and pyrophosphate as complexes. The combination of DMH and pyrophosphate can effectively minimize the difference of the deposition potentials between Au and Sn, making the codeposition of Au-Sn alloys possible. The cyclic voltammetry (CV) curve revealed that the codeposition of Au and Sn occurred at the potential of -790mV with a peak potential of -900mV. Pulsed plating was employed to optimize the morphology and composition of Au-Sn alloy films. The effects of pulse frequency, duty percentage and peak current density on the morphology and composition of the deposits were investigated. The compact Au-Sn eutectic alloy with Sn content controlled from 10 at.% to 50 at.% can be obtained. The Au-Sn deposits were characterized by the scanning electron microscopic (SEM) and energy-dispersive spectroscopic (EDS) analyses.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"21 6","pages":"538-541"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91488526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583147
Haoran Wen, Yaqiang Ji, Kai Zhang, M. Yuen, S. Lee, Xianzhu Fu, R. Sun, C. Wong
Low melting alloy is mixed with Cu filler as thermal interface materials. The thermal performance is investigated by inserting the composite between Al blocks. The ratio of Cu filler is optimized to be 50% to achieve the lowest thermal resistance.
{"title":"Low melting alloy composites as thermal interface materials with low thermal resistance","authors":"Haoran Wen, Yaqiang Ji, Kai Zhang, M. Yuen, S. Lee, Xianzhu Fu, R. Sun, C. Wong","doi":"10.1109/ICEPT.2016.7583147","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583147","url":null,"abstract":"Low melting alloy is mixed with Cu filler as thermal interface materials. The thermal performance is investigated by inserting the composite between Al blocks. The ratio of Cu filler is optimized to be 50% to achieve the lowest thermal resistance.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"49 3","pages":"331-333"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91503161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}