Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583234
W. Zhonghua, Xiao Hui
To study the short-circuit failure on lead-free solder joints soldering with no cleaning flux after heat and humidity test(85°/85%RH) for several days, stereomicroscope and scanning electronic microscope(SEM) and energy spectrometer(EDS) are used to inspect the failure mode and phenomenon, further analyze the root cause of the short-circuit failure. The results showed that, the failure of short-cut between two solder joints was due to tin migration growth to contact each other under the effects of wet circumstance and direct current, tin migration was mainly related to the residual of no-cleaning flux.
{"title":"Study on short-circuit failure of solder-joint interconnections","authors":"W. Zhonghua, Xiao Hui","doi":"10.1109/ICEPT.2016.7583234","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583234","url":null,"abstract":"To study the short-circuit failure on lead-free solder joints soldering with no cleaning flux after heat and humidity test(85°/85%RH) for several days, stereomicroscope and scanning electronic microscope(SEM) and energy spectrometer(EDS) are used to inspect the failure mode and phenomenon, further analyze the root cause of the short-circuit failure. The results showed that, the failure of short-cut between two solder joints was due to tin migration growth to contact each other under the effects of wet circumstance and direct current, tin migration was mainly related to the residual of no-cleaning flux.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"12 1","pages":"727-729"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79121635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583263
Zhen-zhu Zheng, Fan Yang, Chunqing Wang
As the integrated circuit and semiconductor industry developing rapidly, traditional micro-joining technology can not meet the new high-power devices challenge. Due to the size effect, nano-materials can offer low-temperature connection and high-temperature service property, which may be a promising approach for the high-power application. In the interconnection process, such as nano-Ag solder, the sintering temperature is much higher than the theoretical calculating value. This huge temperature difference is related to the microstructure gap between the nanostructure and the conventional pad. In order to achieve the low-temperature joining and increase the interconnection efficiency, the Ni nanostructure was deposited on the Cu pad surface by the electrochemical method in this paper. The Ni nanostructure could reduce the size difference between the nano-solder and the traditional pad. It is significant to control the Ni surface nanostructure. The electrochemical parameters, such as current density and temperature were studied. The surface nanostructure and nano-solder sintering process were investigated. The interconnection can be completed in lower temperature compared with the traditional joining process. The whole connection could be finished more efficiently.
{"title":"Study of interconnection between Ni nano-array and nano-Ag solder","authors":"Zhen-zhu Zheng, Fan Yang, Chunqing Wang","doi":"10.1109/ICEPT.2016.7583263","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583263","url":null,"abstract":"As the integrated circuit and semiconductor industry developing rapidly, traditional micro-joining technology can not meet the new high-power devices challenge. Due to the size effect, nano-materials can offer low-temperature connection and high-temperature service property, which may be a promising approach for the high-power application. In the interconnection process, such as nano-Ag solder, the sintering temperature is much higher than the theoretical calculating value. This huge temperature difference is related to the microstructure gap between the nanostructure and the conventional pad. In order to achieve the low-temperature joining and increase the interconnection efficiency, the Ni nanostructure was deposited on the Cu pad surface by the electrochemical method in this paper. The Ni nanostructure could reduce the size difference between the nano-solder and the traditional pad. It is significant to control the Ni surface nanostructure. The electrochemical parameters, such as current density and temperature were studied. The surface nanostructure and nano-solder sintering process were investigated. The interconnection can be completed in lower temperature compared with the traditional joining process. The whole connection could be finished more efficiently.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"15 1","pages":"849-851"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79136092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583309
Hua Lu, C. Bailey
The Clech Algorithm is an approximate method for the prediction of the stress state and damage of solder joints of electronics components such as Flipchip, Ball Grid Array that are undergone time dependent temperature load. It can be used to predict the reliability of solder joint under temperature cycling conditions. In this work, the application of this algorithm has been described and applied to predict the stress/strain and plastic work density in IGBT solder joints. The results are compared with 2D Finite Element analysis and it is concluded that the Clech Algorithm can be used for reliability prediction of IGBT solder joint.
{"title":"Reliability prediction for IGBT solder joints using Clech Algorithm","authors":"Hua Lu, C. Bailey","doi":"10.1109/ICEPT.2016.7583309","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583309","url":null,"abstract":"The Clech Algorithm is an approximate method for the prediction of the stress state and damage of solder joints of electronics components such as Flipchip, Ball Grid Array that are undergone time dependent temperature load. It can be used to predict the reliability of solder joint under temperature cycling conditions. In this work, the application of this algorithm has been described and applied to predict the stress/strain and plastic work density in IGBT solder joints. The results are compared with 2D Finite Element analysis and it is concluded that the Clech Algorithm can be used for reliability prediction of IGBT solder joint.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"63 1","pages":"1059-1063"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84206249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583172
Long Zhang, Chunyue Huang, Wei Huang, Tian-ming Li, Jianwei Hua
The 3D finite element analysis model of Package-on-Package solder joints was set up based on Patran software. The natural frequency, vibration mode of the model was analyzed under the condition of random vibration, the stress and strain distribution and the strain power spectrum density of response curves of the Package-on-Package solder joints were obtained, and the random vibration fatigue life of the Package-on-Package solder joints were also calculated out based on the power spectrum and rain flow count method; the influence of pad diameter on the random vibration fatigue life of the Package-on-Package solder joints were analyzed. The results show that the Package-on-Package solder joints of the model in this paper has the random vibration fatigue life of 997 hours; on the condition of the pad diameter of the second-layer solder joints increases from 0.15 mm to 0.30mm, the Package-on-Package solder joints vibration fatigue life increases with the increase of the pad diameter.
{"title":"Study of Package-on-Package solder joints under random vibration load based on Patran","authors":"Long Zhang, Chunyue Huang, Wei Huang, Tian-ming Li, Jianwei Hua","doi":"10.1109/ICEPT.2016.7583172","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583172","url":null,"abstract":"The 3D finite element analysis model of Package-on-Package solder joints was set up based on Patran software. The natural frequency, vibration mode of the model was analyzed under the condition of random vibration, the stress and strain distribution and the strain power spectrum density of response curves of the Package-on-Package solder joints were obtained, and the random vibration fatigue life of the Package-on-Package solder joints were also calculated out based on the power spectrum and rain flow count method; the influence of pad diameter on the random vibration fatigue life of the Package-on-Package solder joints were analyzed. The results show that the Package-on-Package solder joints of the model in this paper has the random vibration fatigue life of 997 hours; on the condition of the pad diameter of the second-layer solder joints increases from 0.15 mm to 0.30mm, the Package-on-Package solder joints vibration fatigue life increases with the increase of the pad diameter.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"32 1","pages":"443-447"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85124633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583359
Zhenchao Li, Qian Wang, Yu Chen, Guangjun Cui, Zhao-Lin Liu
Before mass production, designed IC will be firstly verified using a Multi Project Wafer (MPW) procedure. How to package the MPW chips in a short time with a reasonable price is the common need of design houses. The Quad Flat Package (QFP) cavity carrier provides a “house” to protect the chips, and is strongly accepted by IC design companies and research parties. But usually, the QFP cavity carrier is shaped by ceramic in a high price. This article will present an EMC (Epoxy Molding Compound) based QFP cavity carrier which is developed by a microelectronic transfer-molding technology with double side film lining the mold parts. The design of EMC based QFP cavity carrier is elaborated and the development of QFP cavity carrier through by Film Assistant Molding (FAM) technology provided by the Boschman molding tool is demonstrated. After unit and strip drawing, molding process with software of mold flow was simulated. The simulation results showed all of the units in the strip can be fully filled and the compound was void free. Together with previous experience in QFN (Quad Flat No-lead Package) cavity products, it is concluded that QFP plastic cavity carriers will become universal kits for MPW chip or testing chip package in an acceptable price and delivery time.
{"title":"QFP plastic cavity carrier design for MPW chip package","authors":"Zhenchao Li, Qian Wang, Yu Chen, Guangjun Cui, Zhao-Lin Liu","doi":"10.1109/ICEPT.2016.7583359","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583359","url":null,"abstract":"Before mass production, designed IC will be firstly verified using a Multi Project Wafer (MPW) procedure. How to package the MPW chips in a short time with a reasonable price is the common need of design houses. The Quad Flat Package (QFP) cavity carrier provides a “house” to protect the chips, and is strongly accepted by IC design companies and research parties. But usually, the QFP cavity carrier is shaped by ceramic in a high price. This article will present an EMC (Epoxy Molding Compound) based QFP cavity carrier which is developed by a microelectronic transfer-molding technology with double side film lining the mold parts. The design of EMC based QFP cavity carrier is elaborated and the development of QFP cavity carrier through by Film Assistant Molding (FAM) technology provided by the Boschman molding tool is demonstrated. After unit and strip drawing, molding process with software of mold flow was simulated. The simulation results showed all of the units in the strip can be fully filled and the compound was void free. Together with previous experience in QFN (Quad Flat No-lead Package) cavity products, it is concluded that QFP plastic cavity carriers will become universal kits for MPW chip or testing chip package in an acceptable price and delivery time.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"7 1","pages":"1288-1292"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78516312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583151
Jiayun Feng, Baolei Liu, Yanhong Tian, B. Zhang
In this paper, the interfacial reaction and the grain orientation of Cu6Sn5 intermetallic compound was investigated in Cu/molten Sn/Cu interconnection system under the current density of 1.0 × 102A/cm2 at 260 °C. The imposed electric current significantly accelerated the Cu6Sn5 growth rate at anode side under the effect of solid-liquid electromigration, while it has no obvious effect on the Cu3Sn growth rate. The growth kinetics calculation results showed that with the passage of electric current, the growth of Cu6Sn5 compound at the cathode was determined by reaction process, while the Cu3Sn growth was diffusion-controlled. In addition, the current can strongly influence the orientation of Cu6Sn5 phase in Cu-molten Sn-Cu system. There was a strong texture of [0001] direction in Cu6Sn5 phase, which was paralleled with the direction of electron flow. This result indicated that the electrons traveled along some particular directions and were scattered least by the lattices. The newly formed Cu-Sn compounds orientated themselves in those particular growth directions to facilitate electron flow.
{"title":"Influence of electric current on the grain orientation of Cu-Sn intermetallic compounds in Cu/molten Sn/Cu interconnection system","authors":"Jiayun Feng, Baolei Liu, Yanhong Tian, B. Zhang","doi":"10.1109/ICEPT.2016.7583151","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583151","url":null,"abstract":"In this paper, the interfacial reaction and the grain orientation of Cu<sub>6</sub>Sn<sub>5</sub> intermetallic compound was investigated in Cu/molten Sn/Cu interconnection system under the current density of 1.0 × 10<sup>2</sup>A/cm<sup>2</sup> at 260 °C. The imposed electric current significantly accelerated the Cu<sub>6</sub>Sn<sub>5</sub> growth rate at anode side under the effect of solid-liquid electromigration, while it has no obvious effect on the Cu<sub>3</sub>Sn growth rate. The growth kinetics calculation results showed that with the passage of electric current, the growth of Cu<sub>6</sub>Sn<sub>5</sub> compound at the cathode was determined by reaction process, while the Cu<sub>3</sub>Sn growth was diffusion-controlled. In addition, the current can strongly influence the orientation of Cu<sub>6</sub>Sn<sub>5</sub> phase in Cu-molten Sn-Cu system. There was a strong texture of [0001] direction in Cu<sub>6</sub>Sn<sub>5</sub> phase, which was paralleled with the direction of electron flow. This result indicated that the electrons traveled along some particular directions and were scattered least by the lattices. The newly formed Cu-Sn compounds orientated themselves in those particular growth directions to facilitate electron flow.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"89 1","pages":"348-351"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80343386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583085
J. Xia, Guoyuan Li, Bin Zhou
The board level vibration reliability of the Package-on-Package (PoP) structure with different underfill types was investigated by finite element method (FEM). Underfill methods used in this study were the full-filled method, the corer-bonded method and the edge-bonded method. Results show that all of them can obviously improve the reliability of PoP structure in random vibration environment. The stress level of the solder joint significantly decreases by the application of underfill materials in the bottom package body of PoP structure. In addition, the location of critical solder joint is different with different underfill types.
{"title":"Analysis of board level vibration reliability of PoP structure with underfill material","authors":"J. Xia, Guoyuan Li, Bin Zhou","doi":"10.1109/ICEPT.2016.7583085","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583085","url":null,"abstract":"The board level vibration reliability of the Package-on-Package (PoP) structure with different underfill types was investigated by finite element method (FEM). Underfill methods used in this study were the full-filled method, the corer-bonded method and the edge-bonded method. Results show that all of them can obviously improve the reliability of PoP structure in random vibration environment. The stress level of the solder joint significantly decreases by the application of underfill materials in the bottom package body of PoP structure. In addition, the location of critical solder joint is different with different underfill types.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"47 1","pages":"37-42"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82364525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583089
Jinfeng Zeng, Hongru Ma, Xun Tian, Yanqing Ma
Electrically conductive adhesive based on epoxy and conductive materials, which have been considered as the new promising material for electronic packaging because of the advantages of low processing temperature, fine pitch interconnect and environmentally friendly. The silver nanoparticle based on graphene have been used in the electrically conductive adhesive as a result of the excellent electrical material. The number of effective conductive paths were improved after doping silver nanoparticle based on graphene into epoxy. So silver nanoparticle based on graphene was prepared in situ hydrothermal method via silver-ammonia solution and graphene oxide as initial solution without other supported reagents. Scanning Electron Microscopy, Transmission Electron Microscopy, X-ray diffraction and Raman spectroscopy were applied to analyze the morphologies and structures of silver nanoparticle based on graphene. Then electrically conductive adhesive was prepared by mixing silver nanoparticle based on graphene, silver flakes and epoxy together. The electrical properties of electrically conductive adhesive were tested by four-point probe method after cured at 150 °C for 2 h. The result shows that silver nanoparticles were dispersed on the surface of graphene layers uniformly and the average diameter of nanosilver particles is 80 nm. The electrical properties of electrically conductive adhesive was 7.0×10-4 Ω·cm when the nanosilver based on graphene reached 0.2 %, which compared with electrically conductive adhesive (1.1×10-3 Ω·cm) without nanosilver based on graphene was improved.
{"title":"In situ hydrothermal synthesis of silver nanoparticle based on graphene and their application for electrically conductive adhesive","authors":"Jinfeng Zeng, Hongru Ma, Xun Tian, Yanqing Ma","doi":"10.1109/ICEPT.2016.7583089","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583089","url":null,"abstract":"Electrically conductive adhesive based on epoxy and conductive materials, which have been considered as the new promising material for electronic packaging because of the advantages of low processing temperature, fine pitch interconnect and environmentally friendly. The silver nanoparticle based on graphene have been used in the electrically conductive adhesive as a result of the excellent electrical material. The number of effective conductive paths were improved after doping silver nanoparticle based on graphene into epoxy. So silver nanoparticle based on graphene was prepared in situ hydrothermal method via silver-ammonia solution and graphene oxide as initial solution without other supported reagents. Scanning Electron Microscopy, Transmission Electron Microscopy, X-ray diffraction and Raman spectroscopy were applied to analyze the morphologies and structures of silver nanoparticle based on graphene. Then electrically conductive adhesive was prepared by mixing silver nanoparticle based on graphene, silver flakes and epoxy together. The electrical properties of electrically conductive adhesive were tested by four-point probe method after cured at 150 °C for 2 h. The result shows that silver nanoparticles were dispersed on the surface of graphene layers uniformly and the average diameter of nanosilver particles is 80 nm. The electrical properties of electrically conductive adhesive was 7.0×10-4 Ω·cm when the nanosilver based on graphene reached 0.2 %, which compared with electrically conductive adhesive (1.1×10-3 Ω·cm) without nanosilver based on graphene was improved.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"1993 1","pages":"57-60"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82389576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583385
Yan Zhang, W. Yue, Shaochun Zhang, Shirong Huang, Johan Liu
Battery packs have been widely used as the power source in many fields, such as pure or hybrid electric vehicles, because of the advantages of high energy density, long cycle life, low self-discharge rate, no memory effect and so on. The heat dissipation is a key issue in the reliability of the batteries, especially for high power applications. Paraffin waxes are commonly used phase change materials in the thermal management of Li-ion battery packs. In order to improve the thermal performance, graphene powders are utilized as additives to increase the thermal conductivity of paraffin waxes. A series of graphene-enhanced paraffin wax samples are prepared, and then the prepared samples are applied to power sources for experimental evaluation. The results show an improved heat dissipation of paraffin waxes with graphene enhancement. Temperature rise in the heat source can be decreased, and the effect is more obvious for higher power case.
{"title":"Experimental investigation of paraffin wax with graphene enhancement as thermal management materials for batteries","authors":"Yan Zhang, W. Yue, Shaochun Zhang, Shirong Huang, Johan Liu","doi":"10.1109/ICEPT.2016.7583385","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583385","url":null,"abstract":"Battery packs have been widely used as the power source in many fields, such as pure or hybrid electric vehicles, because of the advantages of high energy density, long cycle life, low self-discharge rate, no memory effect and so on. The heat dissipation is a key issue in the reliability of the batteries, especially for high power applications. Paraffin waxes are commonly used phase change materials in the thermal management of Li-ion battery packs. In order to improve the thermal performance, graphene powders are utilized as additives to increase the thermal conductivity of paraffin waxes. A series of graphene-enhanced paraffin wax samples are prepared, and then the prepared samples are applied to power sources for experimental evaluation. The results show an improved heat dissipation of paraffin waxes with graphene enhancement. Temperature rise in the heat source can be decreased, and the effect is more obvious for higher power case.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"2006 1","pages":"1401-1405"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82438883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583317
Jinglong Sun, F. Qin, Pei Chen, Tong An, Zhongkang Wang
Rotating grinding is the most commonly used technique in silicon wafer thinning, while it will induce edge chipping as wafer thickness decrease. This will lead to wafer breakage, and thus resulting in cost waste. This study investigates edge chipping of silicon wafers in rotating grinding. The study correlates edge chipping with grinding process parameters, such as wheel rotation speed, wafer rotation speed and wheel feed rate, as well as the crystallographic orientations and thickness of silicon wafer. It identifies the relationship between the edge chipping and the grinding parameters, crystallographic orientations and wafer thickness respectively. In addition, this study discusses the mechanisms of edge chipping based on machining mechanics.
{"title":"Edge chipping of silicon wafers in rotating grinding","authors":"Jinglong Sun, F. Qin, Pei Chen, Tong An, Zhongkang Wang","doi":"10.1109/ICEPT.2016.7583317","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583317","url":null,"abstract":"Rotating grinding is the most commonly used technique in silicon wafer thinning, while it will induce edge chipping as wafer thickness decrease. This will lead to wafer breakage, and thus resulting in cost waste. This study investigates edge chipping of silicon wafers in rotating grinding. The study correlates edge chipping with grinding process parameters, such as wheel rotation speed, wafer rotation speed and wheel feed rate, as well as the crystallographic orientations and thickness of silicon wafer. It identifies the relationship between the edge chipping and the grinding parameters, crystallographic orientations and wafer thickness respectively. In addition, this study discusses the mechanisms of edge chipping based on machining mechanics.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"109 1","pages":"1099-1103"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81767874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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