Micro and Nanostructures最新文献

In this study, by adding Polyethylene-graft-maleic anhydride (PGMA) to the inorganic CsPbI₂Br perovskite film, the coordination bonds and hydrogen bonds between PGMA and CsPbI₂Br cooperate to passivate defects, regulate energy level and stabilize the perovskite structure and eventually improve the device performance. We systematically study the effects of PGMA addition on the morphology, structure, light absorption, defect concentration and carrier lifetime, hydrophobicity, and optical stability and room temperature black phase stability of CsPbI₂Br films, and the photoelectric performance and air stability of PSCs, as well as their mechanism. The experimental results show that the addition of 3 wt% of PGMA greatly improves the photoelectric conversion efficiency (PCE) of CsPbI₂Br PSCs by 40.19 % because of the synergistic passivation effects and energy level tuning. The hydrogen bonds between –CH₂ in PGMA and I⁻/Br⁻ in CsPbI₂Br, along with the coordination of carbonyl groups with Cs⁺/Pb²⁺, improve carrier transport and collection by inactivating flaw and managing the level, reducing the non-radiative recombination losses. In addition, the PSCs with 3 wt% of PGMA maintain 80 % of their initial efficiency even after 600 h in high humidity air environment due to the synergistic effect of coordination bonds and hydrogen bonds. Our study provides valuable insights into the use of PGMA to improve the performance of all-inorganic CsPbI₂Br PSCs and the practicality of perovskite solar cells.

The performance of two-dimensional (2D) monolayer GaN Schottky barrier field effect transistors (SBFETs) with four different metals (Ag, Au, Al, and Pt) as electrodes were studied by using ab initio simulations. The N-type Schottky contact is formed on Ag-GaN, Au-GaN, and Pt-GaN, characterized by electron Schottky barrier heights (SBH) of 0.6, 0.5, and 0.38 eV, respectively. Whereas, Al-GaN contact formed P-type Schottky contact with hole SBH of 1.42 eV. The 5.1 nm GaN SBFETs with four metal electrodes all could overcome the short-channel effect. Additionally, GaN SBFETs with Ag and Au electrodes have excellent performance, whose ON-currents are 1151.1 μA/μm and 1258.9 μA/μm, respectively. They could satisfy the demands of International Technology Roadmap for Semiconductors for high-performance transistor. Furthermore, research indicates that the device's current increases with increasing temperature. Notably, under the constant bias and gate voltage, the current is unaffected by temperature variations between the left and right electrodes.

In order to address and resolve the significant problem of gate-induced drain leakage (GIDL) current and enhance device reliability, band-to-band tunnelling (BTBT), and OFF-state leakages, a computational model of a cylindrical-ferroelectric-dual-metal-nanowire-field effect transistor (C-FE-DM-NW-FET) has been proposed in this manuscript. The proffered structure is a symmetric gate structure with ferroelectric layer sandwiched between the gate terminal and oxide layer which reduces the BTBT which in term reduces the OFF-state leakage hence making the device definitive for low power applications. In this manuscript, there has been a reduction in the leakage current by a magnitude of 10⁴ times in 50 nm and 10⁷ times in 60 nm channel length which translates to a reduction in gate leakage (I_GIDL) of more than 100 % in C-FE-NW-FET over C-NW FET. To analyze the Electric Field, Surface Potential, and I_GIDL with the proper boundary conditions, the 2D Poisson's equation is solved analytically with Landau-Khalatnikov (LK) equation. The analytical findings are quite similar to the simulated outcomes.

In this work, Fourier series-based analytical models for threshold voltage (V_th) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of V_th for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm.

This paper explores the effects of changing the device's parameters, such as the gate length (L_g), nanowire radius (r), oxide thickness (t_ox), and frequency (f), on the noise characteristics of dual material graded channel (DMGC) cylindrical gate all around (CGAA) FET while considering the presence and absence of interface trap charges. The performance analysis of the DMGC CGAA FET with that of the SMGC (single material graded channel) CGAA FET, is carried out while taking into account the impact of trap charges. It's noteworthy that the DMGC FET demonstrates significant advantages, with improvement in I_on/I_off, reduction in DIBL, and SS when compared to the SMGC CGAA FET, both in the cases of without and with traps. The investigation also extends to analyse the analog/RF performance of the DMGC FET, for different type of trap charges. Furthermore, the power spectral densities of current noise (S_id) and voltage noise (S_vg) are examined by varying the device dimensions and temperature. This also addresses the various sources of noise, including flicker noise (1/f), generation-recombination (G-R) noise, and diffusion noise. These types of noise have different prevalence depending on the operating frequency. At low frequencies, flicker and G-R noises dominate, while at higher frequencies, diffusion noise becomes the prominent factor impacting the device's performance. The research findings indicate that the optimal performance of the DMGC CGAA FET is achieved with smaller nanowire radius and thinner oxide thickness, regardless of trap charges. These findings offer valuable insights for improving the design and performance of DMGC CGAA FET in low power applications.

In this work, a new structure of double-channel hybrid anode Schottky barrier diode with dual anode metal (DCH-DM-HAD) was proposed, and the preliminary investigation of the device's electrical characteristic was conducted by using Silvaco TCAD tools. The double-channel hybrid anode diode (DCH-HAD) and single channel hybrid anode diode (SCH-HAD) were compared and it was found that the Ron at lower forward bias is twice as large as the higher bias, which is attributed to different Von of upper channel and lower channel. It can be avoided by setting different metal structures at anode. Besides, the Von decreases with increasing thickness of the barrier layer, but the reverse leakage current increases fast. Finally, the breakdown voltage of three different structures of hybrid anode diodes were compared, and it is found that replacing nickel with tungsten is harder to form uniform electric field due to difference of workfunction of tungsten and nickel. Nonetheless, these kinds of diodes own excellent electrical characteristics.

In this article, a novel SiC superjunction MOSFET with Schottky diode containing N- and P-type barrier is proposed to improving short-circuit and reverse recovery ruggedness, investigated by TCAD simulations. The adoption of superjunction and p-shields structure can reduce saturation current, and thus, improve short-circuit capability. A fine gate oxide providing long-term reliability of the device is obtained. Also, N-type Schottky diode for electrons is used to dampen bipolar conduction of the parasitic body diode, while P-type Schottky diode for holes is introduced to constrain the hole inflow and extraction attributed to the transient variation of the superjunction. As a result, compared with an SBD-wall-integrated trench MOSFET (SWITCH-MOS), a low on-resistance and high breakdown voltage of the proposed structure are gained. More importantly, the proposed device exhibits stronger temperature-dependent immunity. As expected, simulation results indicate that the proposed device under 10 nH stray inductance shows a 30%–50 % reduction in the peak reverse recovery current and a 50%–70 % decrease in the current rising slope of reverse recovery, compared to only a single superjunction, when the metal workfunction varies from 5.1 to 5.6 eV. Moreover, the short-circuit withstanding time of the proposed structure increases roughly 2 times longer than that of SWITCH-MOS.

In this work, the spacer effects (both low and high-k) on the dc and noise characteristics of heterostructure molybdenum ditelluride (MoTe₂/MoSe₂ and MoTe₂/WSe₂) double gate (DG) MOSFET is analyzed. To study the device characteristics, a hybrid methodology that uses both QuantumWise ATK and Sentaurus TCAD tool is used. The performance metrics of the device such as on-current (I_on), I_on/I_off ratio, subthreshold swing (SS), threshold voltage are obtained. The noise performance of the device is also studied (with/without spacer) using impedance field method. Noise parameters such as noise power spectral density (S_ID) and noise figure (function of both frequency and bias) has also been simulated and noise components such as G-R noise, flicker noise and white noise are obtained. The simulation results shows that the introduction of spacer material enhances the dc performance of the device and influences its noise characteristics.

Recent research has focused an extensive amount of attention on the lead-free substance lead-free methylammonium tin(Sn) tri-iodide (MASnI₃), which has emerged as a highly potential absorber layer in the structure of the device. Because it has a larger visible absorption spectrum and a shorter band gap of 1.3 eV than the lead halide perovskite, MASnI₃ is a potential alternative to MAPbX₃. Through numerical simulation, the different parameters on the device performances are fully investigated. We achieved an open-circuit voltage (V_oc) of 0.93 V, a short-circuit current density (J_sc) of 22.20 mA/cm², a fill factor (FF) of 78.81 %, and a power conversion efficiency (PCE) of 16.39 % using the optimised conditions. It demonstrates the huge potential of recently created lead-free perovskite solar cells and opens up a large dimension of opportunities for the creation of novel perovskite solar cells with a variety of photovoltaic applications. The amalgamation of the Tungsten Disulfide (WS₂) material layer between the electron transport layer (ETL) and the absorber layer raised the device module's power conversion efficiency to 20.36 %.

This article presents the design and optimization of GaP/Si heterojunction Fin-TFET with a MoS₂ channel. The elevated fin structure, coupled with ultrathin MoS₂ layers and the tuneable bandgap properties of MoS₂ material, significantly enhances gate control over the channel and improves device performance. Additionally, the GaP/Si heterojunction with a heavily doped n-type source pocket leads to a narrow barrier junction, promoting Band-to-Band Tunneling (BTBT). The optimized Fin-TFET boasts exceptional electrical characteristics: a high ON-current (7.72 × 10⁻⁵ A/μm), an ultra-low OFF-current (4.16 × 10⁻¹⁷ A/μm), and leading to an outstanding I_ON/I_OFF ratio (7.23 × 10¹²). Furthermore, the device demonstrates a steep subthreshold slope (SS) of 6 mV/dec (point) and 16.8 mV/dec (average), alongside impressive analog performance with a transconductance (g_m) of 2.75 × 10⁻⁴ S, a cut-off frequency (f_c) of 1.3 × 10¹² THz, and a gain-bandwidth product (GBP) of 0.17 × 10¹² THz. The entire analysis was conducted utilizing the Sentaurus TCAD-3D simulation tool.