Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543358
Ying Ju, Fule Li, X. Gu, Chun Zhang, Zhihua Wang
A novel digital calibration technique to correct DAC errors from capacitor mismatch is presented in this paper. The jump height of transfer curve is measured for calibration and random interference introducing method helps to improve the measurement accuracy with seldom modification on analog circuits. An 11-bit 250Ms/s subrange ADC based on SAR architecture is designed to test this calibration technique. Simulation results show that significant improvements can be achieved with the proposed calibration technique.
{"title":"Digital calibration technique for subrange ADC based on SAR architecture","authors":"Ying Ju, Fule Li, X. Gu, Chun Zhang, Zhihua Wang","doi":"10.1109/ISNE.2016.7543358","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543358","url":null,"abstract":"A novel digital calibration technique to correct DAC errors from capacitor mismatch is presented in this paper. The jump height of transfer curve is measured for calibration and random interference introducing method helps to improve the measurement accuracy with seldom modification on analog circuits. An 11-bit 250Ms/s subrange ADC based on SAR architecture is designed to test this calibration technique. Simulation results show that significant improvements can be achieved with the proposed calibration technique.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124186219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543354
Van Kien Nguyen, Yo‐Sheng Lin, Chien-Chin Wang, M. H. Kao, Yu-Ching Lin
A 88 to 98 GHz broadband power amplifier (PA) using the low-cost 90 nm CMOS process technology is designed. The positive feedback of common-source (CS) configuration and Y-shaped power divider and combine are employed to improve performance of the PA. The proposed PA exhibits a simulated saturated output power (PSAT) of 17 dBm, output-referred 1 dB compression point (OP1dB) of 15.2 dBm, power added efficiency (PAE) of 16.4%, and gain of 20.4dB at 94 GHz. In addition, the input and output reflection coefficients is below -10dB at 94 GHz. Simulated results show that the methods applied to this PA can effectively improve gain, OP1dB and PAE of the PA.
{"title":"A 88–98 GHz power amplifier in 90 nm CMOS","authors":"Van Kien Nguyen, Yo‐Sheng Lin, Chien-Chin Wang, M. H. Kao, Yu-Ching Lin","doi":"10.1109/ISNE.2016.7543354","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543354","url":null,"abstract":"A 88 to 98 GHz broadband power amplifier (PA) using the low-cost 90 nm CMOS process technology is designed. The positive feedback of common-source (CS) configuration and Y-shaped power divider and combine are employed to improve performance of the PA. The proposed PA exhibits a simulated saturated output power (PSAT) of 17 dBm, output-referred 1 dB compression point (OP1dB) of 15.2 dBm, power added efficiency (PAE) of 16.4%, and gain of 20.4dB at 94 GHz. In addition, the input and output reflection coefficients is below -10dB at 94 GHz. Simulated results show that the methods applied to this PA can effectively improve gain, OP1dB and PAE of the PA.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126596281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543285
Xu Jin, Huapeng Xiao, Dong Wu, Ning Deng, Huaqiang Wu, Kanyu Cao, H. Qian
As more and more demand on high density storage, 3D NAND Flash memories have developed into multi-level cell and triple-level cell. With the charge-trapping technology adopted in 3D NAND Flash, it is possible to achieve quadruple-level-cell (QLC) which brings higher density capability. Meanwhile, the program coding method makes significant impact on the efficiency of the lockout operation in the program verification. A novel speed-up coding method is presented in this paper, which reduces nearly 30% time delay and 40% power consumption during the verify lockout operation in the QLC memory.
{"title":"A novel speed-up coding method in quadruple-level-cell 3D NAND flash memory","authors":"Xu Jin, Huapeng Xiao, Dong Wu, Ning Deng, Huaqiang Wu, Kanyu Cao, H. Qian","doi":"10.1109/ISNE.2016.7543285","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543285","url":null,"abstract":"As more and more demand on high density storage, 3D NAND Flash memories have developed into multi-level cell and triple-level cell. With the charge-trapping technology adopted in 3D NAND Flash, it is possible to achieve quadruple-level-cell (QLC) which brings higher density capability. Meanwhile, the program coding method makes significant impact on the efficiency of the lockout operation in the program verification. A novel speed-up coding method is presented in this paper, which reduces nearly 30% time delay and 40% power consumption during the verify lockout operation in the QLC memory.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"63 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131126790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543359
Keng-Hong Chu, Tse-An Chen, Chia-Ling Wei
A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.
{"title":"A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits","authors":"Keng-Hong Chu, Tse-An Chen, Chia-Ling Wei","doi":"10.1109/ISNE.2016.7543359","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543359","url":null,"abstract":"A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115159693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543363
Ming-Hsuan Hsu, Chun-Hua Cheng, Shih-Hsu Huang
As the design complexity increases, three-dimensional (3D) integrated circuit (IC) design has become an industry trend. However, the testing of a 3D IC is a design challenge. In addition to minimize the test application time (including pre-bond testing and post-bond testing), the number of test pads of each layer should also be taken into account. In this paper, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling with test pads considered. Different from those previous works, our objective is to minimize the weighted sum of the test application time and the number of required test pads. Experimental results consistently show that our approach works well in practice.
{"title":"3D IC test scheduling with test pads considered","authors":"Ming-Hsuan Hsu, Chun-Hua Cheng, Shih-Hsu Huang","doi":"10.1109/ISNE.2016.7543363","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543363","url":null,"abstract":"As the design complexity increases, three-dimensional (3D) integrated circuit (IC) design has become an industry trend. However, the testing of a 3D IC is a design challenge. In addition to minimize the test application time (including pre-bond testing and post-bond testing), the number of test pads of each layer should also be taken into account. In this paper, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling with test pads considered. Different from those previous works, our objective is to minimize the weighted sum of the test application time and the number of required test pads. Experimental results consistently show that our approach works well in practice.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"49 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543390
Shih‐Kun Liu, Yong-Jai Shen, Wei-Yi Sung, Hong-Zhang Lin
In this study, a fiber optical tweezer is successful integrated for trapping polystyrene particles at the wavelength of 650 nm. The experimental results show that the optimal trapping efficiency of 4.3% occurs at the working distance of 26 μm.
{"title":"Working distance dependence of trapping efficiency in fiber optical tweezers","authors":"Shih‐Kun Liu, Yong-Jai Shen, Wei-Yi Sung, Hong-Zhang Lin","doi":"10.1109/ISNE.2016.7543390","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543390","url":null,"abstract":"In this study, a fiber optical tweezer is successful integrated for trapping polystyrene particles at the wavelength of 650 nm. The experimental results show that the optimal trapping efficiency of 4.3% occurs at the working distance of 26 μm.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116117142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543278
Shi-Jun Liu, Wei-Lin Wang, Yue-Yin Yen, C. Hsu, Hung-Ju Chien, Kuo-Tzu Peng, M. Yeh, Hsien-Chang Kuo, T. Ying
In Cu interconnects, the disadvantage of physical vapor deposited (PVD) Cu seed is the formation of over-hang on patterned trench. Ar plasma treatment (PT) is utilized to diminish undesirable over-hang profile after the deposition of Cu seed. Moreover, Ar PT improves the surface roughness of Cu seed and enhances the (111) texture of the subsequent electroplated Cu film. By applying Ar PT method, the defects of Cu interconnects have 73% reduction in improvement.
{"title":"The defect reduction of Cu interconnects by optimized Cu seed layer","authors":"Shi-Jun Liu, Wei-Lin Wang, Yue-Yin Yen, C. Hsu, Hung-Ju Chien, Kuo-Tzu Peng, M. Yeh, Hsien-Chang Kuo, T. Ying","doi":"10.1109/ISNE.2016.7543278","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543278","url":null,"abstract":"In Cu interconnects, the disadvantage of physical vapor deposited (PVD) Cu seed is the formation of over-hang on patterned trench. Ar plasma treatment (PT) is utilized to diminish undesirable over-hang profile after the deposition of Cu seed. Moreover, Ar PT improves the surface roughness of Cu seed and enhances the (111) texture of the subsequent electroplated Cu film. By applying Ar PT method, the defects of Cu interconnects have 73% reduction in improvement.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116147048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optical, electrical and surface morphological properties of nickel oxide (NiOx)/recessed indium tin oxide (ITO) films were examined to realize their suitability for serving as an anode of OLEDs. Results showed that adding a top NiOx layer allows recessed ITO to exhibit slightly higher optical effects but degraded its electrical conductance. Due to the largely elevated surface work function with this NiOx interlayer recessed OLED exhibited improved current efficiency.
{"title":"Preparation of nickel oxide on recessed ITO anodes for OLED applications","authors":"Wen-Tuan Wu, Ching-Ming Hsu, Wei-Ming Lin, Don-Han Tsai, U-Jin Peng","doi":"10.1109/ISNE.2016.7543387","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543387","url":null,"abstract":"Optical, electrical and surface morphological properties of nickel oxide (NiOx)/recessed indium tin oxide (ITO) films were examined to realize their suitability for serving as an anode of OLEDs. Results showed that adding a top NiOx layer allows recessed ITO to exhibit slightly higher optical effects but degraded its electrical conductance. Due to the largely elevated surface work function with this NiOx interlayer recessed OLED exhibited improved current efficiency.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122881685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543373
W. Lai, M. Chung
This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator and low noise amplifier (LNA) with data-weighted average (DWA) technology. A new image-reject low noise amplifier is designed for ECG communication and bio-signal wireless acquisitions. An inter-stage T-structure filter is used in the low noise amplifier design to provide 35-dB image rejection. The DWA technique is used for reducing DAC noise due to component mismatches. Experimental results show the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply, which can be used for electroencephalogram (EEG) or electrocardiogram (ECG) signal acquisition systems by wireless sensor and communication. This provided sensor setup CO2 concentration detecting instruments on chip. Oxygen generator will real time to support when sensor monitor and wireless send bio-signal to doctor or health cloud.
{"title":"Integrated continuous-time Sigma-Delta Modulator and low noise amplifier for tracheostomy tube wireless application","authors":"W. Lai, M. Chung","doi":"10.1109/ISNE.2016.7543373","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543373","url":null,"abstract":"This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator and low noise amplifier (LNA) with data-weighted average (DWA) technology. A new image-reject low noise amplifier is designed for ECG communication and bio-signal wireless acquisitions. An inter-stage T-structure filter is used in the low noise amplifier design to provide 35-dB image rejection. The DWA technique is used for reducing DAC noise due to component mismatches. Experimental results show the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply, which can be used for electroencephalogram (EEG) or electrocardiogram (ECG) signal acquisition systems by wireless sensor and communication. This provided sensor setup CO2 concentration detecting instruments on chip. Oxygen generator will real time to support when sensor monitor and wireless send bio-signal to doctor or health cloud.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122681836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543369
Chang-Han Yeh, Chun-Hua Cheng, Shih-Hsu Huang
With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.
{"title":"Grouping and placement of memory BIST controllers for test application time minimization","authors":"Chang-Han Yeh, Chun-Hua Cheng, Shih-Hsu Huang","doi":"10.1109/ISNE.2016.7543369","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543369","url":null,"abstract":"With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：