Interface trap density and doping density of grounded body SOI (GBSOI) nMOSFET were analysed by charge pumping current and subthreshold swing measurements. Especially, measurements for D/sub it/ and N/sub A/ of the sidewall channel inducing current leakage were managed. If the subthreshold regions of the main and sidewall channels are separated, D/sub it/ and N/sub A/ of the sidewall channel may be extracted by the differential subthreshold slope measurement with varing SOI body potential. D/sub it/ and N/sub A/ of the sidewall channel were about 1.6/spl times/10/sup 11/ eV/sup -1/ cm/sup -2/ and 7/spl times/10/sup 14/ cm/sup -3/ respectively. These values are an order of magnitude larger and smaller than those of the main channel.
{"title":"Analyses on the interface trap density and doping density of grounded-body SOI (GBSOI) nMOSFET","authors":"Jong-Son Lyu, W. Kang, H. J. Yoo","doi":"10.1109/SOI.1995.526471","DOIUrl":"https://doi.org/10.1109/SOI.1995.526471","url":null,"abstract":"Interface trap density and doping density of grounded body SOI (GBSOI) nMOSFET were analysed by charge pumping current and subthreshold swing measurements. Especially, measurements for D/sub it/ and N/sub A/ of the sidewall channel inducing current leakage were managed. If the subthreshold regions of the main and sidewall channels are separated, D/sub it/ and N/sub A/ of the sidewall channel may be extracted by the differential subthreshold slope measurement with varing SOI body potential. D/sub it/ and N/sub A/ of the sidewall channel were about 1.6/spl times/10/sup 11/ eV/sup -1/ cm/sup -2/ and 7/spl times/10/sup 14/ cm/sup -3/ respectively. These values are an order of magnitude larger and smaller than those of the main channel.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128636277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The operation of SOI devices is limited by self-heating phenomena (SH) due to the low thermal conductivity of the buried oxide. Although much research has been carried out in this field, only recently a SH small signal model has been established versus temperature. However, no detailed analysis of the impact of SH effects on the design of SOI devices has been worked out as a function of temperature. The aim of this paper is first to confirm the previous model by comparing extracted oxide thermal conductivity experimentally measured on fused silica, and, second to evaluate the SH impact on SOI device operation versus temperature.
{"title":"Impact of self-heating effects on the design of SOI devices versus temperature","authors":"J. Jomaah, G. Ghibaudo, F. Balestra, J. Pelloie","doi":"10.1109/SOI.1995.526487","DOIUrl":"https://doi.org/10.1109/SOI.1995.526487","url":null,"abstract":"The operation of SOI devices is limited by self-heating phenomena (SH) due to the low thermal conductivity of the buried oxide. Although much research has been carried out in this field, only recently a SH small signal model has been established versus temperature. However, no detailed analysis of the impact of SH effects on the design of SOI devices has been worked out as a function of temperature. The aim of this paper is first to confirm the previous model by comparing extracted oxide thermal conductivity experimentally measured on fused silica, and, second to evaluate the SH impact on SOI device operation versus temperature.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128569748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Shin, I. Lim, M. Racanelli, W.M. Huang, J. Foerstner, B. Hwang, J. Whitfield, H. Shin, T. Wetteroth, S. Hong, S. Wilson, S. Cheng
The floating-body configuration in SOI devices is desirable because of area efficiency and parasitics reduction. It has been predicted recently that there exists a dynamic floating-body effect in partially depleted SOI devices, which can lead to transient currents during device turn-on/off. This paper presents the observed current transients due to the dynamic floating body effects. The transient behaviors are analyzed and device simulation was done to confirm our analysis.
{"title":"Transient behaviors in partially depleted thin film SOI devices","authors":"H. Shin, I. Lim, M. Racanelli, W.M. Huang, J. Foerstner, B. Hwang, J. Whitfield, H. Shin, T. Wetteroth, S. Hong, S. Wilson, S. Cheng","doi":"10.1109/SOI.1995.526432","DOIUrl":"https://doi.org/10.1109/SOI.1995.526432","url":null,"abstract":"The floating-body configuration in SOI devices is desirable because of area efficiency and parasitics reduction. It has been predicted recently that there exists a dynamic floating-body effect in partially depleted SOI devices, which can lead to transient currents during device turn-on/off. This paper presents the observed current transients due to the dynamic floating body effects. The transient behaviors are analyzed and device simulation was done to confirm our analysis.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126706539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An extremely low dose (5E16 cm/sup -2/) of nitrogen ions has been implanted at very low implant energy (25 keV) into silicon to produce ultra thin SOI wafers with a buried layer of silicon oxy-nitride as thin as 43nm and a top silicon layer as thin as 35 nm after high temperature annealing. Such a low dose significantly reduces the implant time which increases the thruput, produces less damage to the silicon which leads to lower defect densities and decreases contamination. This process is very attractive for high volume manufacturing of SOI at a much lower cost compared with SIMOX. This material will be suitable for ULSI CMOS applications where the thickness of the SOI and buried layers are to be 50 nm each. The described method has to be optimized to obtain device quality SOI material.
{"title":"Ultra thin SOI material by implantation of nitrogen and diffusion of oxygen to form a buried layer of silicon oxy-nitride","authors":"N. Meyyappan, T. Nakato, H. Takeuchi","doi":"10.1109/SOI.1995.526511","DOIUrl":"https://doi.org/10.1109/SOI.1995.526511","url":null,"abstract":"An extremely low dose (5E16 cm/sup -2/) of nitrogen ions has been implanted at very low implant energy (25 keV) into silicon to produce ultra thin SOI wafers with a buried layer of silicon oxy-nitride as thin as 43nm and a top silicon layer as thin as 35 nm after high temperature annealing. Such a low dose significantly reduces the implant time which increases the thruput, produces less damage to the silicon which leads to lower defect densities and decreases contamination. This process is very attractive for high volume manufacturing of SOI at a much lower cost compared with SIMOX. This material will be suitable for ULSI CMOS applications where the thickness of the SOI and buried layers are to be 50 nm each. The described method has to be optimized to obtain device quality SOI material.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122174127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SOI technology is a prime candidate for replacing bulk Si in low-power VLSI CMOS applications. One of the most advanced SOI technologies is SIMOX. One potential problem with SIMOX SOI substrates is the intrinsic low-field conduction through the buried oxide (BOX), which is to be distinguished from defect-related "piping" current. Intrinsic low-level current, summed up over a very large chip area, could add up to a significant leakage component. In addition, low-level leakage poses a long-term reliability problem due to the potential for BOX charge trapping. Thus, a fundamental understanding of this low-field conduction is necessary in order to provide insight about the physical properties of the SIMOX BOX responsible for this current. In this paper, we present one of the first comprehensive studies of the electric-field, temperature, and time dependence of intrinsic low-level SIMOX BOX conduction characteristics for both single and multiple implant substrates. Based on the observed power-law time dependence, we believe that the low-level conduction is due to electron detrapping from pre-existing traps. The effect of Fowler-Nordheim (F-N) stress on low-field leakage is also examined. It was found that high-field stress can fill traps within the BOX which can then easily detrap at room temperature.
{"title":"Intrinsic low-field conduction in SIMOX buried oxides","authors":"J. Yap, J. E. Chung","doi":"10.1109/SOI.1995.526504","DOIUrl":"https://doi.org/10.1109/SOI.1995.526504","url":null,"abstract":"SOI technology is a prime candidate for replacing bulk Si in low-power VLSI CMOS applications. One of the most advanced SOI technologies is SIMOX. One potential problem with SIMOX SOI substrates is the intrinsic low-field conduction through the buried oxide (BOX), which is to be distinguished from defect-related \"piping\" current. Intrinsic low-level current, summed up over a very large chip area, could add up to a significant leakage component. In addition, low-level leakage poses a long-term reliability problem due to the potential for BOX charge trapping. Thus, a fundamental understanding of this low-field conduction is necessary in order to provide insight about the physical properties of the SIMOX BOX responsible for this current. In this paper, we present one of the first comprehensive studies of the electric-field, temperature, and time dependence of intrinsic low-level SIMOX BOX conduction characteristics for both single and multiple implant substrates. Based on the observed power-law time dependence, we believe that the low-level conduction is due to electron detrapping from pre-existing traps. The effect of Fowler-Nordheim (F-N) stress on low-field leakage is also examined. It was found that high-field stress can fill traps within the BOX which can then easily detrap at room temperature.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123825271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Analysis of the electrical performance of SIMOX BOX require studies of both types of this material, standard dose and low dose. Electrical characterization techniques used for thermal and deposited oxides are applicable to SIMOX. Device structures, while providing a wide range of characteristics of the BOX, require sequences of fabrication steps to precede the measurements. In the material development environment, a fast method of evaluation of the properties of the material is of special value. In this paper, we will show the analyses of the SIMOX BOX leakage characteristics by direct measurements based on copper sulfate electrolytic contact.
{"title":"Analysis of SIMOX buried oxide leakage by direct measurements","authors":"M. Anc, W. Krull","doi":"10.1109/SOI.1995.526466","DOIUrl":"https://doi.org/10.1109/SOI.1995.526466","url":null,"abstract":"Analysis of the electrical performance of SIMOX BOX require studies of both types of this material, standard dose and low dose. Electrical characterization techniques used for thermal and deposited oxides are applicable to SIMOX. Device structures, while providing a wide range of characteristics of the BOX, require sequences of fabrication steps to precede the measurements. In the material development environment, a fast method of evaluation of the properties of the material is of special value. In this paper, we will show the analyses of the SIMOX BOX leakage characteristics by direct measurements based on copper sulfate electrolytic contact.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131764321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The cell pitch of high voltage lateral power devices determines many important device performance specifications such as the area of the chip, on-state voltage drop and the maximum controllable current. Since the cell pitch of lateral power devices is determined by the long drift region lengths required to support high voltages in accordance with the RESURF principle, it is desirable to have a uniform lateral electric field distribution in the drift region to minimize the drift region length for a device with a given breakdown voltage. It is generally assumed that the breakdown voltage of DI RESURF devices scales up linearly with increasing drift region length till a limit associated with vertical breakdown is reached. However, 2D numerical simulations of the breakdown of DI PIN diodes indicate non-ideal electric field distribution in the drift region. Two techniques have been studied for achieving a more uniform electric field distribution in the drift region for DI lateral power devices. One technique involves the use of a SIPOS field plate over the drift region to spread the electric field uniformly. The other technique involves tailoring the drift region doping profile, so that the drift region charge increases linearly from the anode end to the cathode end.
{"title":"Step drift doping profile for high voltage DI lateral power devices","authors":"R. Sunkavalli, A. Tamba, B. J. Baliga","doi":"10.1109/SOI.1995.526499","DOIUrl":"https://doi.org/10.1109/SOI.1995.526499","url":null,"abstract":"The cell pitch of high voltage lateral power devices determines many important device performance specifications such as the area of the chip, on-state voltage drop and the maximum controllable current. Since the cell pitch of lateral power devices is determined by the long drift region lengths required to support high voltages in accordance with the RESURF principle, it is desirable to have a uniform lateral electric field distribution in the drift region to minimize the drift region length for a device with a given breakdown voltage. It is generally assumed that the breakdown voltage of DI RESURF devices scales up linearly with increasing drift region length till a limit associated with vertical breakdown is reached. However, 2D numerical simulations of the breakdown of DI PIN diodes indicate non-ideal electric field distribution in the drift region. Two techniques have been studied for achieving a more uniform electric field distribution in the drift region for DI lateral power devices. One technique involves the use of a SIPOS field plate over the drift region to spread the electric field uniformly. The other technique involves tailoring the drift region doping profile, so that the drift region charge increases linearly from the anode end to the cathode end.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132504688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
CMP has been applied to SOI mesa isolation, with good results. Electrical leakage is comparable to that seen on mesa sidewall isolated structures, and there is no indication of contamination or mechanical damage to the transistors. In addition to the individual transistor data, we measured fully operational inverter chains having 640 stages. The yield of these inverter chains is comparable to that of sidewall isolated structures. This is further indication of the viability of the CMP planarization process at isolation. Further work is needed to optimize CMP conditions for isolation, but all indications to date are that it is a viable process for planarization.
{"title":"Novel mesa isolation using CMP for planarization of 0.35/0.25 um SOI","authors":"K. Joyner, I. Ali, R. Rajgopal, T. Houston","doi":"10.1109/SOI.1995.526485","DOIUrl":"https://doi.org/10.1109/SOI.1995.526485","url":null,"abstract":"CMP has been applied to SOI mesa isolation, with good results. Electrical leakage is comparable to that seen on mesa sidewall isolated structures, and there is no indication of contamination or mechanical damage to the transistors. In addition to the individual transistor data, we measured fully operational inverter chains having 640 stages. The yield of these inverter chains is comparable to that of sidewall isolated structures. This is further indication of the viability of the CMP planarization process at isolation. Further work is needed to optimize CMP conditions for isolation, but all indications to date are that it is a viable process for planarization.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129434903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hyoungsub Kim, Jeong-Seok Kim, D. Choi, Gon-sub Lee, Do-Hyung Kim, Kyupil Lee, Kinam Kim, Jong-Woo Park
One of the most important parameters in an SOI-DRAM process is to maintain an excellent gate oxide integrity. Recently, many papers related to microdefects in a SIMOX wafer itself, which cause gate oxide failure, have been reported. However, little study on process induced defects in real device fabrication, especially high density DRAMs, has been done. We find a crucial issue in SOI-DRAM on a SIMOX substrate is a high dose implantation-induced-defect generation (IIDG) during source/drain (S/D) implantation. We propose that a reduced S/D implantation dose is a key factor to achieve a high density DRAM and a possible mechanism for the IIDG in a SIMOX wafer is also discussed.
{"title":"Implantation-induced-defect generation during device fabrication on a SIMOX substrate","authors":"Hyoungsub Kim, Jeong-Seok Kim, D. Choi, Gon-sub Lee, Do-Hyung Kim, Kyupil Lee, Kinam Kim, Jong-Woo Park","doi":"10.1109/SOI.1995.526508","DOIUrl":"https://doi.org/10.1109/SOI.1995.526508","url":null,"abstract":"One of the most important parameters in an SOI-DRAM process is to maintain an excellent gate oxide integrity. Recently, many papers related to microdefects in a SIMOX wafer itself, which cause gate oxide failure, have been reported. However, little study on process induced defects in real device fabrication, especially high density DRAMs, has been done. We find a crucial issue in SOI-DRAM on a SIMOX substrate is a high dose implantation-induced-defect generation (IIDG) during source/drain (S/D) implantation. We propose that a reduced S/D implantation dose is a key factor to achieve a high density DRAM and a possible mechanism for the IIDG in a SIMOX wafer is also discussed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129820634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
If the dimensions of a semiconductor sample are reduced sufficiently, low-dimensionality effects involving quantization effects start to appear. These effects manifest themselves in the form of conductance oscillations. They appear at nanometer-scale dimensions at room temperature. However, it is possible to observe quantization effects in 100-nm-scale devices when the temperature is reduced sufficiently. In this paper measurements and simulations have been applied to SOI quantum wire MOSFETs.
{"title":"Quantum-wire effects in thin and narrow SOI MOSFETs","authors":"X. Baie, J. Colinge, V. Bayot, E. Grivei","doi":"10.1109/SOI.1995.526463","DOIUrl":"https://doi.org/10.1109/SOI.1995.526463","url":null,"abstract":"If the dimensions of a semiconductor sample are reduced sufficiently, low-dimensionality effects involving quantization effects start to appear. These effects manifest themselves in the form of conductance oscillations. They appear at nanometer-scale dimensions at room temperature. However, it is possible to observe quantization effects in 100-nm-scale devices when the temperature is reduced sufficiently. In this paper measurements and simulations have been applied to SOI quantum wire MOSFETs.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132527878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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