Because BJT currents are highly temperature sensitive, self-heating is very important in analog BJT circuits. Dielectrically isolated BJTs (DIBJTs) typically have thermal resistance R/sub TH/ three or more times higher than their bulk counterparts. Circuit simulators are readily modified to account for such effects, but characterizing thermal effects in DIBJTs is rather difficult: self-heating complicates extraction of the temperature dependences and R/sub TH/, and models that predict R/sub TH/ in bulk BJTs do not apply for SOI because of the more complicated boundary conditions. This paper describes a scalable model for R/sub TH/ in vertical DIBJTs, along with a technique for extracting R/sub TH/ in BJTs. The modeled measurements are shown to agree quite well.
{"title":"A physical thermal resistance model for vertical BJTs on SOI","authors":"D. T. Zweidinger, J. Brodsky, R. Fox","doi":"10.1109/SOI.1995.526472","DOIUrl":"https://doi.org/10.1109/SOI.1995.526472","url":null,"abstract":"Because BJT currents are highly temperature sensitive, self-heating is very important in analog BJT circuits. Dielectrically isolated BJTs (DIBJTs) typically have thermal resistance R/sub TH/ three or more times higher than their bulk counterparts. Circuit simulators are readily modified to account for such effects, but characterizing thermal effects in DIBJTs is rather difficult: self-heating complicates extraction of the temperature dependences and R/sub TH/, and models that predict R/sub TH/ in bulk BJTs do not apply for SOI because of the more complicated boundary conditions. This paper describes a scalable model for R/sub TH/ in vertical DIBJTs, along with a technique for extracting R/sub TH/ in BJTs. The modeled measurements are shown to agree quite well.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127924446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Lukvanchikova, M. Petrichuk, M. Garbar, E. Simoen, C. Claeys
Noise spectroscopy of levels is known to be a high-sensitive method for detection of defects, determination of their parameters and elucidation of their nature. This method is based on the analysis of generation-recombination noise that accompanies the processes of charge carrier capture and release on different centers in a semiconductor material or device. The purpose of this paper is to demonstrate the efficiency of the application of low-frequency noise methods for characterization of thin film fully-depleted accumulation mode SOI pMOSFETs.
{"title":"Results on noise examination of fully-depleted accumulation mode SOI pMOSFETs","authors":"N. Lukvanchikova, M. Petrichuk, M. Garbar, E. Simoen, C. Claeys","doi":"10.1109/SOI.1995.526448","DOIUrl":"https://doi.org/10.1109/SOI.1995.526448","url":null,"abstract":"Noise spectroscopy of levels is known to be a high-sensitive method for detection of defects, determination of their parameters and elucidation of their nature. This method is based on the analysis of generation-recombination noise that accompanies the processes of charge carrier capture and release on different centers in a semiconductor material or device. The purpose of this paper is to demonstrate the efficiency of the application of low-frequency noise methods for characterization of thin film fully-depleted accumulation mode SOI pMOSFETs.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128081048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper reports the sidewall-related narrow channel effect in mesa-isolated fully-depleted ultra-thin SOI inversion-type and accumulation-type PMOS devices. Based on the study, contrary to inversion-type devices, the threshold voltage of mesa-isolated ultra-thin SOI accumulation-type PMOS devices shrinks as the channel width scales down as a result of the buried-channel effect influenced by the sidewall via the buried oxide.
{"title":"Accumulation-type vs. inversion-type: narrow channel effect in VLSI mesa-isolated fully-depleted ultra-thin SOI PMOS devices","authors":"K. Su, J. Kuo","doi":"10.1109/SOI.1995.526449","DOIUrl":"https://doi.org/10.1109/SOI.1995.526449","url":null,"abstract":"The paper reports the sidewall-related narrow channel effect in mesa-isolated fully-depleted ultra-thin SOI inversion-type and accumulation-type PMOS devices. Based on the study, contrary to inversion-type devices, the threshold voltage of mesa-isolated ultra-thin SOI accumulation-type PMOS devices shrinks as the channel width scales down as a result of the buried-channel effect influenced by the sidewall via the buried oxide.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128333155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Maszara, D. Boyko, A. Caviglia, G. Goetz, J. B. Mckitterick, J. O'connor
A 28 volt solenoid driver has been realized in partially-depleted SOI CMOS technology. The design features an n-channel high voltage MOSFET with an extended drain and a polysilicon field plate, and an on-board flyback diode, each capable of sinking 0.5 A of current and dissipating about 1 W of DC power. Pulse-width modulation (PWM) control maintains low dynamic power dissipation in the drive FET, while the externally selectable "pull-in and hold" function, which reduces the maximum operating current, helps to minimize the overall chip power. Saturation detection, current sense, and overcurrent fault outputs are provided to assist the system designer. The device was fabricated on SIMOX wafers with 340 nm of Si film using our 1.25 /spl mu/m CMOS SOI process with single level Ti/W interconnects and CoSi/sub 2/ contacts. Our Ti/W metallization, capped with Si/sub 3/N/sub 4/ for corrosion protection, has been evaluated to have a lifetime of /spl sim/16.7 years for 300/spl deg/C operation at 10/sup 6/ A/cm/sup 2/ (a 10% resistance increase was the definition of failure). The output power transistor has been formed with our standard CMOS process. Its gate dimensions were L=2 /spl mu/m and W=48,000 /spl mu/m, with a drain extension of 2.8 /spl mu/m.
{"title":"Smart-power solenoid driver for 300/spl deg/C operation","authors":"W. Maszara, D. Boyko, A. Caviglia, G. Goetz, J. B. Mckitterick, J. O'connor","doi":"10.1109/SOI.1995.526495","DOIUrl":"https://doi.org/10.1109/SOI.1995.526495","url":null,"abstract":"A 28 volt solenoid driver has been realized in partially-depleted SOI CMOS technology. The design features an n-channel high voltage MOSFET with an extended drain and a polysilicon field plate, and an on-board flyback diode, each capable of sinking 0.5 A of current and dissipating about 1 W of DC power. Pulse-width modulation (PWM) control maintains low dynamic power dissipation in the drive FET, while the externally selectable \"pull-in and hold\" function, which reduces the maximum operating current, helps to minimize the overall chip power. Saturation detection, current sense, and overcurrent fault outputs are provided to assist the system designer. The device was fabricated on SIMOX wafers with 340 nm of Si film using our 1.25 /spl mu/m CMOS SOI process with single level Ti/W interconnects and CoSi/sub 2/ contacts. Our Ti/W metallization, capped with Si/sub 3/N/sub 4/ for corrosion protection, has been evaluated to have a lifetime of /spl sim/16.7 years for 300/spl deg/C operation at 10/sup 6/ A/cm/sup 2/ (a 10% resistance increase was the definition of failure). The output power transistor has been formed with our standard CMOS process. Its gate dimensions were L=2 /spl mu/m and W=48,000 /spl mu/m, with a drain extension of 2.8 /spl mu/m.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129227293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Yallup, R. Wilson, C. Quinn, B. McDonnell, S. Blackstone
Tungsten silicide is a well know material used widely in the semiconductor industry, particularly for reducing the conductivity of polysilicon layers. A similar concept has been proposed for the reduction of buried layer resistance in bipolar and smart power circuits. This paper examines in detail the stability of a buried CVD WSi/sub x/ SOI structure and discusses the silicon microstructure as a function of temperature and doping of the layer, SIMS analysis of the silicon layer on top of the silicide layer, and etchability of the silicide layer. It is found that the silicide layer is stable to high temperature and remains intact. In addition it is shown that the SOI layer is not contaminated by the silicide layer. Electrical contact between the silicide layer is also established. Finally a trench etch process is presented which can pattern the film in a single step.
{"title":"Buried WSi/sub x/ SOI structures","authors":"K. Yallup, R. Wilson, C. Quinn, B. McDonnell, S. Blackstone","doi":"10.1109/SOI.1995.526498","DOIUrl":"https://doi.org/10.1109/SOI.1995.526498","url":null,"abstract":"Tungsten silicide is a well know material used widely in the semiconductor industry, particularly for reducing the conductivity of polysilicon layers. A similar concept has been proposed for the reduction of buried layer resistance in bipolar and smart power circuits. This paper examines in detail the stability of a buried CVD WSi/sub x/ SOI structure and discusses the silicon microstructure as a function of temperature and doping of the layer, SIMS analysis of the silicon layer on top of the silicide layer, and etchability of the silicide layer. It is found that the silicide layer is stable to high temperature and remains intact. In addition it is shown that the SOI layer is not contaminated by the silicide layer. Electrical contact between the silicide layer is also established. Finally a trench etch process is presented which can pattern the film in a single step.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125550209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper it is successfully demonstrated that Ta-gate SOI MOSFETs have excellent threshold voltage control in 1V applications.
本文成功地证明了ta栅极SOI mosfet在1V应用中具有优异的阈值电压控制。
{"title":"Tantalum-gate SOI MOSFET's featuring excellent threshold voltage control in low-power applications","authors":"H. Shimada, T. Ushiki, Y. Hirano, T. Ohmi","doi":"10.1109/SOI.1995.526478","DOIUrl":"https://doi.org/10.1109/SOI.1995.526478","url":null,"abstract":"In this paper it is successfully demonstrated that Ta-gate SOI MOSFETs have excellent threshold voltage control in 1V applications.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116536789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate oxides grown on SIMOX wafers contain defects originating from the substrate. The defect-induced traps may cause a threshold voltage instability problem for SOI MOSFET devices as well as gate oxide reliability degradation. Therefore it is essential to study the effect of traps on gate oxide quality with SOI substrates. In this paper, different trap behavior near different electrodes is presented. We find that there are high density positive-charged traps near the poly gate electrode. In addition to the rough poly/Si0/sub 2/ interface, the existence of a high density of positive traps close to the poly/SiO/sub 2/ interface could further degrade the gate oxide reliability for gate injection polarity with SOI wafers.
{"title":"Polarity dependence of gate oxide quality with SOI substrates","authors":"H. Tseng, P. Tobin, S. Hong","doi":"10.1109/SOI.1995.526458","DOIUrl":"https://doi.org/10.1109/SOI.1995.526458","url":null,"abstract":"Gate oxides grown on SIMOX wafers contain defects originating from the substrate. The defect-induced traps may cause a threshold voltage instability problem for SOI MOSFET devices as well as gate oxide reliability degradation. Therefore it is essential to study the effect of traps on gate oxide quality with SOI substrates. In this paper, different trap behavior near different electrodes is presented. We find that there are high density positive-charged traps near the poly gate electrode. In addition to the rough poly/Si0/sub 2/ interface, the existence of a high density of positive traps close to the poly/SiO/sub 2/ interface could further degrade the gate oxide reliability for gate injection polarity with SOI wafers.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121388730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The analysis of hot-carrier induced degradation of SOI/MOSFETs is a complicated problem due to the dual channel and front-back coupling effect. Opinions vary as to whether hot-carrier stress of the front (or back) channel results in damage of the opposite channel. Most of the previous studies have used channel current or transconductance as the monitor of hot-carrier induced degradation in SOI/MOSFETs, which often does not allow clear separation between interface-trap generation and charge trapping at both interfaces. In this paper, by systematically examining the charge-pumping currents, junction recombination currents, static I/sub d/-V/sub g/ characteristics, and transconductance curves, we will demonstrate that the opposite channel is indeed damaged during channel hot-carrier (HC) stress, and this damage can be separated from the front-back coupling effect.
{"title":"Front and back gate interface-trap generation due to hot carrier stress in fully depleted SOI/MOSFETs","authors":"Yujun Li, T. Ma","doi":"10.1109/SOI.1995.526457","DOIUrl":"https://doi.org/10.1109/SOI.1995.526457","url":null,"abstract":"The analysis of hot-carrier induced degradation of SOI/MOSFETs is a complicated problem due to the dual channel and front-back coupling effect. Opinions vary as to whether hot-carrier stress of the front (or back) channel results in damage of the opposite channel. Most of the previous studies have used channel current or transconductance as the monitor of hot-carrier induced degradation in SOI/MOSFETs, which often does not allow clear separation between interface-trap generation and charge trapping at both interfaces. In this paper, by systematically examining the charge-pumping currents, junction recombination currents, static I/sub d/-V/sub g/ characteristics, and transconductance curves, we will demonstrate that the opposite channel is indeed damaged during channel hot-carrier (HC) stress, and this damage can be separated from the front-back coupling effect.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114193363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Shin, T. Wetteroth, S. Wilson, G. Harris, D. Schroder, W. Krull, M. Alles
High temperature annealing treatment is a critical step in SIMOX technology. Inert gases such as Ar or N/sub 2/ can be used during this anneal along with a small amount of oxygen. Characterization of TFSOI near-fully-depleted devices built on Ar and N/sub 2/ annealed SIMOX indicate that, in the N/sub 2/ annealed material, nitrogen atoms may become trapped at the SOI/BOX interface and cause excessive sub-threshold leakage in NMOS devices. This paper will discuss the effect of nitrogen on the device characteristics based on electrical and chemical measurements.
{"title":"Effect of nitrogen and argon anneals on the leakage current of SIMOX TFSOI devices","authors":"H. Shin, T. Wetteroth, S. Wilson, G. Harris, D. Schroder, W. Krull, M. Alles","doi":"10.1109/SOI.1995.526452","DOIUrl":"https://doi.org/10.1109/SOI.1995.526452","url":null,"abstract":"High temperature annealing treatment is a critical step in SIMOX technology. Inert gases such as Ar or N/sub 2/ can be used during this anneal along with a small amount of oxygen. Characterization of TFSOI near-fully-depleted devices built on Ar and N/sub 2/ annealed SIMOX indicate that, in the N/sub 2/ annealed material, nitrogen atoms may become trapped at the SOI/BOX interface and cause excessive sub-threshold leakage in NMOS devices. This paper will discuss the effect of nitrogen on the device characteristics based on electrical and chemical measurements.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121326595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shows that SPV can be employed for fast and reliable monitoring ofthe Si-BOX interfacial charges. Simulation ofthe 0.25 pm CMOS-SOI transistor indicated degradation ofthe subthreshold leakage when the charge density exceeded 2 * 10/sup 12/ cm-2. Further MOSFET miniaturization could lower the critical value of Q/sub Si-Box/ to the levels presently observed in SIMOX SOI wafers.
{"title":"Surface photovoltage monitoring of the Si-buried oxide interface charges","authors":"K. Nauka, M. Cao, F. Assaderaghi","doi":"10.1109/SOI.1995.526456","DOIUrl":"https://doi.org/10.1109/SOI.1995.526456","url":null,"abstract":"Shows that SPV can be employed for fast and reliable monitoring ofthe Si-BOX interfacial charges. Simulation ofthe 0.25 pm CMOS-SOI transistor indicated degradation ofthe subthreshold leakage when the charge density exceeded 2 * 10/sup 12/ cm-2. Further MOSFET miniaturization could lower the critical value of Q/sub Si-Box/ to the levels presently observed in SIMOX SOI wafers.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125048906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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