The recent demand for low-power electronics has driven narrow-width MOSFETs into applications. Meanwhile, SOI devices offer significant power reduction as compared with bulk devices due to the reduced parasitic capacitances. Therefore, it is very attractive to apply narrow-width MOSFETs fabricated on SOI substrate in low-power digital and analog design. However, the behavior of narrow-width SOI MOSFETs has never been reported. In this paper, the threshold voltage behavior of narrow-width FD/NFD SOI MOSFETs with ROSIE (Re-Oxidized Silicon Island Edges) isolation is reported for the first time.
最近对低功耗电子器件的需求推动了窄宽度mosfet的应用。同时，由于寄生电容的减小，SOI器件与本体器件相比具有显著的功耗降低。因此，在SOI衬底上制作窄宽mosfet在低功耗数字和模拟设计中具有很大的吸引力。然而，窄宽度SOI mosfet的行为从未被报道过。本文首次报道了具有ROSIE(再氧化硅岛边缘)隔离的窄宽度FD/NFD SOI mosfet的阈值电压行为。
{"title":"Narrow width effect of ROSIE isolated SOI MOSFET","authors":"S. Fung, M. Chan, S.T.H. Chan, P. Ko","doi":"10.1109/SOI.1995.526474","DOIUrl":"https://doi.org/10.1109/SOI.1995.526474","url":null,"abstract":"The recent demand for low-power electronics has driven narrow-width MOSFETs into applications. Meanwhile, SOI devices offer significant power reduction as compared with bulk devices due to the reduced parasitic capacitances. Therefore, it is very attractive to apply narrow-width MOSFETs fabricated on SOI substrate in low-power digital and analog design. However, the behavior of narrow-width SOI MOSFETs has never been reported. In this paper, the threshold voltage behavior of narrow-width FD/NFD SOI MOSFETs with ROSIE (Re-Oxidized Silicon Island Edges) isolation is reported for the first time.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Compared with partially depleted SOI devices, fully depleted (FD) devices have great potential for low-power high-speed ULSIs because of their advantages such as increased current drivability, excellent subthreshold slope and no kink effect. However, there are two major problems to be solved with 1/4-/spl mu/m level gate devices: one is high source/drain sheet resistance associated with an ultrathin SOI film in both NMOS and PMOS, and the other is low source/drain breakdown voltage induced by parasitic bipolar action in NMOS. In this paper, it will be demonstrated that both can be improved by a self-aligned tungsten (W) layer on the source/drain in ultrathin-film (50-nm) MOSFETs/SIMOX, and the hot-carrier immunity of such devices is shown. We confirmed that the W-layer formation does not cause any changes in PMOS characteristics except a reduction of source/drain sheet resistance, so we describe results in NMOSFETs.
{"title":"Characteristics of 1/4-/spl mu/m gate ultrathin-film MOSFETs/SIMOX with tungsten-deposited low-resistance source/drain","authors":"Y. Sato, T. Tsuchiya, T. Kosugi, H. Ishii","doi":"10.1109/SOI.1995.526444","DOIUrl":"https://doi.org/10.1109/SOI.1995.526444","url":null,"abstract":"Compared with partially depleted SOI devices, fully depleted (FD) devices have great potential for low-power high-speed ULSIs because of their advantages such as increased current drivability, excellent subthreshold slope and no kink effect. However, there are two major problems to be solved with 1/4-/spl mu/m level gate devices: one is high source/drain sheet resistance associated with an ultrathin SOI film in both NMOS and PMOS, and the other is low source/drain breakdown voltage induced by parasitic bipolar action in NMOS. In this paper, it will be demonstrated that both can be improved by a self-aligned tungsten (W) layer on the source/drain in ultrathin-film (50-nm) MOSFETs/SIMOX, and the hot-carrier immunity of such devices is shown. We confirmed that the W-layer formation does not cause any changes in PMOS characteristics except a reduction of source/drain sheet resistance, so we describe results in NMOSFETs.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116195276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Previously, we proposed n/sup +/-p/sup +/ double-gate SOI MOSFETs, and fabricated this device, and demonstrated high-speed, low-power performance with a gate length L/sub G/ of 0.2 /spl mu/m. In this paper, we have derived a threshold voltage model V/sub th/ for short channel devices to predict how far this device can be scaled. Using this model, which agrees with numerical data, we evaluated V/sub th/ lowering /spl Delta/V/sub th/ with decreasing the gate length L/sub G/, and showed that we can design a 0.05 /spl mu/m-L/sub G/ device with /spl Delta/V/sub th/ of 25 mV and an S-swing of 65 mV/decade.
{"title":"Analytical threshold voltage model for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs","authors":"K. Suzuki, Y. Tosaka, T. Sugii","doi":"10.1109/SOI.1995.526464","DOIUrl":"https://doi.org/10.1109/SOI.1995.526464","url":null,"abstract":"Previously, we proposed n/sup +/-p/sup +/ double-gate SOI MOSFETs, and fabricated this device, and demonstrated high-speed, low-power performance with a gate length L/sub G/ of 0.2 /spl mu/m. In this paper, we have derived a threshold voltage model V/sub th/ for short channel devices to predict how far this device can be scaled. Using this model, which agrees with numerical data, we evaluated V/sub th/ lowering /spl Delta/V/sub th/ with decreasing the gate length L/sub G/, and showed that we can design a 0.05 /spl mu/m-L/sub G/ device with /spl Delta/V/sub th/ of 25 mV and an S-swing of 65 mV/decade.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"33 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113978790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yin Hu, T. Houston, R. Rajgopal, K. Joyner, C. Teng
Various isolation techniques on SOI wafer were examined for the 256 Mbit DRAM application. The LOCOS technique results in good isolation down to 0.6 /spl mu/m pitch, in terms of encroachment and subthreshold characteristics. The encroachment of SOI wafers is slightly better than that of bulk wafers on the thick SOI wafers and expect to be even better on the thin SOI wafers. It is the most efficient way to adopt LOCOS isolation for the 256 Mbit SOI DRAM because of many years of process development experience in the bulk technology. In addition, the LOCOS isolation provides no edge leakage to the devices on SOI wafers. However, the LOCOS isolation technique may be limited as the DRAM cell pitch continue to scale down. The MESA isolation provides encroachment free for all ranges of SOI thickness. However, the MESA isolation morphology varies with the size of the isolation region. This could introduce edge leakage in devices with wide isolation region. The morphology variation can be solved with Chemical Mechanical Polishing (CMP) technology and it is expected not to be an issue in the near future. The edge leakage can be suppressed by angled channel stop implant and with mesa corner rounding treatment. As the DRAM cell pitch continue to scale down, the MESA isolation technique may be the only candidate for the 1 Gbit and beyond SOI DRAM.
针对256 Mbit DRAM应用，研究了SOI晶圆上的各种隔离技术。在入侵和亚阈值特性方面，LOCOS技术的隔离效果很好，低至0.6 /spl mu/m间距。SOI晶圆在厚SOI晶圆上的侵蚀性能略好于大块晶圆，在薄SOI晶圆上的侵蚀性能有望更好。由于在批量技术方面多年的工艺开发经验，对于256 Mbit SOI DRAM采用LOCOS隔离是最有效的方法。此外，LOCOS隔离不会为SOI晶圆上的器件提供边缘泄漏。然而，随着DRAM单元间距的不断缩小，LOCOS隔离技术可能会受到限制。MESA隔离为所有SOI厚度范围提供无侵蚀。然而，MESA隔离形态随隔离区的大小而变化。这可能会在具有宽隔离区域的器件中引入边缘泄漏。化学机械抛光(CMP)技术可以解决形貌的变化，预计在不久的将来不会成为一个问题。通过有角度的通道阻塞植入和台面圆角处理可以抑制边缘泄漏。随着DRAM单元间距的不断缩小，MESA隔离技术可能是1gbit及以上SOI DRAM的唯一候选技术。
{"title":"Isolation techniques for 256 Mbit SOI DRAM application","authors":"Yin Hu, T. Houston, R. Rajgopal, K. Joyner, C. Teng","doi":"10.1109/SOI.1995.526443","DOIUrl":"https://doi.org/10.1109/SOI.1995.526443","url":null,"abstract":"Various isolation techniques on SOI wafer were examined for the 256 Mbit DRAM application. The LOCOS technique results in good isolation down to 0.6 /spl mu/m pitch, in terms of encroachment and subthreshold characteristics. The encroachment of SOI wafers is slightly better than that of bulk wafers on the thick SOI wafers and expect to be even better on the thin SOI wafers. It is the most efficient way to adopt LOCOS isolation for the 256 Mbit SOI DRAM because of many years of process development experience in the bulk technology. In addition, the LOCOS isolation provides no edge leakage to the devices on SOI wafers. However, the LOCOS isolation technique may be limited as the DRAM cell pitch continue to scale down. The MESA isolation provides encroachment free for all ranges of SOI thickness. However, the MESA isolation morphology varies with the size of the isolation region. This could introduce edge leakage in devices with wide isolation region. The morphology variation can be solved with Chemical Mechanical Polishing (CMP) technology and it is expected not to be an issue in the near future. The edge leakage can be suppressed by angled channel stop implant and with mesa corner rounding treatment. As the DRAM cell pitch continue to scale down, the MESA isolation technique may be the only candidate for the 1 Gbit and beyond SOI DRAM.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122588384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J.B. Liu, S. Iyer, J. Min, P. K. Chu, R. Gronsky, C. Hu, N. W. Chueng
Separation by plasma implantation of oxygen (SPIMOX) is a novel method for fabricating silicon-on-insulator (SOI) wafers. This method uses plasma immersion ion implantation (PIII) where the desired voltage of implant is applied to a wafer immersed in a plasma. SPIMOX is particularly suited for thin separation by implantation of oxygen (SIMOX) wafer fabrication. High implantation rates can be achieved in SPIMOX. A dose of nearly 10/sup 18/ cm/sup -2/ with an implant current density of 1 mA cm/sup -2/ can be achieved in 3 minutes of implantation time. The short implantation time and the simplicity of the implantation equipment makes it a potentially more economical method for fabricating SIMOX wafers. Moreover, the theoretical time for implantation remains constant in SPIMOX with increase in wafer size.
等离子体氧注入分离(SPIMOX)是一种制备绝缘体上硅(SOI)晶圆的新方法。该方法采用等离子体浸没离子注入(PIII)，将所需的注入电压施加到浸没在等离子体中的晶圆上。SIMOX特别适用于通过注入氧气(SIMOX)晶圆制造的薄分离。在SPIMOX中可以实现较高的植入率。在3分钟的植入时间内，可以达到接近10/sup 18/ cm/sup -2/的剂量，植入电流密度为1 mA cm/sup -2/。短的植入时间和简单的植入设备使其成为一种潜在的更经济的制造SIMOX晶圆的方法。此外，随着晶圆尺寸的增大，SPIMOX的理论注入时间保持不变。
{"title":"Synthesis of buried oxide by plasma implantation with oxygen and water plasma","authors":"J.B. Liu, S. Iyer, J. Min, P. K. Chu, R. Gronsky, C. Hu, N. W. Chueng","doi":"10.1109/SOI.1995.526512","DOIUrl":"https://doi.org/10.1109/SOI.1995.526512","url":null,"abstract":"Separation by plasma implantation of oxygen (SPIMOX) is a novel method for fabricating silicon-on-insulator (SOI) wafers. This method uses plasma immersion ion implantation (PIII) where the desired voltage of implant is applied to a wafer immersed in a plasma. SPIMOX is particularly suited for thin separation by implantation of oxygen (SIMOX) wafer fabrication. High implantation rates can be achieved in SPIMOX. A dose of nearly 10/sup 18/ cm/sup -2/ with an implant current density of 1 mA cm/sup -2/ can be achieved in 3 minutes of implantation time. The short implantation time and the simplicity of the implantation equipment makes it a potentially more economical method for fabricating SIMOX wafers. Moreover, the theoretical time for implantation remains constant in SPIMOX with increase in wafer size.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114695844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B.H. Lee, C. Kang, J.H. Lee, S.I. Yu, K. Lee, K. Park, T. Shim
The BOnded Silicon On Insulator (BOSOI) has been considered as a promising substitute for bulk silicon technology because of its structural flexibility. However,there are considerable drawbacks if epitaxial etch stopping or localized plasma etching technique is used in the fabrication process because of low throughput and high cost. In order to obtain the ultrathin SOI layer with uniform thickness, this paper describes the cost-effective fabrication method of bonded SOI wafer using the double step CMP method in which the abrasive concentration of slurry is controlled to enhance the polish throughput. In this technique, a low total thickness variation (TTV) wafer is used as a handle wafer and the thickness variation of SOI layer can be easily reduced within a reasonable polishing time if the abrasive concentration of slurry is properly adjusted.
{"title":"A novel CMP method for cost-effective bonded SOI wafer fabrication","authors":"B.H. Lee, C. Kang, J.H. Lee, S.I. Yu, K. Lee, K. Park, T. Shim","doi":"10.1109/SOI.1995.526460","DOIUrl":"https://doi.org/10.1109/SOI.1995.526460","url":null,"abstract":"The BOnded Silicon On Insulator (BOSOI) has been considered as a promising substitute for bulk silicon technology because of its structural flexibility. However,there are considerable drawbacks if epitaxial etch stopping or localized plasma etching technique is used in the fabrication process because of low throughput and high cost. In order to obtain the ultrathin SOI layer with uniform thickness, this paper describes the cost-effective fabrication method of bonded SOI wafer using the double step CMP method in which the abrasive concentration of slurry is controlled to enhance the polish throughput. In this technique, a low total thickness variation (TTV) wafer is used as a handle wafer and the thickness variation of SOI layer can be easily reduced within a reasonable polishing time if the abrasive concentration of slurry is properly adjusted.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127869323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We report on the first 1/spl times/2 and 2/spl times/2 waveguide switches based on single-moded rib-waveguides in SOI. The switches are based on the thermo-optical effect and require switching powers of 85 mW at a wavelength of/spl lambda/=1.3 /spl mu/m. Optical device losses of 7 dB (cross talk -6 dB) for the 1/spl times/2-switch and 8 dB (cross talk -5 dB) for the 2/spl times/2-switch have been obtained including Fresnel losses of 2.4 dB.
{"title":"Integrated optical waveguide switches in SOI","authors":"U. Fischer, T. Zinke, K. Petermann","doi":"10.1109/SOI.1995.526500","DOIUrl":"https://doi.org/10.1109/SOI.1995.526500","url":null,"abstract":"We report on the first 1/spl times/2 and 2/spl times/2 waveguide switches based on single-moded rib-waveguides in SOI. The switches are based on the thermo-optical effect and require switching powers of 85 mW at a wavelength of/spl lambda/=1.3 /spl mu/m. Optical device losses of 7 dB (cross talk -6 dB) for the 1/spl times/2-switch and 8 dB (cross talk -5 dB) for the 2/spl times/2-switch have been obtained including Fresnel losses of 2.4 dB.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133988070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Sato, K. Sakaguchi, K. Yamagata, T. Atoji, Y. Fujiyama, J. Nakayama, T. Yonehara
The small thickness variation and the high crystalline quality in the SOI films are required for the large scale integration of devices. BESOI is one of the attractive methods due to its layer thickness versatility and productivity particularly in large-scale wafers. Recently, we have reported a novel BESOI method, in which an epitaxial layer on porous Si is transferred onto another handle wafer by bonding and etching back of porous Si (ELTRAN). The structure difference and the abrupt interface between porous and bulk Si gives the very high etching selectivity (10/sup 4/-10/sup 5/), so that it can replace the dopant-sensitive selective etching in the existing BESOI, and allow high-temperature heat treatments (/spl ges/1100/spl deg/C) both to grow the good epitaxial layer and to increase the bonding strength. In this paper, the high etching selectivity and the resultant SOI thickness uniformity are discussed. The crystalline quality of the SOI layer is evaluated by defect delineate etching and p-n junction diodes.
{"title":"High-quality epitaxial layer transfer (ELTRAN) by bond and etch-back of porous Si","authors":"N. Sato, K. Sakaguchi, K. Yamagata, T. Atoji, Y. Fujiyama, J. Nakayama, T. Yonehara","doi":"10.1109/SOI.1995.526517","DOIUrl":"https://doi.org/10.1109/SOI.1995.526517","url":null,"abstract":"The small thickness variation and the high crystalline quality in the SOI films are required for the large scale integration of devices. BESOI is one of the attractive methods due to its layer thickness versatility and productivity particularly in large-scale wafers. Recently, we have reported a novel BESOI method, in which an epitaxial layer on porous Si is transferred onto another handle wafer by bonding and etching back of porous Si (ELTRAN). The structure difference and the abrupt interface between porous and bulk Si gives the very high etching selectivity (10/sup 4/-10/sup 5/), so that it can replace the dopant-sensitive selective etching in the existing BESOI, and allow high-temperature heat treatments (/spl ges/1100/spl deg/C) both to grow the good epitaxial layer and to increase the bonding strength. In this paper, the high etching selectivity and the resultant SOI thickness uniformity are discussed. The crystalline quality of the SOI layer is evaluated by defect delineate etching and p-n junction diodes.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128167771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For future VLSI technologies, ensuring acceptable device isolation becomes increasingly important. In this study, fundamental variables for submicrometer LOCOS isolation including the top-layer silicon thickness, the stress-relief-oxide (SRO) thickness, the percent field over-oxidation, and field implant conditions have been explored. How these variables impact the minimum achievable isolation spacing as well as the susceptibility to MOS side-gating is examined.
{"title":"Characteristics of submicrometer LOCOS isolation","authors":"J.W. Thomas, J. E. Chung, C. Keast","doi":"10.1109/SOI.1995.526488","DOIUrl":"https://doi.org/10.1109/SOI.1995.526488","url":null,"abstract":"For future VLSI technologies, ensuring acceptable device isolation becomes increasingly important. In this study, fundamental variables for submicrometer LOCOS isolation including the top-layer silicon thickness, the stress-relief-oxide (SRO) thickness, the percent field over-oxidation, and field implant conditions have been explored. How these variables impact the minimum achievable isolation spacing as well as the susceptibility to MOS side-gating is examined.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131622132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SOI technology is based upon the difficult process of fabricating thin silicon films on an insulating layer. This thin silicon layer is the active layer of the device, but it is difficult to obtain electrical characterization of this layer. We are testing a technique for Quality Control and Quality Assessment (QC/QA) by providing rapid, non-invasive, non-contact characterization. This technique is to measure the apparent lifetime of carriers excited by pulsed optical excitation. We infer the effective carrier lifetime from the data by means of an integral of modulating functions with the observed exponentially decaying signal. This provides a robust measure of lifetime with no operator input. This system has been used to determine lifetimes as short as 15 nanoseconds (for a SOI wafer) and as long as 350 /spl mu/seconds (for a bulk wafer) with a reproducibility of about 10%.
{"title":"Minority carrier lifetime results for SOI wafers","authors":"J. Freeouf, S.T. Liu","doi":"10.1109/SOI.1995.526467","DOIUrl":"https://doi.org/10.1109/SOI.1995.526467","url":null,"abstract":"SOI technology is based upon the difficult process of fabricating thin silicon films on an insulating layer. This thin silicon layer is the active layer of the device, but it is difficult to obtain electrical characterization of this layer. We are testing a technique for Quality Control and Quality Assessment (QC/QA) by providing rapid, non-invasive, non-contact characterization. This technique is to measure the apparent lifetime of carriers excited by pulsed optical excitation. We infer the effective carrier lifetime from the data by means of an integral of modulating functions with the observed exponentially decaying signal. This provides a robust measure of lifetime with no operator input. This system has been used to determine lifetimes as short as 15 nanoseconds (for a SOI wafer) and as long as 350 /spl mu/seconds (for a bulk wafer) with a reproducibility of about 10%.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127906588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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