S. Wilson, T. Wetteroth, S. Hong, H. Shin, B. Hwang, M. Racanelli, J. Foerstner, M. Huang, H. Shin
In this paper, we will review our recent material and electrical device results on SIMOX and BESOI wafers. The substrates were obtained from 2 SIMOX suppliers (IBIS and SOITEC) and one bonded supplier (HDOS). Substrates were routinely obtained over a period of more than two years and this has given us some insight into the various manufacturers quality and reproducibility as well as improvement efforts. The material parameters such as film uniformity, contamination, defects, and wafer warp and bow will be discussed. In addition, the integrity of gate oxides grown on these substrates will be compared to those grown on bulk wafers. Device results such as threshold voltage control (Vt) and subthreshold leakage for devices built on SIMOX and BESOI wafers will be compared. These results have been obtained from several lots processed in our line and thus represent variations in both the material and the process.
{"title":"Materials, device and gate oxide integrity evaluation of SIMOX and bonded SOI wafers","authors":"S. Wilson, T. Wetteroth, S. Hong, H. Shin, B. Hwang, M. Racanelli, J. Foerstner, M. Huang, H. Shin","doi":"10.1109/SOI.1995.526501","DOIUrl":"https://doi.org/10.1109/SOI.1995.526501","url":null,"abstract":"In this paper, we will review our recent material and electrical device results on SIMOX and BESOI wafers. The substrates were obtained from 2 SIMOX suppliers (IBIS and SOITEC) and one bonded supplier (HDOS). Substrates were routinely obtained over a period of more than two years and this has given us some insight into the various manufacturers quality and reproducibility as well as improvement efforts. The material parameters such as film uniformity, contamination, defects, and wafer warp and bow will be discussed. In addition, the integrity of gate oxides grown on these substrates will be compared to those grown on bulk wafers. Device results such as threshold voltage control (Vt) and subthreshold leakage for devices built on SIMOX and BESOI wafers will be compared. These results have been obtained from several lots processed in our line and thus represent variations in both the material and the process.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123945623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Sinha, F. Duan, D. Ioannou, W. Jenkins, H. Hughes
Hot carrier related degradation and reliability of SOI devices has assumed recently increased importance. The purpose of this paper is to report two new effects in SOI MOSFETs, and the results of a detailed study of the substrate current. The first effect relates to recent reports claiming that during front gate electron injection stress, the degradation of the back channel is negligible. The second effect relates to the nature of the generation mechanisms of interface states during hot hole injection.
{"title":"SOI-specific hot-hole induced degradation in PD and FD transistors","authors":"S. Sinha, F. Duan, D. Ioannou, W. Jenkins, H. Hughes","doi":"10.1109/SOI.1995.526468","DOIUrl":"https://doi.org/10.1109/SOI.1995.526468","url":null,"abstract":"Hot carrier related degradation and reliability of SOI devices has assumed recently increased importance. The purpose of this paper is to report two new effects in SOI MOSFETs, and the results of a detailed study of the substrate current. The first effect relates to recent reports claiming that during front gate electron injection stress, the degradation of the back channel is negligible. The second effect relates to the nature of the generation mechanisms of interface states during hot hole injection.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115226557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the SIMOX process to become a viable technology, it must be capable of producing a buried oxide (BOX) layer with a high breakdown field and a low density of defects which short the superficial Si layer with the substrate. In this paper we discuss a low cost technique for significantly improving the electrical properties of the BOX. The process is compatible with the formation of a superficial Si layer with a very low density of dislocations.
{"title":"Improvement in electrical properties of SIMOX by high-temperature oxidation","authors":"B. Mrstik, P. McMarr, H. Hughes, M. Anc, W. Krull","doi":"10.1109/SOI.1995.526516","DOIUrl":"https://doi.org/10.1109/SOI.1995.526516","url":null,"abstract":"For the SIMOX process to become a viable technology, it must be capable of producing a buried oxide (BOX) layer with a high breakdown field and a low density of defects which short the superficial Si layer with the substrate. In this paper we discuss a low cost technique for significantly improving the electrical properties of the BOX. The process is compatible with the formation of a superficial Si layer with a very low density of dislocations.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123548066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Schiebel, T. Houston, R. Rajgopal, K. Joyner, J. Fossum, Dongwoo Suh, S. Krishnan
Sub and Fossum (1994) predicted that floating-body effects in partially depleted (PD) SOI transistors will cause the performance of a PD/SOI circuit to depend on its recent history. The voltage of the floating body affects the threshold voltage V/sub t/ which results in hysteretic dependence of leakage current and gate delay. The interactions are complex, and experimental data are needed to confirm the model and establish the significance of the effects on circuit performance. The purpose of this work is to advance understanding of hysteretic floating-body effects, the interplay of time constants involved in these processes, and their impact on circuit performance.
{"title":"A study of floating-body effects on inverter chain delay","authors":"R. Schiebel, T. Houston, R. Rajgopal, K. Joyner, J. Fossum, Dongwoo Suh, S. Krishnan","doi":"10.1109/SOI.1995.526492","DOIUrl":"https://doi.org/10.1109/SOI.1995.526492","url":null,"abstract":"Sub and Fossum (1994) predicted that floating-body effects in partially depleted (PD) SOI transistors will cause the performance of a PD/SOI circuit to depend on its recent history. The voltage of the floating body affects the threshold voltage V/sub t/ which results in hysteretic dependence of leakage current and gate delay. The interactions are complex, and experimental data are needed to confirm the model and establish the significance of the effects on circuit performance. The purpose of this work is to advance understanding of hysteretic floating-body effects, the interplay of time constants involved in these processes, and their impact on circuit performance.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115409867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Raynaud, J. Pelloie, O. Faynot, B. Dunne, J. Hartmann
SOI technology is a promising candidate for low-voltage low-power applications where both partially and fully depleted devices can be used to fulfil the related requirements. One advantage of fully-depleted devices is that a single N+ gate process can be kept for an advanced CMOS process. We show in this paper that an accumulation-mode fully-depleted PMOSFET using an N+ gate can be optimized for a 0.2 /spl mu/m SOI CMOS technology.
SOI技术是低压低功耗应用的一个很有前途的候选者，在这些应用中，部分和完全耗尽的器件都可以用来满足相关要求。完全耗尽器件的一个优点是可以为先进的CMOS工艺保留单个N+栅极工艺。我们在本文中表明，使用N+栅极的累加模式全耗尽PMOSFET可以针对0.2 /spl mu/m SOI CMOS技术进行优化。
{"title":"Fully-depleted accumulation-mode PMOSFET for 0.2 /spl mu/m SOI technology","authors":"C. Raynaud, J. Pelloie, O. Faynot, B. Dunne, J. Hartmann","doi":"10.1109/SOI.1995.526436","DOIUrl":"https://doi.org/10.1109/SOI.1995.526436","url":null,"abstract":"SOI technology is a promising candidate for low-voltage low-power applications where both partially and fully depleted devices can be used to fulfil the related requirements. One advantage of fully-depleted devices is that a single N+ gate process can be kept for an advanced CMOS process. We show in this paper that an accumulation-mode fully-depleted PMOSFET using an N+ gate can be optimized for a 0.2 /spl mu/m SOI CMOS technology.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115419913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Harendt, W. Wondrak, U. Apel, H. Graf, B. Hofflinger, J. Korec, E. Penteker
Intelligent power ICs are increasingly desired for applications in automotive electronics, motor control devices or flat panel displays. In order to meet the requirements regarding reliability, low area consumption and flexibility the dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Integrated power devices on fully isolated SOI wafers showed the advantages of bonded SOI material for this application. However, the full isolation restricts the power devices to area consuming lateral devices or up-drain DMOS type devices only suitable for medium power applications. Devices with high current and high breakdown voltage capability require vertical transistor types. So far, different attempts have been made to integrate vertical connected and dielectrically isolated areas on one wafer. We have developed a process, which allows the fabrication of vertical connected areas and device isolation before bonding and requires no special alignment. First, the area for the vertical contact is patterned and covered with a silicon nitride layer. Subsequently, V-grooves are patterned, etched and thermally oxidised. After removal of the nitride layer the V-grooves are filled with polysilicon. Depending on the deposition conditions, the vertical contact area is filled with polysilicon or epitaxial grown silicon. Thinning occurs by chemo-mechanical polishing. As in the "classical" DI process the oxide at the bottom of the V-groove serves as a polishing stop resulting in a better SOI thickness uniformity.
{"title":"Wafer bonding for intelligent power ICs: integration of vertical structures","authors":"C. Harendt, W. Wondrak, U. Apel, H. Graf, B. Hofflinger, J. Korec, E. Penteker","doi":"10.1109/SOI.1995.526505","DOIUrl":"https://doi.org/10.1109/SOI.1995.526505","url":null,"abstract":"Intelligent power ICs are increasingly desired for applications in automotive electronics, motor control devices or flat panel displays. In order to meet the requirements regarding reliability, low area consumption and flexibility the dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Integrated power devices on fully isolated SOI wafers showed the advantages of bonded SOI material for this application. However, the full isolation restricts the power devices to area consuming lateral devices or up-drain DMOS type devices only suitable for medium power applications. Devices with high current and high breakdown voltage capability require vertical transistor types. So far, different attempts have been made to integrate vertical connected and dielectrically isolated areas on one wafer. We have developed a process, which allows the fabrication of vertical connected areas and device isolation before bonding and requires no special alignment. First, the area for the vertical contact is patterned and covered with a silicon nitride layer. Subsequently, V-grooves are patterned, etched and thermally oxidised. After removal of the nitride layer the V-grooves are filled with polysilicon. Depending on the deposition conditions, the vertical contact area is filled with polysilicon or epitaxial grown silicon. Thinning occurs by chemo-mechanical polishing. As in the \"classical\" DI process the oxide at the bottom of the V-groove serves as a polishing stop resulting in a better SOI thickness uniformity.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"649 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122701974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Raskin, D. Vanhoenacker, J. Colinge, D. Flandre
The use of high-resistivity SIMOX substrates has been proposed to enable the integration of low-loss adapted lines for MMIC applications in SOI CMOS technology. In this work we investigate the impact of the substrate resistivity on another important substrate coupling effect: the intrinsic load impedance of active transistors in amplifier configuration, which conditions the device maximum stable frequency. Related device and line modelling aspects are also discussed.
{"title":"Coupling effects in high-resistivity SIMOX substrates for VHF and microwave applications","authors":"J. Raskin, D. Vanhoenacker, J. Colinge, D. Flandre","doi":"10.1109/SOI.1995.526461","DOIUrl":"https://doi.org/10.1109/SOI.1995.526461","url":null,"abstract":"The use of high-resistivity SIMOX substrates has been proposed to enable the integration of low-loss adapted lines for MMIC applications in SOI CMOS technology. In this work we investigate the impact of the substrate resistivity on another important substrate coupling effect: the intrinsic load impedance of active transistors in amplifier configuration, which conditions the device maximum stable frequency. Related device and line modelling aspects are also discussed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126763379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Sherony, A. Chen, K. Mistry, D. Antoniadis, B. Doyle
Plasma-induced charging damage was examined on both bulk and SOI n-MOSFETs using time-zero dielectric breakdown measurements. It was found that the TZDB distributions for the SOI devices were less dependent on antenna ratio and less susceptible to antenna charging damage than bulk silicon devices. The dramatically different behavior for SOI implies that the antenna design rule requirements for bulk and SOI MOSFETs will not be the same. Finally, it is noted that antenna damage effects in SOI devices may depend on the size of the silicon island relative to the length scale of the plasma non-uniformity.
{"title":"Comparison of plasma-induced charging damage in bulk and SOI MOSFETs","authors":"M. Sherony, A. Chen, K. Mistry, D. Antoniadis, B. Doyle","doi":"10.1109/SOI.1995.526440","DOIUrl":"https://doi.org/10.1109/SOI.1995.526440","url":null,"abstract":"Plasma-induced charging damage was examined on both bulk and SOI n-MOSFETs using time-zero dielectric breakdown measurements. It was found that the TZDB distributions for the SOI devices were less dependent on antenna ratio and less susceptible to antenna charging damage than bulk silicon devices. The dramatically different behavior for SOI implies that the antenna design rule requirements for bulk and SOI MOSFETs will not be the same. Finally, it is noted that antenna damage effects in SOI devices may depend on the size of the silicon island relative to the length scale of the plasma non-uniformity.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125987206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Krishnan, J. Fossum, P. Yeh, O. Faynot, S. Cristoloveanu, J. Gautier
Fully depleted (FD) SOI CMOS is a contender for low-voltage IC applications. However, as FD/SOI MOSFETs are scaled, floating-body effects, which previously seemed insignificant, become important. In this paper, we report kinks in the measured subthreshold current-voltage characteristics of highly scaled FD/SOI MOSFETs, and we describe and model the underlying physical mechanism, showing how it differs from the familiar kink effect in partially depleted (PD) devices. The insight afforded qualifies the meaning of FD/SOI and implies new design issues for low-voltage SOI CMOS.
全耗尽(FD) SOI CMOS是低压集成电路应用的有力竞争者。然而，随着FD/SOI mosfet的缩放，以前看起来微不足道的浮体效应变得重要起来。在本文中，我们报告了高尺度FD/SOI mosfet测量的亚阈值电流电压特性中的扭结，并描述和建模了潜在的物理机制，显示了它与部分耗尽(PD)器件中常见的扭结效应的不同之处。所提供的见解限定了FD/SOI的含义，并暗示了低压SOI CMOS的新设计问题。
{"title":"Floating-body kinks and dynamic effects in fully depleted SOI MOSFETs","authors":"S. Krishnan, J. Fossum, P. Yeh, O. Faynot, S. Cristoloveanu, J. Gautier","doi":"10.1109/SOI.1995.526435","DOIUrl":"https://doi.org/10.1109/SOI.1995.526435","url":null,"abstract":"Fully depleted (FD) SOI CMOS is a contender for low-voltage IC applications. However, as FD/SOI MOSFETs are scaled, floating-body effects, which previously seemed insignificant, become important. In this paper, we report kinks in the measured subthreshold current-voltage characteristics of highly scaled FD/SOI MOSFETs, and we describe and model the underlying physical mechanism, showing how it differs from the familiar kink effect in partially depleted (PD) devices. The insight afforded qualifies the meaning of FD/SOI and implies new design issues for low-voltage SOI CMOS.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125991455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is demonstrated that thermal resistances of SOI MOSFETs obtained by two different methods (gate resistance thermometry and small-signal drain conductance) show very good agreement. This confirms that the full device temperature rise can be associated with a single thermal time constant. Hence, the time constant of the order of 1 /spl mu/s seen in the measurements is the dominant effect on self-heating for all practical purposes. The comparison shows that both techniques yield good results; the drain conductance technique has the further advantage that standard transistors may be used.
{"title":"Comparison of SOI MOSFET self-heating measurements by gate resistance thermometry and small-signal drain admittance extraction","authors":"B. Tenbroek, W. Redman-White, M.S.L. Lee, M. Uren","doi":"10.1109/SOI.1995.526454","DOIUrl":"https://doi.org/10.1109/SOI.1995.526454","url":null,"abstract":"It is demonstrated that thermal resistances of SOI MOSFETs obtained by two different methods (gate resistance thermometry and small-signal drain conductance) show very good agreement. This confirms that the full device temperature rise can be associated with a single thermal time constant. Hence, the time constant of the order of 1 /spl mu/s seen in the measurements is the dominant effect on self-heating for all practical purposes. The comparison shows that both techniques yield good results; the drain conductance technique has the further advantage that standard transistors may be used.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131899890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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