F. Plais, O. Huet, P. Legagneux, D. Pribat, A. Auberton-Herve, T. Barge
Direct-view active matrix liquid crystal displays (AMLCDs) are now fabricated in very large volumes using amorphous silicon (a-Si:H) technology. For this purpose, high temperature polysilicon technology is currently used in Japan, with the active matrix fabricated on a quartz substrate. However, quartz substrates of display quality are rather expensive and low temperature polysilicon technology on glass substrates using laser annealing has been introduced as one possible alternative. Recently the transfer of single-crystalline Si layers on glass has been reported. In this case, circuits are fabricated on SOI substrates obtained by a zone melting recrystallisation process and transfered on the glass after completion of almost all the processing steps. This technique is of interest, as high temperature processing steps and fine design rules can be utilized. The main drawback of the technique is that the transfer operation is the final step. We propose an alternative and new technique based on the transfer before processing of a single crystalline Si layer on glass. Processing is subsequently performed at low temperature, using technological steps developed for the fabrication of low temperature polysilicon devices. A SIMOX substrate is thermally oxydized and then bonded at 450/spl deg/C to the glass substrate (Corning 7059 or 1737). The silicon substrate and the thin buried oxide are then removed by a combination of mechanical and chemical etching.
{"title":"Single crystalline silicon thin film transistors fabricated on Corning 7059","authors":"F. Plais, O. Huet, P. Legagneux, D. Pribat, A. Auberton-Herve, T. Barge","doi":"10.1109/SOI.1995.526514","DOIUrl":"https://doi.org/10.1109/SOI.1995.526514","url":null,"abstract":"Direct-view active matrix liquid crystal displays (AMLCDs) are now fabricated in very large volumes using amorphous silicon (a-Si:H) technology. For this purpose, high temperature polysilicon technology is currently used in Japan, with the active matrix fabricated on a quartz substrate. However, quartz substrates of display quality are rather expensive and low temperature polysilicon technology on glass substrates using laser annealing has been introduced as one possible alternative. Recently the transfer of single-crystalline Si layers on glass has been reported. In this case, circuits are fabricated on SOI substrates obtained by a zone melting recrystallisation process and transfered on the glass after completion of almost all the processing steps. This technique is of interest, as high temperature processing steps and fine design rules can be utilized. The main drawback of the technique is that the transfer operation is the final step. We propose an alternative and new technique based on the transfer before processing of a single crystalline Si layer on glass. Processing is subsequently performed at low temperature, using technological steps developed for the fabrication of low temperature polysilicon devices. A SIMOX substrate is thermally oxydized and then bonded at 450/spl deg/C to the glass substrate (Corning 7059 or 1737). The silicon substrate and the thin buried oxide are then removed by a combination of mechanical and chemical etching.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132577490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There is general agreement that SOI CMOS has the potential of becoming a mainstream technology for future high performance and low-power logic applications. For this to be fulfilled, SOI CMOS technology should be able to support the design and manufacturing of complex future microprocessors. Then, from the design standpoint, SOI CMOS should be nearly identical to bulk CMOS, so that design tools, methodologies, and functional blocks can all be transferred with minimal perturbation. From the manufacturing standpoint, SOI CMOS should produce acceptable yields in circuits with 10 to 100 M transistors which will require process robustness latitude, scalability, and cost equivalent to or better than bulk. From the circuit design standpoint it is generally acknowledged that fully-depleted (FD) MOSFET's will provide the easier transfer path, because of their lack of significant floating-body (FB) effects under normal operation. However, scaled FD-MOSFET's require very thin SOI films which pose several technological challenges. On the other hand, partially-depleted (PD) MOSFET's are easier to make; indeed, their front-end technology can be imported from bulk with minimal perturbation. However, they display prominent FB effects which can pose problems in circuit design. The choice between the FD versus PD option is then recognized as the main SOI front-end technology tradeoff.
{"title":"SOI CMOS front-end technology: options and tradeoffs","authors":"D. Antoniadis","doi":"10.1109/SOI.1995.526431","DOIUrl":"https://doi.org/10.1109/SOI.1995.526431","url":null,"abstract":"There is general agreement that SOI CMOS has the potential of becoming a mainstream technology for future high performance and low-power logic applications. For this to be fulfilled, SOI CMOS technology should be able to support the design and manufacturing of complex future microprocessors. Then, from the design standpoint, SOI CMOS should be nearly identical to bulk CMOS, so that design tools, methodologies, and functional blocks can all be transferred with minimal perturbation. From the manufacturing standpoint, SOI CMOS should produce acceptable yields in circuits with 10 to 100 M transistors which will require process robustness latitude, scalability, and cost equivalent to or better than bulk. From the circuit design standpoint it is generally acknowledged that fully-depleted (FD) MOSFET's will provide the easier transfer path, because of their lack of significant floating-body (FB) effects under normal operation. However, scaled FD-MOSFET's require very thin SOI films which pose several technological challenges. On the other hand, partially-depleted (PD) MOSFET's are easier to make; indeed, their front-end technology can be imported from bulk with minimal perturbation. However, they display prominent FB effects which can pose problems in circuit design. The choice between the FD versus PD option is then recognized as the main SOI front-end technology tradeoff.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114648852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Pelella, J. Fossum, Dongwoo Suh, S. Krishnan, K. Jenkins
Partially-depleted (PD) SOI MOSFETs offer improved threshold control and sensitivity over fully depleted devices, but the effects of dynamic floating-body charging on the threshold voltage VT(t) can possibly lead to instabilities in PD/SOI circuits. We show in this paper that the dynamic charging of the body can also induce a parasitic bipolar-transistor (BJT) transient current which can be significant even at low voltages well below the drain-source breakdown defined by the BJT. Our results indicate that if device/circuit design allows substantial variation of the body charge, then the transient BJT current could be large enough to upset the logic or memory (SRAM or DRAM) function of a chip. They further show that such an upset becomes more probable as the device is scaled, and they give insight regarding device and circuit design to reduce the probability.
与完全耗尽器件相比，部分耗尽(PD) SOI mosfet提供了更好的阈值控制和灵敏度，但动态浮体充电对阈值电压VT(t)的影响可能导致PD/SOI电路的不稳定。我们在本文中表明，体的动态充电也可以诱导寄生双极晶体管(BJT)瞬态电流，即使在远低于BJT定义的漏源击穿的低电压下，该电流也可以显着。我们的研究结果表明，如果器件/电路设计允许本体电荷的实质性变化，那么瞬态BJT电流可能大到足以扰乱芯片的逻辑或内存(SRAM或DRAM)功能。他们进一步表明，随着设备的缩放，这种混乱变得更有可能，并且他们提供了有关设备和电路设计的见解，以降低概率。
{"title":"Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFETs","authors":"M. Pelella, J. Fossum, Dongwoo Suh, S. Krishnan, K. Jenkins","doi":"10.1109/SOI.1995.526434","DOIUrl":"https://doi.org/10.1109/SOI.1995.526434","url":null,"abstract":"Partially-depleted (PD) SOI MOSFETs offer improved threshold control and sensitivity over fully depleted devices, but the effects of dynamic floating-body charging on the threshold voltage VT(t) can possibly lead to instabilities in PD/SOI circuits. We show in this paper that the dynamic charging of the body can also induce a parasitic bipolar-transistor (BJT) transient current which can be significant even at low voltages well below the drain-source breakdown defined by the BJT. Our results indicate that if device/circuit design allows substantial variation of the body charge, then the transient BJT current could be large enough to upset the logic or memory (SRAM or DRAM) function of a chip. They further show that such an upset becomes more probable as the device is scaled, and they give insight regarding device and circuit design to reduce the probability.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132946829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A. Auberton-Herve, J. Lamure, T. Barge, F. Metral, S. Trucchi
Silicon On Insulator technologies appear to be a key issue for low-power, low-voltage technologies (/spl ap/1.5 V) and will play a major role in ULSI developments. Today two SOI material technologies are in competition in the very thin SOI film market: SIMOX (Separation by IMplanted OXygen) and BESOI (Bond and Etch Back SOI) Technology. We have developed a new SOI material technology using a bonding technique combined with an ion implantation step, which aims to overcome the remaining limitations of both the above techniques. This process was developed as the "IMPROVE" (IMplanted PROtons Voids Engineering) process and is henceforth referred to as "Smart-cut". The process is implemented for fabrication of Unibond wafers.
{"title":"\"Smart cut\": a promising new SOI material technology","authors":"M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A. Auberton-Herve, J. Lamure, T. Barge, F. Metral, S. Trucchi","doi":"10.1109/SOI.1995.526518","DOIUrl":"https://doi.org/10.1109/SOI.1995.526518","url":null,"abstract":"Silicon On Insulator technologies appear to be a key issue for low-power, low-voltage technologies (/spl ap/1.5 V) and will play a major role in ULSI developments. Today two SOI material technologies are in competition in the very thin SOI film market: SIMOX (Separation by IMplanted OXygen) and BESOI (Bond and Etch Back SOI) Technology. We have developed a new SOI material technology using a bonding technique combined with an ion implantation step, which aims to overcome the remaining limitations of both the above techniques. This process was developed as the \"IMPROVE\" (IMplanted PROtons Voids Engineering) process and is henceforth referred to as \"Smart-cut\". The process is implemented for fabrication of Unibond wafers.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133188823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Weldon, Y. Chabal, S. Christman, J. Bourcereau, C. A. Goodwin, C. Hsieh, S. Nakahara, R. Shanaman, W. G. Easter, L. Feldman
In this work, we utilize infrared absorption spectroscopy (IRAS) to probe the chemical purity of both wafer surfaces immediately prior to bonding and the wafer interface right after joining. The IRAS technique can give partial chemical information, particularly for hydrogen and can also indicate the nature of the interactions (van der Waals, H-bonding, chemical bonds). Experimentally, we probe the surfaces of Si wafers in two ways: either with multiple internal reflections (MIR) using the wafer itself to trap the IR radiation, or with MIR using a germanium plate to trap the IR radiation. The first approach is a convenient way to probe all vibrations above 1500 cm/sup -1/. The second is a sensitive way to access lower frequency vibrations (>700 cm/sup -1/), but is insensitive to the components parallel to the interface. To probe the interface of joined wafers, we use the technique of multiple internal transmission (MIT), using the joined Si wafers themselves to trap the IR radiation. This configuration is again limited to frequencies above 1500 cm/sup -1/, but its sensitivity to vibrations perpendicular to the interface is 20 times that of MIR.
{"title":"The role of hydrogen in silicon wafer bonding: an infrared study","authors":"M. Weldon, Y. Chabal, S. Christman, J. Bourcereau, C. A. Goodwin, C. Hsieh, S. Nakahara, R. Shanaman, W. G. Easter, L. Feldman","doi":"10.1109/SOI.1995.526513","DOIUrl":"https://doi.org/10.1109/SOI.1995.526513","url":null,"abstract":"In this work, we utilize infrared absorption spectroscopy (IRAS) to probe the chemical purity of both wafer surfaces immediately prior to bonding and the wafer interface right after joining. The IRAS technique can give partial chemical information, particularly for hydrogen and can also indicate the nature of the interactions (van der Waals, H-bonding, chemical bonds). Experimentally, we probe the surfaces of Si wafers in two ways: either with multiple internal reflections (MIR) using the wafer itself to trap the IR radiation, or with MIR using a germanium plate to trap the IR radiation. The first approach is a convenient way to probe all vibrations above 1500 cm/sup -1/. The second is a sensitive way to access lower frequency vibrations (>700 cm/sup -1/), but is insensitive to the components parallel to the interface. To probe the interface of joined wafers, we use the technique of multiple internal transmission (MIT), using the joined Si wafers themselves to trap the IR radiation. This configuration is again limited to frequencies above 1500 cm/sup -1/, but its sensitivity to vibrations perpendicular to the interface is 20 times that of MIR.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125901934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G.G. Li, A. R. Forouhi, A. Auberton-Herve, A. Wittkower
A study of the optical properties of SOI wafers can provide a quick, nondestructive, and reliable characterization technique. In this paper, we demonstrate a new optical technique which can simultaneously and unambiguously determine thickness, interface roughness (/spl sigma/), refractive index (n), and extinction coefficient (k) of thin films for SOI. The Forouhi-Bloomer dispersion equation for n and k is used to analyze measured reflectance spectra.
{"title":"Optical characterization of silicon-on-insulator","authors":"G.G. Li, A. R. Forouhi, A. Auberton-Herve, A. Wittkower","doi":"10.1109/SOI.1995.526483","DOIUrl":"https://doi.org/10.1109/SOI.1995.526483","url":null,"abstract":"A study of the optical properties of SOI wafers can provide a quick, nondestructive, and reliable characterization technique. In this paper, we demonstrate a new optical technique which can simultaneously and unambiguously determine thickness, interface roughness (/spl sigma/), refractive index (n), and extinction coefficient (k) of thin films for SOI. The Forouhi-Bloomer dispersion equation for n and k is used to analyze measured reflectance spectra.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kawamura, T. Nakajima, I. Hamaguchi, T. Yano, Y. Nagatake, M. Tachimori
For commercial ULSIs using SOI CMOS, low-dose SIMOX wafers are very attractive because of their excellent crystalline quality and low cost compared with high-dose SIMOX wafers. However, it has been reported that the buried-oxide (BOX) of the low-dose SIMOX wafer has a couple of problems to be solved. One problem is the presence of "pipe" leakage caused by particles shadowing the oxygen ion beam during the implantation. Another problem is the breakdown electric field being lower than that of the thermal oxide. In this paper, it is shown that high-temperature oxidation, which increases the BOX thickness, effectively solves the above problems.
{"title":"Improvement of buried oxide quality in low-dose SIMOX wafers by high-temperature oxidation","authors":"K. Kawamura, T. Nakajima, I. Hamaguchi, T. Yano, Y. Nagatake, M. Tachimori","doi":"10.1109/SOI.1995.526507","DOIUrl":"https://doi.org/10.1109/SOI.1995.526507","url":null,"abstract":"For commercial ULSIs using SOI CMOS, low-dose SIMOX wafers are very attractive because of their excellent crystalline quality and low cost compared with high-dose SIMOX wafers. However, it has been reported that the buried-oxide (BOX) of the low-dose SIMOX wafer has a couple of problems to be solved. One problem is the presence of \"pipe\" leakage caused by particles shadowing the oxygen ion beam during the implantation. Another problem is the breakdown electric field being lower than that of the thermal oxide. In this paper, it is shown that high-temperature oxidation, which increases the BOX thickness, effectively solves the above problems.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131114119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The supply noise from the packaging of CMOS/SOI circuits can cause performance degradation, reliability reduction and even loss of circuit functionality due to the device latch-up problem. By properly adding on-chip decoupling capacitors in the proximity of the circuitry, we can effectively alleviate the switching noise problem and improve the performance of CMOS/SOI circuits.
{"title":"On-chip decoupling capacitor design to reduce switching-noise-induced instability in CMOS/SOI VLSI","authors":"L. K. Wang, Howard H. Chen","doi":"10.1109/SOI.1995.526480","DOIUrl":"https://doi.org/10.1109/SOI.1995.526480","url":null,"abstract":"The supply noise from the packaging of CMOS/SOI circuits can cause performance degradation, reliability reduction and even loss of circuit functionality due to the device latch-up problem. By properly adding on-chip decoupling capacitors in the proximity of the circuitry, we can effectively alleviate the switching noise problem and improve the performance of CMOS/SOI circuits.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The purpose of this paper is to report the successful injection of holes into the buried oxide of SIMOX for determining hole trap densities and cross-sections. Avalanche injection is used to drive holes into the oxide from the avalanche plasma generated in the depletion region of the superficial silicon layer. The carrier injection rate is controlled by varying the applied voltage and repetition rate of the exciting gate pulse. Avalanche injection is unique in that it permits the independent study of both electrons and holes. Such a study serves to clarify the role played by either electrons or holes in a radiation environment by eliminating the complications associated with ionizing radiation studies where both electrons and holes are generated.
{"title":"Avalanche hole injection into SIMOX oxide","authors":"R. J. Lambert, T. Bhar, H. Hughes, L. Allen","doi":"10.1109/SOI.1995.526490","DOIUrl":"https://doi.org/10.1109/SOI.1995.526490","url":null,"abstract":"The purpose of this paper is to report the successful injection of holes into the buried oxide of SIMOX for determining hole trap densities and cross-sections. Avalanche injection is used to drive holes into the oxide from the avalanche plasma generated in the depletion region of the superficial silicon layer. The carrier injection rate is controlled by varying the applied voltage and repetition rate of the exciting gate pulse. Avalanche injection is unique in that it permits the independent study of both electrons and holes. Such a study serves to clarify the role played by either electrons or holes in a radiation environment by eliminating the complications associated with ionizing radiation studies where both electrons and holes are generated.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116983150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An SOI DRAM is a candidate for giga-bit scale DRAM with improved data retention characteristics and/or simple capacitor structure achieved by low leakage current, reduced soft error effect and low Cb/Cs ratio. The SOI DRAM is also expected to realize low-voltage memory which will be used in handy systems in a forthcoming multimedia era by reduced junction capacitance and back-gate-bias effect. However, some drawbacks are also suspected owing to floating substrate effects. In the present report, these features are summarized to demonstrate the perspective on SOI DRAM.
SOI DRAM是千兆级DRAM的候选产品，具有更好的数据保留特性和/或简单的电容器结构，通过低泄漏电流，减少软误差效应和低Cb/Cs比实现。SOI DRAM还有望通过降低结电容和反向偏置效应，实现在即将到来的多媒体时代的便携式系统中使用的低压存储器。然而，由于浮动衬底效应，也存在一些缺陷。在本报告中，总结了这些特点，以展示SOI DRAM的前景。
{"title":"SOI DRAM: its features and possibility","authors":"Y. Yamaguchi, Y. Inoue","doi":"10.1109/SOI.1995.526491","DOIUrl":"https://doi.org/10.1109/SOI.1995.526491","url":null,"abstract":"An SOI DRAM is a candidate for giga-bit scale DRAM with improved data retention characteristics and/or simple capacitor structure achieved by low leakage current, reduced soft error effect and low Cb/Cs ratio. The SOI DRAM is also expected to realize low-voltage memory which will be used in handy systems in a forthcoming multimedia era by reduced junction capacitance and back-gate-bias effect. However, some drawbacks are also suspected owing to floating substrate effects. In the present report, these features are summarized to demonstrate the perspective on SOI DRAM.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115939572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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