The mechanism of SFT generation in low-dose SIMOX wafers was analyzed. It was found that generation of these microdefects inside the top Si layer is strongly suppressed in comparison with those in the BOX. Moreover, both processes occur at different stages of high temperature annealing and thus can be controlled by the proper optimization of annealing conditions. As a result, it seems possible to produce SIMOX wafers with a defect-free top Si film and a gettering layer located beneath the BOX.
{"title":"Gettering layer formation in low-dose SIMOX wafers","authors":"J. Jabłoński, M. Saito, M. Imai, S. Nakashima","doi":"10.1109/SOI.1995.526447","DOIUrl":"https://doi.org/10.1109/SOI.1995.526447","url":null,"abstract":"The mechanism of SFT generation in low-dose SIMOX wafers was analyzed. It was found that generation of these microdefects inside the top Si layer is strongly suppressed in comparison with those in the BOX. Moreover, both processes occur at different stages of high temperature annealing and thus can be controlled by the proper optimization of annealing conditions. As a result, it seems possible to produce SIMOX wafers with a defect-free top Si film and a gettering layer located beneath the BOX.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125563124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Presents a new technique for thinning SOI bonded wafers by applying voltage during KOH etching. The SOI surface is etched by KOH, and voltage is applied between the supporting substrate and etchant. As a result, etching stops automatically at a certain thickness corresponding to the applied voltage. Conventional MIS etch stopping requires an additional electrode at the SOI surface, and also requires an extra process to provide good ohmic contact at the electrode. Moreover, as it is difficult to apply uniform voltage over a large area SOI active layer, an area with a diameter of only several millimeters can be thinned uniformly. Other techniques, such as scanning of limited area plasma etching and other etch stopping techniques have been proposed to make thin uniform SOI bonded wafers. Most of these techniques, however, involve relatively expensive processes such as plasma thinning, epitaxy and ion implantation. This paper proposes a low-cost etch stopping process for bonded SOI that allows variation of less than /spl plusmn/0.1 /spl mu/m in 150mm /spl phi/ wafers.
{"title":"Highly uniform SOI fabrication by applying voltage during KOH etching of bonded wafers","authors":"A. Ogura","doi":"10.1109/SOI.1995.526459","DOIUrl":"https://doi.org/10.1109/SOI.1995.526459","url":null,"abstract":"Presents a new technique for thinning SOI bonded wafers by applying voltage during KOH etching. The SOI surface is etched by KOH, and voltage is applied between the supporting substrate and etchant. As a result, etching stops automatically at a certain thickness corresponding to the applied voltage. Conventional MIS etch stopping requires an additional electrode at the SOI surface, and also requires an extra process to provide good ohmic contact at the electrode. Moreover, as it is difficult to apply uniform voltage over a large area SOI active layer, an area with a diameter of only several millimeters can be thinned uniformly. Other techniques, such as scanning of limited area plasma etching and other etch stopping techniques have been proposed to make thin uniform SOI bonded wafers. Most of these techniques, however, involve relatively expensive processes such as plasma thinning, epitaxy and ion implantation. This paper proposes a low-cost etch stopping process for bonded SOI that allows variation of less than /spl plusmn/0.1 /spl mu/m in 150mm /spl phi/ wafers.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130840626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S.O. Hong, T. Wetteroth, H. Shin, S. Wilson, W.M. Huang, J. Foerstner, M. Racanelli, H. Shin, B. Hwang, D. Schroder
The quality of gate oxides on Thin-Film-Silicon-On-Insulator (TFSOI) substrates is essential for the development of TFSOI technologies. Compared with the extensive work on device characterization and circuit performance, however, data in this area are still limited. This paper presents a gate oxide integrity (GOI) study on both SIMOX (Separation-by-IMplantation-of-OXygen) and BESOI (Bonded-Etched-back-SOI) substrates. The effect of wafer polishing to reduce the initial surface micro-roughness is also discussed.
{"title":"Integrity of gate oxide on TFSOI materials","authors":"S.O. Hong, T. Wetteroth, H. Shin, S. Wilson, W.M. Huang, J. Foerstner, M. Racanelli, H. Shin, B. Hwang, D. Schroder","doi":"10.1109/SOI.1995.526441","DOIUrl":"https://doi.org/10.1109/SOI.1995.526441","url":null,"abstract":"The quality of gate oxides on Thin-Film-Silicon-On-Insulator (TFSOI) substrates is essential for the development of TFSOI technologies. Compared with the extensive work on device characterization and circuit performance, however, data in this area are still limited. This paper presents a gate oxide integrity (GOI) study on both SIMOX (Separation-by-IMplantation-of-OXygen) and BESOI (Bonded-Etched-back-SOI) substrates. The effect of wafer polishing to reduce the initial surface micro-roughness is also discussed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Silicon-on-Diamond (SOD) is a candidate for the next generation of SOI materials, especially for applications requiring high heat spreading capability. Undoped diamond is a highly electrically insulating material at temperatures below 600 K. Resistivities above 10/sup 13/ /spl Omega/cm (at 10 V) and breakdown fields above 10/sup 7/ V/cm have been reported. Diamond conducts heat about 10 times better than silicon and more than 1000 times better than silicon dioxide. In this paper, necessary process modifications for successful manufacturing of devices on SOD-materials are discussed and evaluated.
{"title":"Evaluation of silicon device processes aimed for silicon-on-diamond material","authors":"A. Soderbarg, B. Edholm, S. Bengtsson","doi":"10.1109/SOI.1995.526482","DOIUrl":"https://doi.org/10.1109/SOI.1995.526482","url":null,"abstract":"Silicon-on-Diamond (SOD) is a candidate for the next generation of SOI materials, especially for applications requiring high heat spreading capability. Undoped diamond is a highly electrically insulating material at temperatures below 600 K. Resistivities above 10/sup 13/ /spl Omega/cm (at 10 V) and breakdown fields above 10/sup 7/ V/cm have been reported. Diamond conducts heat about 10 times better than silicon and more than 1000 times better than silicon dioxide. In this paper, necessary process modifications for successful manufacturing of devices on SOD-materials are discussed and evaluated.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122625430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The new portable computing and telecommunications market requires high performance, low power, high density electrically reprogrammable non-volatile memories. Memories integrated with information handling circuits on SOI wafers can offer significant advantages for high speed computation, better isolation, lower leakage, better noise immunity, and excellent CMOS latch-up margin. A NOR Virtual Ground (NVG) flash memory cell fabricated on an SOI wafer is considered. The fabrication process for NVG on SOI can be unchanged if the silicon thickness of the SOI wafer is properly chosen and doped, such that the N+ bit-line (Source/Drain) touches the oxide layer. One important feature of cells on SOI is that it is difficult to ground the p-body of cell and it will be left floating during all memory operations. Therefore, it is important to study the effect of the floating body on channel-hot-electron (CHE) programming and Fowler-Nordheim (F-N) channel erase used in NVG flash memory.
{"title":"Programming and erase with floating-body for high density low voltage flash EEPROM fabricated on SOI wafers","authors":"M. Chi, A. Bergemont","doi":"10.1109/SOI.1995.526494","DOIUrl":"https://doi.org/10.1109/SOI.1995.526494","url":null,"abstract":"The new portable computing and telecommunications market requires high performance, low power, high density electrically reprogrammable non-volatile memories. Memories integrated with information handling circuits on SOI wafers can offer significant advantages for high speed computation, better isolation, lower leakage, better noise immunity, and excellent CMOS latch-up margin. A NOR Virtual Ground (NVG) flash memory cell fabricated on an SOI wafer is considered. The fabrication process for NVG on SOI can be unchanged if the silicon thickness of the SOI wafer is properly chosen and doped, such that the N+ bit-line (Source/Drain) touches the oxide layer. One important feature of cells on SOI is that it is difficult to ground the p-body of cell and it will be left floating during all memory operations. Therefore, it is important to study the effect of the floating body on channel-hot-electron (CHE) programming and Fowler-Nordheim (F-N) channel erase used in NVG flash memory.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130590303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In silicon many of the transition metals have states near the center of the gap and so can be used to form semi-insulating wafers. In this paper calculated and measured resistivities of silicon as a function of substrate doping for gold doped n-type and silver doped p-type silicon are presented. Arrhenius plots of the effective diffusion coefficient of gold in Si/sub 3/N/sub 4/ diffusion barriers are also measured. A structure for forming semi-insulating silicon with an upper conductive layer using a wafer bonding technique is developed.
{"title":"Semi-insulating silicon for microwave integrated circuits","authors":"S. Campbell","doi":"10.1109/SOI.1995.526476","DOIUrl":"https://doi.org/10.1109/SOI.1995.526476","url":null,"abstract":"In silicon many of the transition metals have states near the center of the gap and so can be used to form semi-insulating wafers. In this paper calculated and measured resistivities of silicon as a function of substrate doping for gold doped n-type and silver doped p-type silicon are presented. Arrhenius plots of the effective diffusion coefficient of gold in Si/sub 3/N/sub 4/ diffusion barriers are also measured. A structure for forming semi-insulating silicon with an upper conductive layer using a wafer bonding technique is developed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123055373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Reichert, T. Ouisse, J. Pelloie, S. Cristoloveanu
The temperature range of silicon components may be substantially extended by using SOI devices. In this paper, we propose a new physical definition of the usual parameters appearing in the empirical models used for expressing the surface mobility. We also present a thorough experimental study of the mobility in thin film SOI MOSFET's, in the temperature range 298-623K. All data agree with the theoretical model, which may thus be used for a physical interpretation of the results from room to high temperature.
{"title":"Surface mobility of SOI MOSFET's in the high temperature range: modelling and experiment","authors":"G. Reichert, T. Ouisse, J. Pelloie, S. Cristoloveanu","doi":"10.1109/SOI.1995.526451","DOIUrl":"https://doi.org/10.1109/SOI.1995.526451","url":null,"abstract":"The temperature range of silicon components may be substantially extended by using SOI devices. In this paper, we propose a new physical definition of the usual parameters appearing in the empirical models used for expressing the surface mobility. We also present a thorough experimental study of the mobility in thin film SOI MOSFET's, in the temperature range 298-623K. All data agree with the theoretical model, which may thus be used for a physical interpretation of the results from room to high temperature.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125640398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ipposhi, T. Iwamatsu, Y. Yamaguchi, K. Ueda, H. Morinaka, K. Mashiko, Y. Inoue, T. Hirao
Thin-film SOI MOSFETs offer high-speed and low-power characteristics due to reduced junction capacitance and reduced back-gate-bias effect. Therefore, thin SOI devices have been considered to be candidates for element transistor structures used in high-speed and low-power CMOS LSIs. In order to proceed to the stage of commercial application, it is necessary to demonstrate the effectiveness of SOI devices in various kinds of practical circuits. In this paper, we report an advanced 0.5 /spl mu/m CMOS/SOI technology and demonstrate ultrahigh-speed and low-power operation in two kinds of typical circuits: frequency divider and adder.
薄膜SOI mosfet由于减少了结电容和减少了后门偏置效应而具有高速和低功耗的特性。因此，薄SOI器件被认为是用于高速和低功耗CMOS lsi的元件晶体管结构的候选器件。为了进入商业应用阶段，有必要在各种实际电路中证明SOI器件的有效性。在本文中，我们报道了一种先进的0.5 /spl μ m CMOS/SOI技术，并演示了两种典型电路:分频器和加法器的超高速低功耗工作。
{"title":"An advanced 0.5 /spl mu/m CMOS/SOI technology for practical ultrahigh-speed and low-power circuits","authors":"T. Ipposhi, T. Iwamatsu, Y. Yamaguchi, K. Ueda, H. Morinaka, K. Mashiko, Y. Inoue, T. Hirao","doi":"10.1109/SOI.1995.526453","DOIUrl":"https://doi.org/10.1109/SOI.1995.526453","url":null,"abstract":"Thin-film SOI MOSFETs offer high-speed and low-power characteristics due to reduced junction capacitance and reduced back-gate-bias effect. Therefore, thin SOI devices have been considered to be candidates for element transistor structures used in high-speed and low-power CMOS LSIs. In order to proceed to the stage of commercial application, it is necessary to demonstrate the effectiveness of SOI devices in various kinds of practical circuits. In this paper, we report an advanced 0.5 /spl mu/m CMOS/SOI technology and demonstrate ultrahigh-speed and low-power operation in two kinds of typical circuits: frequency divider and adder.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127182185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There are still important issues that remain on the microstructure of low-dose SIMOX that may affect its quality and performance as an SOI material. These issues include the presence of crystalline defects in the top Si layer and the presence of Si islands in the buried oxide (BOX) which can severely degrade dielectric properties. While the reasons for crystalline defect formation have been recently determined, the mechanism(s) of Si island formation in the BOX are still unclear. Such understanding could assist in improved processing for fabricating high quality BOX layers in low-dose SIMOX. In this paper we report on the effect of implant dose on the microstructural changes found during Si island formation.
{"title":"Effect of implant dose on formation of buried-oxide Si islands in low-dose SIMOX","authors":"S. Bagchi, J.D. Lee, S. Krause, P. Roitman","doi":"10.1109/SOI.1995.526489","DOIUrl":"https://doi.org/10.1109/SOI.1995.526489","url":null,"abstract":"There are still important issues that remain on the microstructure of low-dose SIMOX that may affect its quality and performance as an SOI material. These issues include the presence of crystalline defects in the top Si layer and the presence of Si islands in the buried oxide (BOX) which can severely degrade dielectric properties. While the reasons for crystalline defect formation have been recently determined, the mechanism(s) of Si island formation in the BOX are still unclear. Such understanding could assist in improved processing for fabricating high quality BOX layers in low-dose SIMOX. In this paper we report on the effect of implant dose on the microstructural changes found during Si island formation.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Since the interconnect capacitance almost maintains the same level even with shrinking device dimension, high current drive of a transistor is required for ultra-high speed operation. Although the ultra-thin SOI MOSFET is a promising candidate for ultra-small devices, its enormous parasitic resistance is a significant problem. The reduction of the parasitic resistance is a key issue in achieving high-performance ultra-thin SOI devices. In this study, a lateral contact structure, unique to SOI devices, with ultra-low contact resistance, is proposed for realizing ultimate low parasitic resistance.
{"title":"Minimum parasitic resistance for ultra-thin SOI MOSFET with high-permittivity gate insulator performed by lateral contact structure","authors":"H. Shimada, T. Ohmi","doi":"10.1109/SOI.1995.526479","DOIUrl":"https://doi.org/10.1109/SOI.1995.526479","url":null,"abstract":"Since the interconnect capacitance almost maintains the same level even with shrinking device dimension, high current drive of a transistor is required for ultra-high speed operation. Although the ultra-thin SOI MOSFET is a promising candidate for ultra-small devices, its enormous parasitic resistance is a significant problem. The reduction of the parasitic resistance is a key issue in achieving high-performance ultra-thin SOI devices. In this study, a lateral contact structure, unique to SOI devices, with ultra-low contact resistance, is proposed for realizing ultimate low parasitic resistance.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114409416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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