Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614538
Z. Song, D. Cai, X. Li, L. Wang, Yuxiang Chen, H. P. Chen, Q. Wang, Y. Zhan, M. Ji
In this work, we present the results of a highly reliable phase change memory (PCM) based on Carbon-doped Ge2Sb2Te5- material in 40 nm node. The large Reset/Set resistance ratio of more than 2 orders of magnitude is achieved. The chip exhibits excellent data retention, endurance characteristics, and the sensing window is even larger after 260°C soldering test. It is estimated that the PCM could retain data for 10 years at 128°C. In a 128 Mb test chip over 108 cycles is achieved. PCM is suitable for applications requiring high thermal stability and cycling endurance.
{"title":"High Endurance Phase Change Memory Chip Implemented based on Carbon-doped Ge2Sb2Te5 in 40 nm Node for Embedded Application","authors":"Z. Song, D. Cai, X. Li, L. Wang, Yuxiang Chen, H. P. Chen, Q. Wang, Y. Zhan, M. Ji","doi":"10.1109/IEDM.2018.8614538","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614538","url":null,"abstract":"In this work, we present the results of a highly reliable phase change memory (PCM) based on Carbon-doped Ge2Sb2Te5- material in 40 nm node. The large Reset/Set resistance ratio of more than 2 orders of magnitude is achieved. The chip exhibits excellent data retention, endurance characteristics, and the sensing window is even larger after 260°C soldering test. It is estimated that the PCM could retain data for 10 years at 128°C. In a 128 Mb test chip over 108 cycles is achieved. PCM is suitable for applications requiring high thermal stability and cycling endurance.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115628180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614624
R. Pillarisetty, N. Thomas, H. George, K. Singh, J. Roberts, L. Lampert, P. Amin, T. Watson, G. Zheng, J. Torres, M. Metz, R. Kotlyar, P. Keys, J. Boter, J. P. Dehollain, G. Droulers, G. Eenink, R. Li, L. Massa, D. Sabbagh, N. Samkharadze, C. Volk, B. P. Wuetz, A. Zwerver, M. Veldhorst, G. Scappucci, L. Vandersypen, J. Clarke
Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a 28Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots
{"title":"Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology","authors":"R. Pillarisetty, N. Thomas, H. George, K. Singh, J. Roberts, L. Lampert, P. Amin, T. Watson, G. Zheng, J. Torres, M. Metz, R. Kotlyar, P. Keys, J. Boter, J. P. Dehollain, G. Droulers, G. Eenink, R. Li, L. Massa, D. Sabbagh, N. Samkharadze, C. Volk, B. P. Wuetz, A. Zwerver, M. Veldhorst, G. Scappucci, L. Vandersypen, J. Clarke","doi":"10.1109/IEDM.2018.8614624","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614624","url":null,"abstract":"Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a 28Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614604
Fan Ye, Jaesung Lee, P. Feng
We report on the first experimental demonstration of electrothermally tuned few-layer graphene resonant nanoelectromechanical systems (NEMS) operating at high and very high frequency (HF/VHF) simultaneously with strong visible light emission. In tri-layer graphene resonators with carefully controlled Joule heating, we have demonstrated ultra-wide frequency tuning up to $Delta f/f_{0}approx 1300%$, which is the highest frequency tuning range known to date among reported 2D materials resonators. Simultaneously, device temperature variations imposed by Joule heating are monitored using Raman spectroscopy and emission spectrum; and we find that the device temperature increases from 300K up to 2650K, which is the highest operating temperature known to date for electromechanical resonators. When device temperature is above 1800K, the vibrating graphene NEMS starts glowing and emitting visible light with robust mechanical resonance. These results show that electromechanical resonance modes can be robustly sustained and read out at glowing temperatures with incandescent emission in graphene NEMS, suggesting new perspectives for integrating and configuring timing functions in light emitting graphene devices for harsh and extreme environment applications.
{"title":"Glowing Graphene Nanoelectromechanical Resonators at Ultra-High Temperature up to 2650K","authors":"Fan Ye, Jaesung Lee, P. Feng","doi":"10.1109/IEDM.2018.8614604","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614604","url":null,"abstract":"We report on the first experimental demonstration of electrothermally tuned few-layer graphene resonant nanoelectromechanical systems (NEMS) operating at high and very high frequency (HF/VHF) simultaneously with strong visible light emission. In tri-layer graphene resonators with carefully controlled Joule heating, we have demonstrated ultra-wide frequency tuning up to $Delta f/f_{0}approx 1300%$, which is the highest frequency tuning range known to date among reported 2D materials resonators. Simultaneously, device temperature variations imposed by Joule heating are monitored using Raman spectroscopy and emission spectrum; and we find that the device temperature increases from 300K up to 2650K, which is the highest operating temperature known to date for electromechanical resonators. When device temperature is above 1800K, the vibrating graphene NEMS starts glowing and emitting visible light with robust mechanical resonance. These results show that electromechanical resonance modes can be robustly sustained and read out at glowing temperatures with incandescent emission in graphene NEMS, suggesting new perspectives for integrating and configuring timing functions in light emitting graphene devices for harsh and extreme environment applications.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126148319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614703
Xiuyan Li, A. Toriumi
Steep subthreshold swing (SS) in ferroelectric (FE) FETs have been intensively discussed these years in terms of the negative capacitance(NC) effect, but still under debate. This paper demonstrates the direct correlation between sub-60 mV/dec SS and internal potential $(V_{int})$ enhancement in MOSFET externally connected to FE capacitor in DC mode through systematic experiments. It is shown that $V_{int}$ enhancement only occurs in a limited voltage window, and that hysteresis-free steep SS is achievable by tuning the paraelectric capacitance. The present results support that the steep SS values so far reported are tightly related to FE domain switching around the coercive field rather than the ideal NC effect.
{"title":"Direct relationship between sub-60 mV/dec subthreshold swing and internal potential instability in MOSFET externally connected to ferroelectric capacitor","authors":"Xiuyan Li, A. Toriumi","doi":"10.1109/IEDM.2018.8614703","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614703","url":null,"abstract":"Steep subthreshold swing (SS) in ferroelectric (FE) FETs have been intensively discussed these years in terms of the negative capacitance(NC) effect, but still under debate. This paper demonstrates the direct correlation between sub-60 mV/dec SS and internal potential $(V_{int})$ enhancement in MOSFET externally connected to FE capacitor in DC mode through systematic experiments. It is shown that $V_{int}$ enhancement only occurs in a limited voltage window, and that hysteresis-free steep SS is achievable by tuning the paraelectric capacitance. The present results support that the steep SS values so far reported are tightly related to FE domain switching around the coercive field rather than the ideal NC effect.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124726039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614551
Jianshi Tang, Douglas M. Bishop, Seyoung Kim, M. Copel, T. Gokmen, T. Todorov, SangHoon Shin, Ko-Tao Lee, P. Solomon, Kevin K. H. Chan, W. Haensch, J. Rozen
We demonstrate a nonvolatile Electro-Chemical Random-Access Memory (ECRAM) based on lithium (Li) ion intercalation in tungsten oxide (WO3) for high-speed, low-power neuromorphic computing. Symmetric and linear update on the channel conductance is achieved using gate current pulses, where up to 1000 discrete states with large dynamic range and good retention are demonstrated. MNIST simulation based on the experimental data shows an accuracy of 96%. For the first time, high-speed programming with pulse width down to 5 ns and device operation at scales down to $300times 300 text{nm}^{2}$ are shown, confirming the technological relevance of ECRAM for neuromorphic array implementation. It is also verified that the conductance change scales linearly with pulse width, amplitude and charge, projecting an ultralow switching energy ∼1 fJ for $100times 100 text{nm}^{2}$ devices.
{"title":"ECRAM as Scalable Synaptic Cell for High-Speed, Low-Power Neuromorphic Computing","authors":"Jianshi Tang, Douglas M. Bishop, Seyoung Kim, M. Copel, T. Gokmen, T. Todorov, SangHoon Shin, Ko-Tao Lee, P. Solomon, Kevin K. H. Chan, W. Haensch, J. Rozen","doi":"10.1109/IEDM.2018.8614551","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614551","url":null,"abstract":"We demonstrate a nonvolatile Electro-Chemical Random-Access Memory (ECRAM) based on lithium (Li) ion intercalation in tungsten oxide (WO3) for high-speed, low-power neuromorphic computing. Symmetric and linear update on the channel conductance is achieved using gate current pulses, where up to 1000 discrete states with large dynamic range and good retention are demonstrated. MNIST simulation based on the experimental data shows an accuracy of 96%. For the first time, high-speed programming with pulse width down to 5 ns and device operation at scales down to $300times 300 text{nm}^{2}$ are shown, confirming the technological relevance of ECRAM for neuromorphic array implementation. It is also verified that the conductance change scales linearly with pulse width, amplitude and charge, projecting an ultralow switching energy ∼1 fJ for $100times 100 text{nm}^{2}$ devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115107466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614714
B. Mahajan, Yen-Pu Chen, W. Ahn, N. Zagni, M. Alam
Despite exceeding the Baliga's Figure of Merit (BFOM) by 400% and Huang's Chip Area Manufacturing FOM (HCAFOM) by 330% [1], the performance of existing $beta$-Ga2O3 FETs is inferior to that of GaN, primarily due to extreme self-heating. Self-heating effect (SHE) has emerged as an important concern for device performance, output power density, run-time variability and reliability for modern logic transistors. The effects are even more severe for high-power transistor where the channel material may be a poor thermal conductor, e.g. $beta$-Ga2O3. Very high internal electric fields, extreme temperature and mechanical stresses associated with these transistors drive electrochemical reactions [2], influence atomic processes [3], and accelerate multiple non-equilibrium effects [4]. A device-circuit-package, multi-physics, multi-scale simulation is needed to capture these effects self-consistently, but such a model has not yet been developed. In this paper, we (i) develop the first self-consistent device (TCAD), circuit (HSPICE), and package (COMSOL) model considering SHE which predicts FET performance on variety of substrates accurately; (ii) use the model to propose a novel hexagonal-Boron Nitride (h-BN) based $beta$-Ga2O3 FET with 30% (cf. Sapphire substrate) and 80% (cf. SiO2 substrate) reduction in thermal resistance $(R_{th})$; (iii) demonstrate the performance of boost converter (with parameters extracted from our TCAD model) with h-BN based $beta$-Ga2O3 FET, which outperforms the existing $beta$-Ga2O3 FETs, achieving an efficiency within 10-15% of highest performing enhancement mode (E-mode) GaN FET; (iv) propose h-BN based FinFET which exceeds the ION of the existing $beta$-Ga2O3 FET by more than 500%; and (v) develop a Faraday-cage type novel packaging strategy for effective heat dissipation and efficient system performance in $beta$-Ga2O3 FETs.
{"title":"Design and Optimization of $boldsymbol{beta}$-Ga2O3 on (h-BN layered) Sapphire for High Efficiency Power Transistors: A Device-Circuit-Package Perspective","authors":"B. Mahajan, Yen-Pu Chen, W. Ahn, N. Zagni, M. Alam","doi":"10.1109/IEDM.2018.8614714","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614714","url":null,"abstract":"Despite exceeding the Baliga's Figure of Merit (BFOM) by 400% and Huang's Chip Area Manufacturing FOM (HCAFOM) by 330% [1], the performance of existing <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> FETs is inferior to that of GaN, primarily due to extreme self-heating. Self-heating effect (SHE) has emerged as an important concern for device performance, output power density, run-time variability and reliability for modern logic transistors. The effects are even more severe for high-power transistor where the channel material may be a poor thermal conductor, e.g. <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf>. Very high internal electric fields, extreme temperature and mechanical stresses associated with these transistors drive electrochemical reactions [2], influence atomic processes [3], and accelerate multiple non-equilibrium effects [4]. A device-circuit-package, multi-physics, multi-scale simulation is needed to capture these effects self-consistently, but such a model has not yet been developed. In this paper, we (i) develop the first self-consistent device (TCAD), circuit (HSPICE), and package (COMSOL) model considering SHE which predicts FET performance on variety of substrates accurately; (ii) use the model to propose a novel hexagonal-Boron Nitride (h-BN) based <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> FET with 30% (cf. Sapphire substrate) and 80% (cf. SiO<inf>2</inf> substrate) reduction in thermal resistance <tex>$(R_{th})$</tex>; (iii) demonstrate the performance of boost converter (with parameters extracted from our TCAD model) with h-BN based <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> FET, which outperforms the existing <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> FETs, achieving an efficiency within 10-15% of highest performing enhancement mode (E-mode) GaN FET; (iv) propose h-BN based FinFET which exceeds the I<inf>ON</inf> of the existing <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> FET by more than 500%; and (v) develop a Faraday-cage type novel packaging strategy for effective heat dissipation and efficient system performance in <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> FETs.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"414 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124808621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614553
P. Sung, C. Chang, L. Chen, K. Kao, C. Su, Tzu-Han Liao, C.-C. Fang, C. Wang, T. Hong, Che-Yu Jao, Hui-Shun Hsu, S. Luo, Y.-S. Wang, H.-F. Huang, J. Li, Y. Huang, F. Hsueh, C. Wu, Y.-M. Huang, F. Hou, G. Luo, Y. Huang, Y.-L. Shen, W. C. Ma, K. Huang, K. Lin, S. Samukawa, Y. Li, G. Huang, Y. Lee, J.-Y. Li, W. Wu, J. Shieh, T. Chao, W. Yeh, Y. Wang
For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.
{"title":"Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications","authors":"P. Sung, C. Chang, L. Chen, K. Kao, C. Su, Tzu-Han Liao, C.-C. Fang, C. Wang, T. Hong, Che-Yu Jao, Hui-Shun Hsu, S. Luo, Y.-S. Wang, H.-F. Huang, J. Li, Y. Huang, F. Hsueh, C. Wu, Y.-M. Huang, F. Hou, G. Luo, Y. Huang, Y.-L. Shen, W. C. Ma, K. Huang, K. Lin, S. Samukawa, Y. Li, G. Huang, Y. Lee, J.-Y. Li, W. Wu, J. Shieh, T. Chao, W. Yeh, Y. Wang","doi":"10.1109/IEDM.2018.8614553","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614553","url":null,"abstract":"For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121673970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614589
K. Pradeep, T. Poiroux, P. Scheer, A. Juge, G. Gouget, G. Ghibaudo
A unified, industrially compatible methodology to characterize and model in-wafer variability at different spatial scales, with addressable array test structures is proposed. Using a physics-based compact model, a single statistical model for both local and global variability is developed for the first time. The proposed method and model are validated using 28 nm FD-SOI devices and the dependence of dominant sources of variability on bias and device geometry is evaluated.
{"title":"Characterization Methodology and Physical Compact Modeling of in-Wafer Global and Local Variability","authors":"K. Pradeep, T. Poiroux, P. Scheer, A. Juge, G. Gouget, G. Ghibaudo","doi":"10.1109/IEDM.2018.8614589","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614589","url":null,"abstract":"A unified, industrially compatible methodology to characterize and model in-wafer variability at different spatial scales, with addressable array test structures is proposed. Using a physics-based compact model, a single statistical model for both local and global variability is developed for the first time. The proposed method and model are validated using 28 nm FD-SOI devices and the dependence of dominant sources of variability on bias and device geometry is evaluated.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131541707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614635
Y. Song, J. Lee, Sung-hee Han, H. Shin, K. H. Lee, K. Suh, D. Jeong, G. Koh, Sechung Oh, Joon-Min Park, Soojeoung Park, B. Bae, O. I. Kwon, K. Hwang, Bum-seok Seo, You Kyoung Lee, S. Hwang, Dongsoo Lee, Y. Ji, Kyu-Charn Park, G. Jeong, Hyunju Hong, K. Lee, H. K. Kang, E. Jung
We successfully demonstrated the manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform by achieving stable functionality and robust package level reliability. Read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology. Write margin was also increased by improving the efficiency using novel integration process. Its product reliability was confirmed in package level with passing HTOL 1000 hours tests, 106 endurance test, and retention test. For a wider application, we also demonstrated the feasibility of high density 128Mb STT-MRAM. Based on these results, we clearly verified the product manufacturability of embedded STT-MRAM.
{"title":"Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic","authors":"Y. Song, J. Lee, Sung-hee Han, H. Shin, K. H. Lee, K. Suh, D. Jeong, G. Koh, Sechung Oh, Joon-Min Park, Soojeoung Park, B. Bae, O. I. Kwon, K. Hwang, Bum-seok Seo, You Kyoung Lee, S. Hwang, Dongsoo Lee, Y. Ji, Kyu-Charn Park, G. Jeong, Hyunju Hong, K. Lee, H. K. Kang, E. Jung","doi":"10.1109/IEDM.2018.8614635","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614635","url":null,"abstract":"We successfully demonstrated the manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform by achieving stable functionality and robust package level reliability. Read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology. Write margin was also increased by improving the efficiency using novel integration process. Its product reliability was confirmed in package level with passing HTOL 1000 hours tests, 106 endurance test, and retention test. For a wider application, we also demonstrated the feasibility of high density 128Mb STT-MRAM. Based on these results, we clearly verified the product manufacturability of embedded STT-MRAM.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126466568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614626
Xu Wang, A. Toriumi
This paper reports for the first time a new kinetic model of thermal oxidation of Ge that considers both O-vacancy and atomic O diffusion as a function of O2 pressure. The model is based on newly obtained results that Ge oxidation is described by kinetics completely different from the Deal-Grove model and that it exhibits anomalous O2 pressure dependence. Furthermore, new experimental results have been obtained in the oxidation of SiO2/GeO2/Ge, GeO2/SiO2/Si and GeO2/SiO2/Ge stacks. They also strongly support new kinetic model of Ge oxidation. This is critically important for high quality Ge gate stacks, as the Deal-Grove model have played a significant role in Si technology.
{"title":"Why GeO2 growth on Ge is suppressed and GeO2/Ge stack is much improved in high pressure O2 oxidation?","authors":"Xu Wang, A. Toriumi","doi":"10.1109/IEDM.2018.8614626","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614626","url":null,"abstract":"This paper reports for the first time a new kinetic model of thermal oxidation of Ge that considers both O-vacancy and atomic O diffusion as a function of O<inf>2</inf> pressure. The model is based on newly obtained results that Ge oxidation is described by kinetics completely different from the Deal-Grove model and that it exhibits anomalous O<inf>2</inf> pressure dependence. Furthermore, new experimental results have been obtained in the oxidation of SiO<inf>2</inf>/GeO<inf>2</inf>/Ge, GeO<inf>2</inf>/SiO<inf>2</inf>/Si and GeO<inf>2</inf>/SiO<inf>2</inf>/Ge stacks. They also strongly support new kinetic model of Ge oxidation. This is critically important for high quality Ge gate stacks, as the Deal-Grove model have played a significant role in Si technology.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131834739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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