Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614655
Lingfei Wang, Lin Wang, K. Ang, A. Thean, G. Liang
For the first time, a surface potential- and physics-based compact model for two dimensional (2D) polycrystalline-molybdenum disulfide (MoS2) field effect transistors (FETs) with resistive switching (RS) behavior is developed and verified by experimental data. This model is incorporated with the theories of thermal activation transport, grain boundary (GB) barrier and space charge limited current (SCLC). Based on the GB induced disorders, the grain size, low temperature and high electrical field dependent characteristics are studied. The predicted transfer and output characteristics have excellent quantitative agreement with experimental results. Furthermore, considering the hopping process induced defect- (i.e., sulfur vacancy) redistribution, the GB (e.g., intersecting or bisecting GB) dependent resistive switching behavior is physically investigated. Finally, this model is implemented to simulate the synaptic activity such as short-term/long-term plasticity, which indicates the possibility of using 2D-FETs for neuromorphic computing applications.
{"title":"A Surface Potential- and Physics- Based Compact Model for 2D Polycrystalline-MoS2FET with Resistive Switching Behavior in Neuromorphic Computing","authors":"Lingfei Wang, Lin Wang, K. Ang, A. Thean, G. Liang","doi":"10.1109/IEDM.2018.8614655","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614655","url":null,"abstract":"For the first time, a surface potential- and physics-based compact model for two dimensional (2D) polycrystalline-molybdenum disulfide (MoS2) field effect transistors (FETs) with resistive switching (RS) behavior is developed and verified by experimental data. This model is incorporated with the theories of thermal activation transport, grain boundary (GB) barrier and space charge limited current (SCLC). Based on the GB induced disorders, the grain size, low temperature and high electrical field dependent characteristics are studied. The predicted transfer and output characteristics have excellent quantitative agreement with experimental results. Furthermore, considering the hopping process induced defect- (i.e., sulfur vacancy) redistribution, the GB (e.g., intersecting or bisecting GB) dependent resistive switching behavior is physically investigated. Finally, this model is implemented to simulate the synaptic activity such as short-term/long-term plasticity, which indicates the possibility of using 2D-FETs for neuromorphic computing applications.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130568947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614487
T. Miyashita, Shiyu Sun, Sushant Mittal, M. Kim, A. Pal, A. Sachid, Kalpana Pathak, M. Cogorno, Namsung Kim
Selective fin trimming after dummy gate removal is proposed as the local fin width scaling approach for further FinFET extension. In this approach, local fin trimming is selectively performed for the channel region after dummy gate removal in the replacement metal gate (RMG) module while preserving the original source and drain (S/D) fin width, in order to avoid the parasitic resistance increase that results from the global fin trimming approach. TCAD simulation shows clearly that the local fin trimming can improve gate electrostatics with narrower fins, while also providing the benefits of lower S/D resistance and PMOS high channel stress. Although, fin height reduction and parasitic capacitance increases are not preferable, overall gate delay is improved due to strong $I_{text{on}}-I_{text{off}}$ boost. Selectra™ etch fin trimming results are also presented demonstrating good fin width controllability and smaller variations without any critical fin damages. This local fin trimming is promising for N5 and beyond to further extend FinFET technology.
{"title":"Selective Fin Trimming after Dummy Gate Removal as the Local Fin Width Scaling Approach for N5 and Beyond","authors":"T. Miyashita, Shiyu Sun, Sushant Mittal, M. Kim, A. Pal, A. Sachid, Kalpana Pathak, M. Cogorno, Namsung Kim","doi":"10.1109/IEDM.2018.8614487","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614487","url":null,"abstract":"Selective fin trimming after dummy gate removal is proposed as the local fin width scaling approach for further FinFET extension. In this approach, local fin trimming is selectively performed for the channel region after dummy gate removal in the replacement metal gate (RMG) module while preserving the original source and drain (S/D) fin width, in order to avoid the parasitic resistance increase that results from the global fin trimming approach. TCAD simulation shows clearly that the local fin trimming can improve gate electrostatics with narrower fins, while also providing the benefits of lower S/D resistance and PMOS high channel stress. Although, fin height reduction and parasitic capacitance increases are not preferable, overall gate delay is improved due to strong $I_{text{on}}-I_{text{off}}$ boost. Selectra™ etch fin trimming results are also presented demonstrating good fin width controllability and smaller variations without any critical fin damages. This local fin trimming is promising for N5 and beyond to further extend FinFET technology.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614565
S. Iida, Y. Sakano, T. Asatsuma, M. Takami, I. Yoshiba, N. Ohba, H. Mizuno, T. Oka, K. Yamaguchi, A. Suzuki, K. Suzuki, M. Yamada, M. Takizawa, Y. Tateshita, K. Ohno
This is a report of a CMOS image sensor with a sub-pixel architecture having a pixel pitch of 3 um. The aforementioned sensor achieves both ultra-low random noise of 0.68e-rms and high dynamic range of 121 dB in a single exposure, further realizing LED flicker mitigation.
{"title":"A 0.68e-rms Random-Noise 121dB Dynamic-Range Sub-pixel architecture CMOS Image Sensor with LED Flicker Mitigation","authors":"S. Iida, Y. Sakano, T. Asatsuma, M. Takami, I. Yoshiba, N. Ohba, H. Mizuno, T. Oka, K. Yamaguchi, A. Suzuki, K. Suzuki, M. Yamada, M. Takizawa, Y. Tateshita, K. Ohno","doi":"10.1109/IEDM.2018.8614565","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614565","url":null,"abstract":"This is a report of a CMOS image sensor with a sub-pixel architecture having a pixel pitch of 3 um. The aforementioned sensor achieves both ultra-low random noise of 0.68e-rms and high dynamic range of 121 dB in a single exposure, further realizing LED flicker mitigation.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115077254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614611
Xiaoyu Sun, Panni Wang, K. Ni, S. Datta, Shimeng Yu
In-memory computing with analog non-volatile memories (NVMs) can accelerate both the in-situ training and inference of deep neural networks (DNNs) by parallelizing multiply-accumulate (MAC) operations in the analog domain. However, the in-situ training accuracy suffers from unacceptable degradation due to undesired weight-update asymmetry/nonlinearity and limited bit precision. In this work, we overcome this challenge by introducing a compact Ferroelectric FET (FeFET) based synaptic cell that exploits hybrid precision for in-situ training and inference. We propose a novel hybrid approach where we use modulated “volatile” gate voltage of FeFET to represent the least significant bits (LSBs) for symmetric/linear update during training only, and use “non-volatile” polarization states of FeFET to hold the information of most significant bits (MSBs) for inference. This design is demonstrated by the experimentally validated FeFET SPICE model and cosimulation with the TensorFlow framework. The results show that with the proposed 6-bit and 7-bit synapse design, the insitu training accuracy can achieve ∼97.3% on MNIST dataset and ∼87% on CIFAR-10 dataset, respectively, approaching the ideal software based training.
{"title":"Exploiting Hybrid Precision for Training and Inference: A 2T-1FeFET Based Analog Synaptic Weight Cell","authors":"Xiaoyu Sun, Panni Wang, K. Ni, S. Datta, Shimeng Yu","doi":"10.1109/IEDM.2018.8614611","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614611","url":null,"abstract":"In-memory computing with analog non-volatile memories (NVMs) can accelerate both the in-situ training and inference of deep neural networks (DNNs) by parallelizing multiply-accumulate (MAC) operations in the analog domain. However, the in-situ training accuracy suffers from unacceptable degradation due to undesired weight-update asymmetry/nonlinearity and limited bit precision. In this work, we overcome this challenge by introducing a compact Ferroelectric FET (FeFET) based synaptic cell that exploits hybrid precision for in-situ training and inference. We propose a novel hybrid approach where we use modulated “volatile” gate voltage of FeFET to represent the least significant bits (LSBs) for symmetric/linear update during training only, and use “non-volatile” polarization states of FeFET to hold the information of most significant bits (MSBs) for inference. This design is demonstrated by the experimentally validated FeFET SPICE model and cosimulation with the TensorFlow framework. The results show that with the proposed 6-bit and 7-bit synapse design, the insitu training accuracy can achieve ∼97.3% on MNIST dataset and ∼87% on CIFAR-10 dataset, respectively, approaching the ideal software based training.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130962574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614673
M. Popovici, A. Belmonte, H. Oh, G. Potoms, J. Meersschaut, O. Richard, H. Hody, S. Van Elshocht, R. Delhougne, L. Goux, G. Kar
We demonstrate the fabrication of strontium titanate (STO) based metal-insulator-metal (MIM) capacitors with very-high dielectric constant (k∼118) and low leakage of 10−7 A/cm2 at ±1V for a ∼11nm thick dielectric using Ru as bottom electrode (BE) and top electrode (TE). The k enhancement is attributed to the formation of an ultrathin cubic SrRuO3 phase at the Ru/STO bottom interface, acting as a template optimizing the STO crystal quality from the interface to the bulk. This interface quality is evidenced by the same k∼118 extracted from STO thickness series and relating to the bulk-k value. This achievement opens up an alternative integration roadmap for DRAM capacitors, moving from the current cup-shape to a denser pillar-shape design.
{"title":"High-performance ($text{EOT} < 0.4text{nm}$, Jg∼10−7 A/cm2) ALD-deposited RuSrTiO3 stack for next generations DRAM pillar capacitor","authors":"M. Popovici, A. Belmonte, H. Oh, G. Potoms, J. Meersschaut, O. Richard, H. Hody, S. Van Elshocht, R. Delhougne, L. Goux, G. Kar","doi":"10.1109/IEDM.2018.8614673","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614673","url":null,"abstract":"We demonstrate the fabrication of strontium titanate (STO) based metal-insulator-metal (MIM) capacitors with very-high dielectric constant (k∼118) and low leakage of 10−7 A/cm2 at ±1V for a ∼11nm thick dielectric using Ru as bottom electrode (BE) and top electrode (TE). The k enhancement is attributed to the formation of an ultrathin cubic SrRuO3 phase at the Ru/STO bottom interface, acting as a template optimizing the STO crystal quality from the interface to the bulk. This interface quality is evidenced by the same k∼118 extracted from STO thickness series and relating to the bulk-k value. This achievement opens up an alternative integration roadmap for DRAM capacitors, moving from the current cup-shape to a denser pillar-shape design.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132157547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614674
N. Miyata, J. Nara, T. Yamasaki, K. Sumita, R. Sano, H. Nohira
We report an electric-field-induced interface dipole modulation (IDM) in HfO2/1-ML TiO2/SiO2 MOS stack structures. Experimental evidence for IDM was exhibited, and rearrangement of interfacial Ti-O configuration by an electric field was theoretically demonstrated to cause the potential modulation. Multi-stack HfO2/SiO2 MOSFETs with multiple dipole modulation layers are promising in terms of a low temperature process, practical memory window, and stable potential switching.
{"title":"Interface Dipole Modulation in HfO2/SiO2 MOS Stack Structures","authors":"N. Miyata, J. Nara, T. Yamasaki, K. Sumita, R. Sano, H. Nohira","doi":"10.1109/IEDM.2018.8614674","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614674","url":null,"abstract":"We report an electric-field-induced interface dipole modulation (IDM) in HfO<inf>2</inf>/1-ML TiO<inf>2</inf>/SiO<inf>2</inf> MOS stack structures. Experimental evidence for IDM was exhibited, and rearrangement of interfacial Ti-O configuration by an electric field was theoretically demonstrated to cause the potential modulation. Multi-stack HfO<inf>2</inf>/SiO<inf>2</inf> MOSFETs with multiple dipole modulation layers are promising in terms of a low temperature process, practical memory window, and stable potential switching.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132239135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614669
T. Maeda, T. Narita, Hiroyuki Ueda, M. Kanechika, T. Uesugi, T. Kachi, T. Kimoto, M. Horita, Jun Suda
We report homoepitaxial GaN p-n junction diodes with novel beveled-mesa structures. The n-layers and p-layers, the doping concentrations of which are comparable, were prepared. We found that electric field crowding does not occur in the structure using TCAD simulation. The fabricated devices showed the breakdown voltages of 180–480 V, small leakage currents, and excellent avalanche capabilities. The breakdown voltages increased at elevated temperature. At the breakdown, nearly uniform luminescence in the entire p-n junctions was observed in all the devices. These results are strong evidences that the uniform avalanche breakdowns occurred in the devices. We carefully characterized the depletion layer width at the breakdown, and the parallel-plane breakdown electric fields of 2.8-3.5 MV/cm were obtained, which are among the best of the reported non-punch-through GaN vertical devices.
{"title":"Parallel-Plane Breakdown Fields of 2.8-3.5 MV/cm in GaN-on-GaN p-n Junction Diodes with Double-Side-Depleted Shallow Bevel Termination","authors":"T. Maeda, T. Narita, Hiroyuki Ueda, M. Kanechika, T. Uesugi, T. Kachi, T. Kimoto, M. Horita, Jun Suda","doi":"10.1109/IEDM.2018.8614669","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614669","url":null,"abstract":"We report homoepitaxial GaN p-n junction diodes with novel beveled-mesa structures. The n-layers and p-layers, the doping concentrations of which are comparable, were prepared. We found that electric field crowding does not occur in the structure using TCAD simulation. The fabricated devices showed the breakdown voltages of 180–480 V, small leakage currents, and excellent avalanche capabilities. The breakdown voltages increased at elevated temperature. At the breakdown, nearly uniform luminescence in the entire p-n junctions was observed in all the devices. These results are strong evidences that the uniform avalanche breakdowns occurred in the devices. We carefully characterized the depletion layer width at the breakdown, and the parallel-plane breakdown electric fields of 2.8-3.5 MV/cm were obtained, which are among the best of the reported non-punch-through GaN vertical devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130247477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614485
S. Migita, H. Ota, A. Toriumi
Steep-subthreshold swing ($SS$) behaviors in ferroelectric-gate field-effect transistors (Fe-FETs) are investigated using the metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gates stack structures with different area ratios between MIS and MFM capacitors. It is analyzed that the capacitance matching between them by adjusting the area ratio is significant to efficiently utilize the polarization reversal behavior in the ferroelectric layer. In this work we explain the steep-SS behavior from viewpoint of positive feedback of polarization reversal. Furthermore it is discussed why steep-SS is observable in recent Fe-FETs.
{"title":"Assessment of Steep-Subthreshold Swing Behaviors in Ferroelectric-Gate Field-Effect Transistors Caused by Positive Feedback of Polarization Reversal","authors":"S. Migita, H. Ota, A. Toriumi","doi":"10.1109/IEDM.2018.8614485","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614485","url":null,"abstract":"Steep-subthreshold swing ($SS$) behaviors in ferroelectric-gate field-effect transistors (Fe-FETs) are investigated using the metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gates stack structures with different area ratios between MIS and MFM capacitors. It is analyzed that the capacitance matching between them by adjusting the area ratio is significant to efficiently utilize the polarization reversal behavior in the ferroelectric layer. In this work we explain the steep-SS behavior from viewpoint of positive feedback of polarization reversal. Furthermore it is discussed why steep-SS is observable in recent Fe-FETs.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"234 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114207384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614693
Wenshen Li, Zongyang Hu, K. Nomoto, R. Jinno, Zexuan Zhang, Thieu Quang Tu, K. Sasaki, A. Kuramata, D. Jena, H. Xing
High-performance $beta$-Ga203 vertical trench Schottky barrier diodes (SBDs) are demonstrated on bulk Ga2O3 substrates with a halide vapor phase epitaxial layer. A breakdown voltage (BV) of 2.44 kV, Baliga's figure-of-merit (BV2/Ron) of 0.39 GW/cm2 from DC measurements and 0.45 GW/cm2 from pulsed measurements are achieved, all of which are the highest among $beta$-Ga2O3-based power devices. A lowest reverse leakage current density below $1 mu mathrm{A}/text{cm}^{2}$ until breakdown is observed on devices with a fin width of $1-2 mu mathrm{m}$, thanks to the reduced surface field (RESURF) effect provided by the trench SBD structure. The specific on-resistance is found to reduce with increasing area ratio of the fin-channels following a simple relationship. The reverse leakage current agrees well with simulated results considering the barrier tunneling and barrier height lowering effects. The breakdown of the devices is identified to happen at the trench bottom corner, where a maximum electric field over 5 MV/cm could be sustained. This work marks a significant step toward reaching the promise of a high figure-of-merit in $beta$-Ga2O3.
在具有卤化物气相外延层的大块Ga2O3衬底上展示了高性能$beta$ -Ga203垂直沟槽肖特基势垒二极管(sbd)。击穿电压(BV)为2.44 kV，直流测量Baliga优值(BV2/Ron)为0.39 GW/cm2，脉冲测量Baliga优值(BV2/Ron)为0.45 GW/cm2，均为$beta$ - ga2o3基功率器件中最高的。在翅片宽度为$1-2 mu mathrm{m}$的器件上，由于沟槽SBD结构提供了减少表面场(RESURF)效应，直到击穿为止，反向泄漏电流密度最低，低于$1 mu mathrm{A}/text{cm}^{2}$。比导通电阻随翅片通道面积比的增大而减小，并遵循一个简单的关系。考虑势垒隧穿效应和势垒高度降低效应，反漏电流与模拟结果吻合较好。确定器件击穿发生在沟槽底部角落，在那里可以维持超过5 MV/cm的最大电场。这项工作标志着朝着$beta$ -Ga2O3的高品质数字的承诺迈出了重要的一步。
{"title":"2.44 kV Ga2O3 vertical trench Schottky barrier diodes with very low reverse leakage current","authors":"Wenshen Li, Zongyang Hu, K. Nomoto, R. Jinno, Zexuan Zhang, Thieu Quang Tu, K. Sasaki, A. Kuramata, D. Jena, H. Xing","doi":"10.1109/IEDM.2018.8614693","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614693","url":null,"abstract":"High-performance <tex>$beta$</tex>-Ga203 vertical trench Schottky barrier diodes (SBDs) are demonstrated on bulk Ga<inf>2</inf>O<inf>3</inf> substrates with a halide vapor phase epitaxial layer. A breakdown voltage (BV) of 2.44 kV, Baliga's figure-of-merit (BV<sup>2</sup>/R<inf>on</inf>) of 0.39 GW/cm<sup>2</sup> from DC measurements and 0.45 GW/cm<sup>2</sup> from pulsed measurements are achieved, all of which are the highest among <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf>-based power devices. A lowest reverse leakage current density below <tex>$1 mu mathrm{A}/text{cm}^{2}$</tex> until breakdown is observed on devices with a fin width of <tex>$1-2 mu mathrm{m}$</tex>, thanks to the reduced surface field (RESURF) effect provided by the trench SBD structure. The specific on-resistance is found to reduce with increasing area ratio of the fin-channels following a simple relationship. The reverse leakage current agrees well with simulated results considering the barrier tunneling and barrier height lowering effects. The breakdown of the devices is identified to happen at the trench bottom corner, where a maximum electric field over 5 MV/cm could be sustained. This work marks a significant step toward reaching the promise of a high figure-of-merit in <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf>.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116209493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614662
Xinning Wang, Ranjith Kumar, S. Prakash, Peng Zheng, Tai-Hsuan Wu, Q. Shi, Marni Nabors, Srinivasa Chaitanya Gadigatla, S. Realov, Chin-Hsuan Chen, Ying Zhang, K. Mistry, A. Yeoh, I. Post, C. Auth, A. Madhavan
This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments. The 10nm short height library enables 2.7x transistor density scaling going from 14nm counterpart. The taller height libraries are optimized to meet performance and reliability requirements of Intel's leading edge client/server products. PPA trade-offs are analyzed both at std. cell level and block level on an industry standard Core IP design.
{"title":"Design-Technology Co-Optimization of Standard Cell Libraries on Intel 10nm Process","authors":"Xinning Wang, Ranjith Kumar, S. Prakash, Peng Zheng, Tai-Hsuan Wu, Q. Shi, Marni Nabors, Srinivasa Chaitanya Gadigatla, S. Realov, Chin-Hsuan Chen, Ying Zhang, K. Mistry, A. Yeoh, I. Post, C. Auth, A. Madhavan","doi":"10.1109/IEDM.2018.8614662","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614662","url":null,"abstract":"This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments. The 10nm short height library enables 2.7x transistor density scaling going from 14nm counterpart. The taller height libraries are optimized to meet performance and reliability requirements of Intel's leading edge client/server products. PPA trade-offs are analyzed both at std. cell level and block level on an industry standard Core IP design.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"526 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116220842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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