Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117800
Jiyoung Yoon, Bumgi Lee, Jaehee Song, Bokyoung Kang, Sangho Lee, Doh-Soon Kwak, Heonsang Lim, Ilsang Park, Jonghoon Kim, S. Pae
This paper presents an accelerated stress of product at the wafer level for quality evaluations by performing pre-assessment of stand-by stress-related deteriorations. It is a customized defect-inducing evaluation methodology designed to have consistency with longer term package level test. The test was conducted on 18-nm 8Gb DDR4 DRAM wafers under various time and voltage stress conditions at elevated temperature to find the optimal condition for quality monitoring purpose. Then, the screen-ability was empirically verified through physical failure analysis and statistically verified through Fisher's Exact Test.
{"title":"Customized wafer level verification methodology: quality risk pre-diagnosis with enhanced screen-ability of stand-by stress-related deteriorations","authors":"Jiyoung Yoon, Bumgi Lee, Jaehee Song, Bokyoung Kang, Sangho Lee, Doh-Soon Kwak, Heonsang Lim, Ilsang Park, Jonghoon Kim, S. Pae","doi":"10.1109/IRPS48203.2023.10117800","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117800","url":null,"abstract":"This paper presents an accelerated stress of product at the wafer level for quality evaluations by performing pre-assessment of stand-by stress-related deteriorations. It is a customized defect-inducing evaluation methodology designed to have consistency with longer term package level test. The test was conducted on 18-nm 8Gb DDR4 DRAM wafers under various time and voltage stress conditions at elevated temperature to find the optimal condition for quality monitoring purpose. Then, the screen-ability was empirically verified through physical failure analysis and statistically verified through Fisher's Exact Test.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131519777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118294
F. Maria, F. Balestra, C. Theodorou, G. Ghibaudo, C. Zota, E. Cha
This work studies self-heating effects in InGaAs cryogenic HEMT devices, which aim at the enhancement of control/readout electronics performance in quantum computers. Starting from the well-known method of gate resistance thermometry, documented in literature for its reliable results, we characterized these devices down to deep cryogenic temperatures, namely 10 K, typical of signal-processing electronics for qubits, such as low-noise amplifiers (LNA). We furthermore compared the results with those belonging to far more industrialized silicon technologies (Si FDSOI and bulk), showing exceptional performance of the InGaAs HEMTs thanks to their lack of buried oxide and quantum well structure, which combined with their high electron-mobility, makes them a great study case for the technologies of the future.
{"title":"Experimental Study of Self-Heating Effect in InGaAs HEMTs for Quantum Technologies Down to 10K","authors":"F. Maria, F. Balestra, C. Theodorou, G. Ghibaudo, C. Zota, E. Cha","doi":"10.1109/IRPS48203.2023.10118294","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118294","url":null,"abstract":"This work studies self-heating effects in InGaAs cryogenic HEMT devices, which aim at the enhancement of control/readout electronics performance in quantum computers. Starting from the well-known method of gate resistance thermometry, documented in literature for its reliable results, we characterized these devices down to deep cryogenic temperatures, namely 10 K, typical of signal-processing electronics for qubits, such as low-noise amplifiers (LNA). We furthermore compared the results with those belonging to far more industrialized silicon technologies (Si FDSOI and bulk), showing exceptional performance of the InGaAs HEMTs thanks to their lack of buried oxide and quantum well structure, which combined with their high electron-mobility, makes them a great study case for the technologies of the future.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131298308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117743
Utpreksh Patbhaje, Rupali Verma, J. Kumar, Ansh, M. Shrivastava
MoSe2 is a wonderful ambipolar 2D material that provides a great platform for future electronics but lacks analysis for operation under electrical stress. This work focuses on parameter drifts observed in MoSe2 FETs due to evolution of channel as function of time and applied field during which captured stress current shows increment trends that does not saturate even after 1000 seconds of operation. ID(max) improvement of 42%, VT shifts by 380%, SS improvement by 30% and mobility increment by 33% presents unreliable scenarios in operation. This has been attributed to persistent strain in channel that manifests as improved ordering in channel that points to contact region being susceptible to performance degradation in MoSe2 FETs.
{"title":"Unveiling Field Driven Performance Unreliabilities Governed by Channel Dynamics in MoSe2 FETs","authors":"Utpreksh Patbhaje, Rupali Verma, J. Kumar, Ansh, M. Shrivastava","doi":"10.1109/IRPS48203.2023.10117743","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117743","url":null,"abstract":"MoSe2 is a wonderful ambipolar 2D material that provides a great platform for future electronics but lacks analysis for operation under electrical stress. This work focuses on parameter drifts observed in MoSe2 FETs due to evolution of channel as function of time and applied field during which captured stress current shows increment trends that does not saturate even after 1000 seconds of operation. ID(max) improvement of 42%, VT shifts by 380%, SS improvement by 30% and mobility increment by 33% presents unreliable scenarios in operation. This has been attributed to persistent strain in channel that manifests as improved ordering in channel that points to contact region being susceptible to performance degradation in MoSe2 FETs.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117638
M. Monishmurali, N. K. Kranthi, G. Boselli, M. Shrivastava
Physical insights into the impact of the thin-oxide polysilicon gate on the on-resistance of DeMOS-based HV-PNP are developed using detailed TCAD simulation. Turn-on and eventual failure mechanisms in HV-PNP are discussed. The impact of thin-oxide polysilicon placed over the N-Well and P-Well regions is investigated separately. The physics of regenerative bipolar degradation and its effect of dynamic on-resistance is understood as a function of thin-oxide placement. Furthermore, floating the thin-oxide gate mitigated regenerative bipolar degradation while having a faster lateral PNP trigger, resulting in the best case of on-resistance at all current levels. The insights developed in this work help to design compact high-voltage PNPs.
{"title":"Impact of Thin-oxide Gate on the On-Resistance of HV-PNP Under ESD Stress","authors":"M. Monishmurali, N. K. Kranthi, G. Boselli, M. Shrivastava","doi":"10.1109/IRPS48203.2023.10117638","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117638","url":null,"abstract":"Physical insights into the impact of the thin-oxide polysilicon gate on the on-resistance of DeMOS-based HV-PNP are developed using detailed TCAD simulation. Turn-on and eventual failure mechanisms in HV-PNP are discussed. The impact of thin-oxide polysilicon placed over the N-Well and P-Well regions is investigated separately. The physics of regenerative bipolar degradation and its effect of dynamic on-resistance is understood as a function of thin-oxide placement. Furthermore, floating the thin-oxide gate mitigated regenerative bipolar degradation while having a faster lateral PNP trigger, resulting in the best case of on-resistance at all current levels. The insights developed in this work help to design compact high-voltage PNPs.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126544797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117807
N. Said, K. Harrouche, F. Medjdoub, N. Labat, J. Tartarin, N. Malbert
Downscaling HEMT devices is nowadays substantial to allow their operation in the millimeter wave frequency domain. In this work, the electrical parameters of three different AlN/GaN structures featuring various GaN channel thicknesses were compared. After a DC electrical stabilization procedure, 96 HEMT devices under test exhibit a minor dispersion in DIBL and lag rates, which reflects an undeniable technological mastering and maturity. Evaluation of the sensitivity of devices with different geometries at temperatures of up to 200°C revealed that the gate-drain distance impacts Ron variation and not Idss variation with temperature. We also showed that DIBL at moderate electrical field and the drain lags exhibit athermal behavior; unlike gate lag delays which can be thermally activated and exhibit a linear temperature dependence regardless of the size of the gate length and gate-to-drain distance.
{"title":"Thermal and statistical analysis of various AlN/GaN HEMT geometries for millimeter Wave applications","authors":"N. Said, K. Harrouche, F. Medjdoub, N. Labat, J. Tartarin, N. Malbert","doi":"10.1109/IRPS48203.2023.10117807","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117807","url":null,"abstract":"Downscaling HEMT devices is nowadays substantial to allow their operation in the millimeter wave frequency domain. In this work, the electrical parameters of three different AlN/GaN structures featuring various GaN channel thicknesses were compared. After a DC electrical stabilization procedure, 96 HEMT devices under test exhibit a minor dispersion in DIBL and lag rates, which reflects an undeniable technological mastering and maturity. Evaluation of the sensitivity of devices with different geometries at temperatures of up to 200°C revealed that the gate-drain distance impacts Ron variation and not Idss variation with temperature. We also showed that DIBL at moderate electrical field and the drain lags exhibit athermal behavior; unlike gate lag delays which can be thermally activated and exhibit a linear temperature dependence regardless of the size of the gate length and gate-to-drain distance.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117347597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118099
L. Grenouillet, J. Barbot, J. Laguerre, S. Martin, C. Carabasse, M. Louro, M. Bedjaoui, S. Minoret, S. Kerdilès, C. Boixaderas, T. Magis, C. Jahan, F. Andrieu, J. Coignus
Ferroelectricity in doped HfO2 thin films was reported for the first time 12 years ago, generating strong interest in the non-volatile memory and logic community. Thanks to their CMOS compatibility and potential for scaling, hafnia-based Ferroelectric Random Access Memories (FeRAMs), Ferroelectric Tunnel Junctions (FTJ s) and Ferroelectric Field Effect Transistors (FeFETs) are not only a breakthrough with respect to conventional perovskite-based ferroelectric (FE) devices but also potentially a revolution from an application prospective, in particular considering the non-volatility and intrinsic energy efficiency of these devices. However, their maturity is currently too low to consider practical applications. In this paper, we therefore focus on the reliability assessment of Metal/FE/Metal (MFM) and Metal/FE/Dielectric/Metal (MFDM) stacks, either in the form of large area ferroelectric capacitors, or in the form of kbit arrays integrated in CMOS Back-End of Line.
{"title":"Reliability assessment of hafnia-based ferroelectric devices and arrays for memory and AI applications (Invited)","authors":"L. Grenouillet, J. Barbot, J. Laguerre, S. Martin, C. Carabasse, M. Louro, M. Bedjaoui, S. Minoret, S. Kerdilès, C. Boixaderas, T. Magis, C. Jahan, F. Andrieu, J. Coignus","doi":"10.1109/IRPS48203.2023.10118099","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118099","url":null,"abstract":"Ferroelectricity in doped HfO2 thin films was reported for the first time 12 years ago, generating strong interest in the non-volatile memory and logic community. Thanks to their CMOS compatibility and potential for scaling, hafnia-based Ferroelectric Random Access Memories (FeRAMs), Ferroelectric Tunnel Junctions (FTJ s) and Ferroelectric Field Effect Transistors (FeFETs) are not only a breakthrough with respect to conventional perovskite-based ferroelectric (FE) devices but also potentially a revolution from an application prospective, in particular considering the non-volatility and intrinsic energy efficiency of these devices. However, their maturity is currently too low to consider practical applications. In this paper, we therefore focus on the reliability assessment of Metal/FE/Metal (MFM) and Metal/FE/Dielectric/Metal (MFDM) stacks, either in the form of large area ferroelectric capacitors, or in the form of kbit arrays integrated in CMOS Back-End of Line.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123953395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118305
Ayumu Yamada, Naoko Misawa, C. Matsui, Ken Takeuchi
A CNN-based Fluctuation Pattern Classifier (FPC) is proposed. FPC is fully trained on the artificially created dataset with assumed fluctuation patterns such as random telegraph noise (RTN) and Oxygen Vacancy movement. FPC is applied to the measured ReRAM signals under different write conditions before read cycles and physical models are established based on the classification results. Proposed fluctuation reduction write (FRW) reduces ReRAM fluctuation rate by 35.1% to improve the inference accuracy of neural network.
{"title":"ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset","authors":"Ayumu Yamada, Naoko Misawa, C. Matsui, Ken Takeuchi","doi":"10.1109/IRPS48203.2023.10118305","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118305","url":null,"abstract":"A CNN-based Fluctuation Pattern Classifier (FPC) is proposed. FPC is fully trained on the artificially created dataset with assumed fluctuation patterns such as random telegraph noise (RTN) and Oxygen Vacancy movement. FPC is applied to the measured ReRAM signals under different write conditions before read cycles and physical models are established based on the classification results. Proposed fluctuation reduction write (FRW) reduces ReRAM fluctuation rate by 35.1% to improve the inference accuracy of neural network.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124101111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118247
Yusuf Cinar, Junghoon Kim, Eunho Oh, Sun-Gu Lee, Changsik Kwon, Jonggyu Park
This paper investigates the acoustic noise generation mechanism of solid-state drives (SSD) by analyzing NAND operation and measures variation of voltage, vibration, and acoustic pressure depending on the NAND operation. NAND operation is measured with respect to number of overlapped banks during its operation. It is observed that frequency components of bank interleaving process during the NAND operation affect voltage, vibration, and acoustic pressure variation. It was shown that acoustic noise of SSDs greatly depends on NAND operation.
{"title":"Analysis of SSD Acoustic Noise Generation Mechanism depending on NAND operation","authors":"Yusuf Cinar, Junghoon Kim, Eunho Oh, Sun-Gu Lee, Changsik Kwon, Jonggyu Park","doi":"10.1109/IRPS48203.2023.10118247","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118247","url":null,"abstract":"This paper investigates the acoustic noise generation mechanism of solid-state drives (SSD) by analyzing NAND operation and measures variation of voltage, vibration, and acoustic pressure depending on the NAND operation. NAND operation is measured with respect to number of overlapped banks during its operation. It is observed that frequency components of bank interleaving process during the NAND operation affect voltage, vibration, and acoustic pressure variation. It was shown that acoustic noise of SSDs greatly depends on NAND operation.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117070716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117882
L. Reganaz, D. Deleruyelle, Q. Rafhay, Joel Minguet Lopez, N. Castellani, J. Nodin, A. Bricalli, G. Piccolboni, G. Molas, F. Andrieu
We investigate the impact of ReRAM resistance fluctuations in a 16kb memory array. ReRAM retention and read current fluctuations are the main factors limiting the reliability of the array. A KMC-based 3D simulation framework is introduced for a complete physical description of the observed mechanisms. After individual cell relaxation (up to one second at room temperature) and resistance distribution stabilization, single cell level fluctuations still occur, especially in HRS. Oxygen vacancy migration and recombination, RTN and 1/f noise components contribute to the dynamic evolution. In a first phase, higher and faster current fluctuations are measured due to RTN and Vo low energy migration (1-10min at 25°C). In a second phase, the contribution of Vo migration tends to decrease as they neutralize in clusters or diffuse (> 10min at 25°C). Finally, the impact of individual cell fluctuations on the variability and reliability of memory array is analyzed.
{"title":"Investigation of resistance fluctuations in ReRAM: physical origin, temporal dependence and impact on memory reliability","authors":"L. Reganaz, D. Deleruyelle, Q. Rafhay, Joel Minguet Lopez, N. Castellani, J. Nodin, A. Bricalli, G. Piccolboni, G. Molas, F. Andrieu","doi":"10.1109/IRPS48203.2023.10117882","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117882","url":null,"abstract":"We investigate the impact of ReRAM resistance fluctuations in a 16kb memory array. ReRAM retention and read current fluctuations are the main factors limiting the reliability of the array. A KMC-based 3D simulation framework is introduced for a complete physical description of the observed mechanisms. After individual cell relaxation (up to one second at room temperature) and resistance distribution stabilization, single cell level fluctuations still occur, especially in HRS. Oxygen vacancy migration and recombination, RTN and 1/f noise components contribute to the dynamic evolution. In a first phase, higher and faster current fluctuations are measured due to RTN and Vo low energy migration (1-10min at 25°C). In a second phase, the contribution of Vo migration tends to decrease as they neutralize in clusters or diffuse (> 10min at 25°C). Finally, the impact of individual cell fluctuations on the variability and reliability of memory array is analyzed.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"511 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115126711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118271
Laura Zunarelli, L. Balestra, S. Reggiani, R. Sankaralingam, M. Dissegna, G. Boselli
This paper investigates a method to increase the holding voltage in a conventional Silicon Controlled Rectifier (SCR) for ESD power clamping. Specifically, a SCR-LDMOS device with 150 V trigger voltage and 9 V holding voltage is investigated assuming the application of high-energy electron irradiation. Based on previous experimental and TCAD investigations, the most relevant kind of defects is accounted for at different irradiation levels clearly showing an increase of the holding voltage up to 16 V without any other significant change in the TLP characteristics. The role of trapped charges in the holding regime has been addressed up to the thermal runaway through extensive numerical investigations.
{"title":"TCAD study of the Holding-Voltage Modulation in Irradiated SCR-LDMOS for HV ESD Protection","authors":"Laura Zunarelli, L. Balestra, S. Reggiani, R. Sankaralingam, M. Dissegna, G. Boselli","doi":"10.1109/IRPS48203.2023.10118271","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118271","url":null,"abstract":"This paper investigates a method to increase the holding voltage in a conventional Silicon Controlled Rectifier (SCR) for ESD power clamping. Specifically, a SCR-LDMOS device with 150 V trigger voltage and 9 V holding voltage is investigated assuming the application of high-energy electron irradiation. Based on previous experimental and TCAD investigations, the most relevant kind of defects is accounted for at different irradiation levels clearly showing an increase of the holding voltage up to 16 V without any other significant change in the TLP characteristics. The role of trapped charges in the holding regime has been addressed up to the thermal runaway through extensive numerical investigations.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122687493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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