Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118344
R. Ranjan, P. R. Perepa, Ki-Don Lee, Hokyung Park, Peter Kim, G. Yerubandi, J. Haefner, Caleb Dongkyun Kwon, M. Jin, Wenhao Zhou, H. Shim, Shin-Young Chung
To understand the effect of barrier metal thickness (BM THK) of metal gate (MG) on static random access memory (SRAM) reliability, we evaluated 3 different wafer-level reliability (WLR) methods; random telegraph noise (RTN) characteristics ($tau_{mathrm{c}}/tau_{mathrm{e}}$, or capture/ emission time constant) and BTI recovery are studied on single-bit transistors, and SRAM static noise margin (SNM) degradation is also investigated with various stress configuration. Using three different MG process splits, it is observed that RTN performance is modulated by BM THK. Through BM THK optimization, the best result (i.e., $mathbf{RTN}downarrow$, bias temperature instability (BTI) $mathbf{recovery}uparrow$, SRAM SNM $mathbf{shift}downarrow$) could be achieved, owing to less oxide damage by minimal trapping/de-trapping phenomenon. This clearly indicates the need of subtle process-reliability optimization. In addition, high temperature operating life (HTOL) is performed to confirm the SRAM Vmin shift at package-level test.
{"title":"Impact of Barrier Metal Thickness on SRAM Reliability","authors":"R. Ranjan, P. R. Perepa, Ki-Don Lee, Hokyung Park, Peter Kim, G. Yerubandi, J. Haefner, Caleb Dongkyun Kwon, M. Jin, Wenhao Zhou, H. Shim, Shin-Young Chung","doi":"10.1109/IRPS48203.2023.10118344","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118344","url":null,"abstract":"To understand the effect of barrier metal thickness (BM THK) of metal gate (MG) on static random access memory (SRAM) reliability, we evaluated 3 different wafer-level reliability (WLR) methods; random telegraph noise (RTN) characteristics ($tau_{mathrm{c}}/tau_{mathrm{e}}$, or capture/ emission time constant) and BTI recovery are studied on single-bit transistors, and SRAM static noise margin (SNM) degradation is also investigated with various stress configuration. Using three different MG process splits, it is observed that RTN performance is modulated by BM THK. Through BM THK optimization, the best result (i.e., $mathbf{RTN}downarrow$, bias temperature instability (BTI) $mathbf{recovery}uparrow$, SRAM SNM $mathbf{shift}downarrow$) could be achieved, owing to less oxide damage by minimal trapping/de-trapping phenomenon. This clearly indicates the need of subtle process-reliability optimization. In addition, high temperature operating life (HTOL) is performed to confirm the SRAM Vmin shift at package-level test.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117914
S. Mukhopadhyay, C. Chen, M. Jamil, Jihan Standfest, I. Meric, B. Gill, S. Ramey
Transistor aging under complex input waveform stress has been a key concern for device and circuit reliability. The overall Design Technology Co-Optimization (DTCO) is strongly guided by the reliability risk of a single transistor as well as by the reliability performance of the overall IP/product. Although the IP/Product reliability evaluation is most beneficial at the early stages of the technology development, it is often very expensive, and no certain aging model methodology exists to quantify the risks. In this work, for the first time we demonstrate a unified aging model framework, which not only can predict the traditional DC transistor aging, but also can accurately predict aging in various styles of circuits. Various Ring-Oscillators (RO) under arbitrary stress conditions are used to demonstrate model predictability after long-term stress approaching product use conditions. Such consistent framework helps to guide the process technology development, as well as provides for high-confidence product/IP reliability design assurance.
{"title":"A Unified Aging Model Framework Capturing Device to Circuit Degradation for Advance Technology Nodes","authors":"S. Mukhopadhyay, C. Chen, M. Jamil, Jihan Standfest, I. Meric, B. Gill, S. Ramey","doi":"10.1109/IRPS48203.2023.10117914","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117914","url":null,"abstract":"Transistor aging under complex input waveform stress has been a key concern for device and circuit reliability. The overall Design Technology Co-Optimization (DTCO) is strongly guided by the reliability risk of a single transistor as well as by the reliability performance of the overall IP/product. Although the IP/Product reliability evaluation is most beneficial at the early stages of the technology development, it is often very expensive, and no certain aging model methodology exists to quantify the risks. In this work, for the first time we demonstrate a unified aging model framework, which not only can predict the traditional DC transistor aging, but also can accurately predict aging in various styles of circuits. Various Ring-Oscillators (RO) under arbitrary stress conditions are used to demonstrate model predictability after long-term stress approaching product use conditions. Such consistent framework helps to guide the process technology development, as well as provides for high-confidence product/IP reliability design assurance.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117793
R. Malik, Vipin Joshi, R. R. Chaudhuri, Mehak Ashraf Mir, Zubear Khan, Avinas N. Shaji, Madhura Bhattacharya, Anup T. Vitthal, M. Shrivastava
In this work, we probe the physical mechanism responsible for V th and gate current instability in p-GaN Schottky gated AlGaN/GaN HEMTs. Devices exhibited a negative Vth shift accompanied by a distinct increase in gate current, followed by gate failure, when driven at positive gate over-drives. Temperature and frequency dependent CV analysis is carried out along with capacitive-DL TS measurements to probe and validate the physical mechanism responsible for the observed gate instabilities. Generation of hole traps with an energy level of 0.43e V, in response to gate bias stress is found to trigger gate instability, subsequently leading to device failure.
{"title":"Signatures of Positive Gate Over-Drive Induced Hole Trap Generation and its Impact on p-GaN Gate Stack Instability in AlGaN/GaN HEMTs","authors":"R. Malik, Vipin Joshi, R. R. Chaudhuri, Mehak Ashraf Mir, Zubear Khan, Avinas N. Shaji, Madhura Bhattacharya, Anup T. Vitthal, M. Shrivastava","doi":"10.1109/IRPS48203.2023.10117793","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117793","url":null,"abstract":"In this work, we probe the physical mechanism responsible for V th and gate current instability in p-GaN Schottky gated AlGaN/GaN HEMTs. Devices exhibited a negative Vth shift accompanied by a distinct increase in gate current, followed by gate failure, when driven at positive gate over-drives. Temperature and frequency dependent CV analysis is carried out along with capacitive-DL TS measurements to probe and validate the physical mechanism responsible for the observed gate instabilities. Generation of hole traps with an energy level of 0.43e V, in response to gate bias stress is found to trigger gate instability, subsequently leading to device failure.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130129063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117636
Viktor Dudash, K. Machani, B. Boehme, S. Capecchi, Jungtae Ok, K. Meier, F. Kuechenmeister, M. Wieland, K. Bock
In this study a Finite Element Model (FEM) was designed in order to predict the reliability behavior of 7×7 mm2 Wafer Level Chip Scale Packages (WLCSP) during board level thermal cycling tests, considering different solder material models for SAC405 and SACQ interconnects. A significant difference in plastic strains within the package was observed for a variety of solder material models: Compared to SACQ interconnects an approximate 70% plastic strain increase in solder and a 35% plastic strain reduction in the polyimide passivation layer was observed for packages with SAC405 interconnects. Simulations were verified by experimental thermal cycling test data done at board level. During thermal cycling, packages showed different failure modes depending on the interconnect material used in the package. Also, SAC405 showed earlier failure. Maximum strain obtained from simulations was used as an indicator of potential failure locations for the solder alloy and polyimide layer. The proposed model setup enables precise simulation results, which are well aligned with the actual experimental findings on the behavior of WLCSP with SAC405 and SACQ interconnects.
{"title":"Wafer Level Chip Scale Package Failure Mode Prediction using Finite Element Modeling","authors":"Viktor Dudash, K. Machani, B. Boehme, S. Capecchi, Jungtae Ok, K. Meier, F. Kuechenmeister, M. Wieland, K. Bock","doi":"10.1109/IRPS48203.2023.10117636","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117636","url":null,"abstract":"In this study a Finite Element Model (FEM) was designed in order to predict the reliability behavior of 7×7 mm2 Wafer Level Chip Scale Packages (WLCSP) during board level thermal cycling tests, considering different solder material models for SAC405 and SACQ interconnects. A significant difference in plastic strains within the package was observed for a variety of solder material models: Compared to SACQ interconnects an approximate 70% plastic strain increase in solder and a 35% plastic strain reduction in the polyimide passivation layer was observed for packages with SAC405 interconnects. Simulations were verified by experimental thermal cycling test data done at board level. During thermal cycling, packages showed different failure modes depending on the interconnect material used in the package. Also, SAC405 showed earlier failure. Maximum strain obtained from simulations was used as an indicator of potential failure locations for the solder alloy and polyimide layer. The proposed model setup enables precise simulation results, which are well aligned with the actual experimental findings on the behavior of WLCSP with SAC405 and SACQ interconnects.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130482077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118173
S. Moreau, D. Bouchu, J. Jourdon, B. Ayoub, S. Lhostis, H. Frémont, P. Lamontagne
With hybrid bonding (HB) pitch reduction, many challenges are arising. One of them is related to the reliability of HB-based interconnects and in particular their electromigration performances as electromigration (EM)-related degradation is intimately linked to the electrical current in addition to temperature and mechanical stresses. This study highlights a change in the failure modes for EM-related failures in HB-based interconnects when decreasing the interconnect pitch from 6.84 down to 1.44 µm. The weakest link moves from the BEOL levels to hybrid bonding ones but without affecting the projected performance under use conditions. Additional studies done on design aspects do not evidence any negative impact on the electro migration resistance of the HB brick.
{"title":"Recent Advances on Electromigration in Cu/SiO2 to Cu/SiO2 Hybrid Bonds for 3D Integrated Circuits","authors":"S. Moreau, D. Bouchu, J. Jourdon, B. Ayoub, S. Lhostis, H. Frémont, P. Lamontagne","doi":"10.1109/IRPS48203.2023.10118173","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118173","url":null,"abstract":"With hybrid bonding (HB) pitch reduction, many challenges are arising. One of them is related to the reliability of HB-based interconnects and in particular their electromigration performances as electromigration (EM)-related degradation is intimately linked to the electrical current in addition to temperature and mechanical stresses. This study highlights a change in the failure modes for EM-related failures in HB-based interconnects when decreasing the interconnect pitch from 6.84 down to 1.44 µm. The weakest link moves from the BEOL levels to hybrid bonding ones but without affecting the projected performance under use conditions. Additional studies done on design aspects do not evidence any negative impact on the electro migration resistance of the HB brick.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129753331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117833
E. Murakami, T. Takeshita, K. Oda, M. Kobayashi, K. Asayama, M. Okamoto
SiC-MOSFETs with high reliability have been desired for electric vehicles. We classify commercial SiC-MOSFETs into “heavily nitrided” and “lightly nitrided” based on time-dependent gate-current characteristics of fabricated devices. In “heavily nitrided” devices for higher mobility, high-voltage gate pulse for screening of B-mode (extrinsic defects) causes hole-trapping near the SiO2/SiC interface through impact ionization. This phenomenon leads to an increase in gate current as well as a negative shift of threshold voltage. Moreover, this is enhanced at low temperatures (-60, 25°C). Thus, high-temperature (200°C) screening is preferable. In addition, the relation between Weibull slopes for time-to-breakdown and charge-to-breakdown is closely examined.
{"title":"Classification of Commercial SiC-MOSFETs Based on Time-Dependent Gate-current Characteristics","authors":"E. Murakami, T. Takeshita, K. Oda, M. Kobayashi, K. Asayama, M. Okamoto","doi":"10.1109/IRPS48203.2023.10117833","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117833","url":null,"abstract":"SiC-MOSFETs with high reliability have been desired for electric vehicles. We classify commercial SiC-MOSFETs into “heavily nitrided” and “lightly nitrided” based on time-dependent gate-current characteristics of fabricated devices. In “heavily nitrided” devices for higher mobility, high-voltage gate pulse for screening of B-mode (extrinsic defects) causes hole-trapping near the SiO2/SiC interface through impact ionization. This phenomenon leads to an increase in gate current as well as a negative shift of threshold voltage. Moreover, this is enhanced at low temperatures (-60, 25°C). Thus, high-temperature (200°C) screening is preferable. In addition, the relation between Weibull slopes for time-to-breakdown and charge-to-breakdown is closely examined.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121235752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117818
C. Bogner, C. Schlünder, M. Waltl, H. Reisinger, T. Grasser
One of the major challenges for modeling BTI degradation in modern technology nodes and deeply scaled transistors is the occurrence of significant time dependent variability (TDV). This means that due to the sparsity of defects, the impact of single defects as well as variation in the number of defects per device need to be taken into consideration. We present a modeling approach based on physical principles to describe both mean parameter degradation as well as TDV. Our approach is based on activation energy maps combined with an exponential-Poisson model in order to capture variability. For parameter extraction a combination of ultra fast measurements on large area transistors and transistor array measurements are applied. Thereby, ultra fast measurements have the capability to make a wide range of capture-/emission times experimentally accessible, improving the confidence of the extracted activation energy map. On the other hand, transistor arrays have proven to be the ideal test vehicle to efficiently measure an ensemble of transistors and to asses TDV.
{"title":"Modeling of NBTI Induced Threshold Voltage Shift Based on Activation Energy Maps Under Consideration of Variability","authors":"C. Bogner, C. Schlünder, M. Waltl, H. Reisinger, T. Grasser","doi":"10.1109/IRPS48203.2023.10117818","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117818","url":null,"abstract":"One of the major challenges for modeling BTI degradation in modern technology nodes and deeply scaled transistors is the occurrence of significant time dependent variability (TDV). This means that due to the sparsity of defects, the impact of single defects as well as variation in the number of defects per device need to be taken into consideration. We present a modeling approach based on physical principles to describe both mean parameter degradation as well as TDV. Our approach is based on activation energy maps combined with an exponential-Poisson model in order to capture variability. For parameter extraction a combination of ultra fast measurements on large area transistors and transistor array measurements are applied. Thereby, ultra fast measurements have the capability to make a wide range of capture-/emission times experimentally accessible, improving the confidence of the extracted activation energy map. On the other hand, transistor arrays have proven to be the ideal test vehicle to efficiently measure an ensemble of transistors and to asses TDV.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115185428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117918
Sunil Rathore, Rajeewa Kumar Jaisawal, P. Kondekar, N. Gandhi, Shashank Banchhor, Young Suh Song, N. Bagga
Internal and external process variations severely affect the device threshold voltage $(mathrm{V}_{text{th}})$ and, in turn, the device's reliability. For the first time, this paper presented a thorough analysis of the self-heating aware $mathrm{V}_{text{th}}$ variation of a Nanosheet FET and, thus, the device's aging. Using well-calibrated TCAD models, we evaluated the 'change in $V_{th} ^{prime}$ and performed an extensive design space exploration to analyze: (i) the impact of work function (WF) modulation owing to metal grain sizes and effective grains (for confined dimensions) on $mathrm{V}_{text{th}}$ variation; (ii) the impact of ambient temperature (TA) on $mathrm{V}_{text{th}}$ variation; (iii) the influence of trap charges on device characteristics; (iv) how the consideration of RDF impacted $mathrm{V}_{text{th}};$ (v) the device's aging, i.e., end of a lifetime (EOL). These investigations provided guidelines for designing a reliable Nanosheet FET (NSFET) to investigate and mitigate early aging.
{"title":"Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET","authors":"Sunil Rathore, Rajeewa Kumar Jaisawal, P. Kondekar, N. Gandhi, Shashank Banchhor, Young Suh Song, N. Bagga","doi":"10.1109/IRPS48203.2023.10117918","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117918","url":null,"abstract":"Internal and external process variations severely affect the device threshold voltage $(mathrm{V}_{text{th}})$ and, in turn, the device's reliability. For the first time, this paper presented a thorough analysis of the self-heating aware $mathrm{V}_{text{th}}$ variation of a Nanosheet FET and, thus, the device's aging. Using well-calibrated TCAD models, we evaluated the 'change in $V_{th} ^{prime}$ and performed an extensive design space exploration to analyze: (i) the impact of work function (WF) modulation owing to metal grain sizes and effective grains (for confined dimensions) on $mathrm{V}_{text{th}}$ variation; (ii) the impact of ambient temperature (TA) on $mathrm{V}_{text{th}}$ variation; (iii) the influence of trap charges on device characteristics; (iv) how the consideration of RDF impacted $mathrm{V}_{text{th}};$ (v) the device's aging, i.e., end of a lifetime (EOL). These investigations provided guidelines for designing a reliable Nanosheet FET (NSFET) to investigate and mitigate early aging.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115241653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118286
Om. Prakash, K. Ni, H. Amrouch
In this work, we applied the dual-port concept to decouple the trade-off between the Ferroelectric (FE) thickness $(t_{FE})$ scaling and Memory Window (MW) in the amorphous channel ferroelectric FET (FeFET) for monolithic 3D BEOL integration. To prove the effectiveness of the proposed device structure and explore design space, we developed a fully cali-brated TCAD model and applied it to the amorphous channel FeFET study. We demonstrate the MW in two different scenarios: (i) write and read from the front gate, and (ii) write from the front gate and read from the back gate. We show the $t_{FE}$ and channel length scaling possibility in the second scenario, as well as the possibility for the multi-bit FeFET memory application.
{"title":"Monolithic 3D Integrated BEOL Dual-Port Ferroelectric FET to Break the Tradeoff Between the Memory Window and the Ferroelectric Thickness","authors":"Om. Prakash, K. Ni, H. Amrouch","doi":"10.1109/IRPS48203.2023.10118286","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118286","url":null,"abstract":"In this work, we applied the dual-port concept to decouple the trade-off between the Ferroelectric (FE) thickness $(t_{FE})$ scaling and Memory Window (MW) in the amorphous channel ferroelectric FET (FeFET) for monolithic 3D BEOL integration. To prove the effectiveness of the proposed device structure and explore design space, we developed a fully cali-brated TCAD model and applied it to the amorphous channel FeFET study. We demonstrate the MW in two different scenarios: (i) write and read from the front gate, and (ii) write from the front gate and read from the back gate. We show the $t_{FE}$ and channel length scaling possibility in the second scenario, as well as the possibility for the multi-bit FeFET memory application.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115803106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118091
Dongyoung Kim, Skylar DeBoer, Stephen A. Mancini, S. Isukapati, Justin Lynch, Nick Yun, Adam J. Morgan, S. Jang, Woongje Sung
This paper reports static, dynamic, and short-circuit characteristics of split-gate (SG) 1.2 kV 4H-SiC MOSFETs. Conventional (C) MOSFETs and SG-MOSFETs were fabricated and evaluated. Identical conduction behaviors were achieved due to them having the same cell pitch. Although the maximum electric field in the gate oxide is higher in the SG-MOSFETs, this both device architectures obtained similar breakdown voltages with low leakage current. Due to the structure of the split-gate, the reverse capacitance $(mathbf{C}_{mathbf{rss}})$ was reduced by 32 % when compared to conventional MOSFETs. As a result, switching loss for turn-on and turn-off transients was reduced, and thus total switching loss was reduced by 25 % in the SG- M OSFE Ts. Finally, the short-circuit (SC) ruggedness of the MOSFETs were evaluated. Even though the maximum drain current is higher in the SG-MOSFETs, under SC condition, a similar short-circuit withstand time (SCWT) was obtained. In order to further investigate short-circuit characteristics, non-isothermal simulations were conducted. It was discovered that there is no issue with the exposed edge of the gate in SG- M OSFE Ts under SC conditions despite the high electric field in gate oxide. Significantly reduced energy loss was achieved in the SG-MOSFETs with no compromise in static and short-circuit characteristics compared to the conventional MOSFETs.
本文报道了分栅(SG) 1.2 kV 4H-SiC mosfet的静态、动态和短路特性。制备并评价了常规(C) mosfet和sg - mosfet。由于它们具有相同的细胞间距，因此实现了相同的传导行为。虽然栅极氧化物中的最大电场在sg - mosfet中较高，但这两种器件架构获得了相似的击穿电压和低泄漏电流。由于分栅结构，与传统mosfet相比，反向电容$(mathbf{C}_{mathbf{rss}})$减少了32%。结果，降低了导通和关断瞬态的开关损耗，从而使SG- M mosfet的总开关损耗降低了25%。最后，对mosfet的短路(SC)耐用性进行了评估。尽管sg - mosfet的最大漏极电流更高，但在SC条件下，可以获得相似的耐短路时间(SCWT)。为了进一步研究短路特性，进行了非等温模拟。研究发现，在SC条件下，尽管栅极氧化物中存在高电场，但SG- M OSFE晶体管栅极的外露边缘没有问题。与传统的mosfet相比，sg - mosfet在静态和短路特性方面没有妥协，显著降低了能量损失。
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